^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ADXL345/346 Three-Axis Digital Accelerometers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Enter bugs at http://blackfin.uclinux.org/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2009 Michael Hennerich, Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/input/adxl34x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "adxl34x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* ADXL345/6 Register Map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DEVID 0x00 /* R Device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define THRESH_TAP 0x1D /* R/W Tap threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OFSX 0x1E /* R/W X-axis offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OFSY 0x1F /* R/W Y-axis offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OFSZ 0x20 /* R/W Z-axis offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DUR 0x21 /* R/W Tap duration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LATENT 0x22 /* R/W Tap latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define WINDOW 0x23 /* R/W Tap window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define THRESH_ACT 0x24 /* R/W Activity threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define THRESH_INACT 0x25 /* R/W Inactivity threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TIME_INACT 0x26 /* R/W Inactivity time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ACT_INACT_CTL 0x27 /* R/W Axis enable control for activity and */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* inactivity detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define THRESH_FF 0x28 /* R/W Free-fall threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TIME_FF 0x29 /* R/W Free-fall time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TAP_AXES 0x2A /* R/W Axis control for tap/double tap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ACT_TAP_STATUS 0x2B /* R Source of tap/double tap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BW_RATE 0x2C /* R/W Data rate and power mode control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define POWER_CTL 0x2D /* R/W Power saving features control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define INT_ENABLE 0x2E /* R/W Interrupt enable control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define INT_MAP 0x2F /* R/W Interrupt mapping control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define INT_SOURCE 0x30 /* R Source of interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DATA_FORMAT 0x31 /* R/W Data format control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DATAX0 0x32 /* R X-Axis Data 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DATAX1 0x33 /* R X-Axis Data 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DATAY0 0x34 /* R Y-Axis Data 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DATAY1 0x35 /* R Y-Axis Data 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DATAZ0 0x36 /* R Z-Axis Data 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DATAZ1 0x37 /* R Z-Axis Data 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define FIFO_CTL 0x38 /* R/W FIFO control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define FIFO_STATUS 0x39 /* R FIFO status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TAP_SIGN 0x3A /* R Sign and source for tap/double tap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Orientation ADXL346 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ORIENT_CONF 0x3B /* R/W Orientation configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ORIENT 0x3C /* R Orientation status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* DEVIDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ID_ADXL345 0xE5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ID_ADXL346 0xE6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* INT_ENABLE/INT_MAP/INT_SOURCE Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DATA_READY (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SINGLE_TAP (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DOUBLE_TAP (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ACTIVITY (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define INACTIVITY (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define FREE_FALL (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define WATERMARK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OVERRUN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* ACT_INACT_CONTROL Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ACT_ACDC (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ACT_X_EN (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ACT_Y_EN (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ACT_Z_EN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define INACT_ACDC (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define INACT_X_EN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define INACT_Y_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define INACT_Z_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* TAP_AXES Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SUPPRESS (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TAP_X_EN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TAP_Y_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TAP_Z_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* ACT_TAP_STATUS Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ACT_X_SRC (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ACT_Y_SRC (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ACT_Z_SRC (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ASLEEP (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TAP_X_SRC (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TAP_Y_SRC (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TAP_Z_SRC (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* BW_RATE Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define LOW_POWER (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RATE(x) ((x) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* POWER_CTL Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PCTL_LINK (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PCTL_AUTO_SLEEP (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PCTL_MEASURE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PCTL_SLEEP (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PCTL_WAKEUP(x) ((x) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* DATA_FORMAT Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SELF_TEST (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SPI (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define INT_INVERT (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define FULL_RES (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define JUSTIFY (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RANGE(x) ((x) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RANGE_PM_2g 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RANGE_PM_4g 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RANGE_PM_8g 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define RANGE_PM_16g 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * Maximum value our axis may get in full res mode for the input device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * (signed 13 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ADXL_FULLRES_MAX_VAL 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Maximum value our axis may get in fixed res mode for the input device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * (signed 10 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ADXL_FIXEDRES_MAX_VAL 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* FIFO_CTL Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define FIFO_MODE(x) (((x) & 0x3) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define FIFO_BYPASS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define FIFO_FIFO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define FIFO_STREAM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define FIFO_TRIGGER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TRIGGER (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SAMPLES(x) ((x) & 0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* FIFO_STATUS Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define FIFO_TRIG (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define ENTRIES(x) ((x) & 0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* TAP_SIGN Bits ADXL346 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define XSIGN (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define YSIGN (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ZSIGN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define XTAP (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define YTAP (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ZTAP (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* ORIENT_CONF ADXL346 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ORIENT_DEADZONE(x) (((x) & 0x7) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ORIENT_DIVISOR(x) ((x) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* ORIENT ADXL346 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ADXL346_2D_VALID (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ADXL346_2D_ORIENT(x) (((x) & 0x30) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define ADXL346_3D_VALID (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ADXL346_3D_ORIENT(x) ((x) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define ADXL346_2D_PORTRAIT_POS 0 /* +X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define ADXL346_2D_PORTRAIT_NEG 1 /* -X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define ADXL346_2D_LANDSCAPE_POS 2 /* +Y */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define ADXL346_2D_LANDSCAPE_NEG 3 /* -Y */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ADXL346_3D_FRONT 3 /* +X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ADXL346_3D_BACK 4 /* -X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ADXL346_3D_RIGHT 2 /* +Y */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ADXL346_3D_LEFT 5 /* -Y */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ADXL346_3D_TOP 1 /* +Z */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define ADXL346_3D_BOTTOM 6 /* -Z */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #undef ADXL_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define ADXL_X_AXIS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define ADXL_Y_AXIS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define ADXL_Z_AXIS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define AC_READ(ac, reg) ((ac)->bops->read((ac)->dev, reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define AC_WRITE(ac, reg, val) ((ac)->bops->write((ac)->dev, reg, val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct axis_triple {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int z;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct adxl34x {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct input_dev *input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct mutex mutex; /* reentrant protection for struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct adxl34x_platform_data pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct axis_triple swcal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct axis_triple hwcal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct axis_triple saved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) char phys[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned orient2d_saved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned orient3d_saved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) bool disabled; /* P: mutex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) bool opened; /* P: mutex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) bool suspended; /* P: mutex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) bool fifo_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) const struct adxl34x_bus_ops *bops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const struct adxl34x_platform_data adxl34x_default_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .tap_threshold = 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .tap_duration = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .tap_latency = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .tap_window = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .act_axis_control = 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .activity_threshold = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .inactivity_threshold = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .inactivity_time = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .free_fall_threshold = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .free_fall_time = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .data_rate = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .data_range = ADXL_FULL_RES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .ev_type = EV_ABS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .ev_code_x = ABS_X, /* EV_REL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .ev_code_y = ABS_Y, /* EV_REL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .ev_code_z = ABS_Z, /* EV_REL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY {x,y,z} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .fifo_mode = ADXL_FIFO_STREAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .watermark = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static void adxl34x_get_triple(struct adxl34x *ac, struct axis_triple *axis)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) short buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ac->bops->read_block(ac->dev, DATAX0, DATAZ1 - DATAX0 + 1, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) mutex_lock(&ac->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ac->saved.x = (s16) le16_to_cpu(buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) axis->x = ac->saved.x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ac->saved.y = (s16) le16_to_cpu(buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) axis->y = ac->saved.y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ac->saved.z = (s16) le16_to_cpu(buf[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) axis->z = ac->saved.z;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) mutex_unlock(&ac->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static void adxl34x_service_ev_fifo(struct adxl34x *ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct adxl34x_platform_data *pdata = &ac->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct axis_triple axis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) adxl34x_get_triple(ac, &axis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) input_event(ac->input, pdata->ev_type, pdata->ev_code_x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) axis.x - ac->swcal.x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) input_event(ac->input, pdata->ev_type, pdata->ev_code_y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) axis.y - ac->swcal.y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) input_event(ac->input, pdata->ev_type, pdata->ev_code_z,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) axis.z - ac->swcal.z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static void adxl34x_report_key_single(struct input_dev *input, int key)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) input_report_key(input, key, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) input_sync(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) input_report_key(input, key, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static void adxl34x_send_key_events(struct adxl34x *ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct adxl34x_platform_data *pdata, int status, int press)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) for (i = ADXL_X_AXIS; i <= ADXL_Z_AXIS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (status & (1 << (ADXL_Z_AXIS - i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) input_report_key(ac->input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) pdata->ev_code_tap[i], press);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static void adxl34x_do_tap(struct adxl34x *ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct adxl34x_platform_data *pdata, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) adxl34x_send_key_events(ac, pdata, status, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) input_sync(ac->input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) adxl34x_send_key_events(ac, pdata, status, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static irqreturn_t adxl34x_irq(int irq, void *handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct adxl34x *ac = handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct adxl34x_platform_data *pdata = &ac->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int int_stat, tap_stat, samples, orient, orient_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * ACT_TAP_STATUS should be read before clearing the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * Avoid reading ACT_TAP_STATUS in case TAP detection is disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (pdata->tap_axis_control & (TAP_X_EN | TAP_Y_EN | TAP_Z_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) tap_stat = AC_READ(ac, ACT_TAP_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) tap_stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int_stat = AC_READ(ac, INT_SOURCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (int_stat & FREE_FALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) adxl34x_report_key_single(ac->input, pdata->ev_code_ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (int_stat & OVERRUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dev_dbg(ac->dev, "OVERRUN\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (int_stat & (SINGLE_TAP | DOUBLE_TAP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) adxl34x_do_tap(ac, pdata, tap_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (int_stat & DOUBLE_TAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) adxl34x_do_tap(ac, pdata, tap_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (pdata->ev_code_act_inactivity) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (int_stat & ACTIVITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) input_report_key(ac->input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) pdata->ev_code_act_inactivity, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (int_stat & INACTIVITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) input_report_key(ac->input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) pdata->ev_code_act_inactivity, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * ORIENTATION SENSING ADXL346 only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (pdata->orientation_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) orient = AC_READ(ac, ORIENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if ((pdata->orientation_enable & ADXL_EN_ORIENTATION_2D) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) (orient & ADXL346_2D_VALID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) orient_code = ADXL346_2D_ORIENT(orient);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* Report orientation only when it changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (ac->orient2d_saved != orient_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ac->orient2d_saved = orient_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) adxl34x_report_key_single(ac->input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) pdata->ev_codes_orient_2d[orient_code]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if ((pdata->orientation_enable & ADXL_EN_ORIENTATION_3D) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) (orient & ADXL346_3D_VALID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) orient_code = ADXL346_3D_ORIENT(orient) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* Report orientation only when it changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (ac->orient3d_saved != orient_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ac->orient3d_saved = orient_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) adxl34x_report_key_single(ac->input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) pdata->ev_codes_orient_3d[orient_code]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (int_stat & (DATA_READY | WATERMARK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (pdata->fifo_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) samples = ENTRIES(AC_READ(ac, FIFO_STATUS)) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) samples = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) for (; samples > 0; samples--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) adxl34x_service_ev_fifo(ac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * To ensure that the FIFO has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * completely popped, there must be at least 5 us between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * the end of reading the data registers, signified by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * transition to register 0x38 from 0x37 or the CS pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * going high, and the start of new reads of the FIFO or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * reading the FIFO_STATUS register. For SPI operation at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * 1.5 MHz or lower, the register addressing portion of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * transmission is sufficient delay to ensure the FIFO has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * completely popped. It is necessary for SPI operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * greater than 1.5 MHz to de-assert the CS pin to ensure a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * total of 5 us, which is at most 3.4 us at 5 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (ac->fifo_delay && (samples > 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) udelay(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) input_sync(ac->input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static void __adxl34x_disable(struct adxl34x *ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * A '0' places the ADXL34x into standby mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * with minimum power consumption.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) AC_WRITE(ac, POWER_CTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static void __adxl34x_enable(struct adxl34x *ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) AC_WRITE(ac, POWER_CTL, ac->pdata.power_mode | PCTL_MEASURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) void adxl34x_suspend(struct adxl34x *ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) mutex_lock(&ac->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (!ac->suspended && !ac->disabled && ac->opened)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) __adxl34x_disable(ac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ac->suspended = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) mutex_unlock(&ac->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) EXPORT_SYMBOL_GPL(adxl34x_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) void adxl34x_resume(struct adxl34x *ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) mutex_lock(&ac->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (ac->suspended && !ac->disabled && ac->opened)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) __adxl34x_enable(ac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ac->suspended = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) mutex_unlock(&ac->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) EXPORT_SYMBOL_GPL(adxl34x_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static ssize_t adxl34x_disable_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct adxl34x *ac = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return sprintf(buf, "%u\n", ac->disabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static ssize_t adxl34x_disable_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct adxl34x *ac = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) error = kstrtouint(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) mutex_lock(&ac->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (!ac->suspended && ac->opened) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (!ac->disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) __adxl34x_disable(ac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (ac->disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) __adxl34x_enable(ac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ac->disabled = !!val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) mutex_unlock(&ac->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static DEVICE_ATTR(disable, 0664, adxl34x_disable_show, adxl34x_disable_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static ssize_t adxl34x_calibrate_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct adxl34x *ac = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ssize_t count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) mutex_lock(&ac->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) count = sprintf(buf, "%d,%d,%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ac->hwcal.x * 4 + ac->swcal.x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ac->hwcal.y * 4 + ac->swcal.y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ac->hwcal.z * 4 + ac->swcal.z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) mutex_unlock(&ac->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static ssize_t adxl34x_calibrate_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct adxl34x *ac = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * Hardware offset calibration has a resolution of 15.6 mg/LSB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * We use HW calibration and handle the remaining bits in SW. (4mg/LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) mutex_lock(&ac->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ac->hwcal.x -= (ac->saved.x / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) ac->swcal.x = ac->saved.x % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ac->hwcal.y -= (ac->saved.y / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ac->swcal.y = ac->saved.y % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ac->hwcal.z -= (ac->saved.z / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ac->swcal.z = ac->saved.z % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) AC_WRITE(ac, OFSX, (s8) ac->hwcal.x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) AC_WRITE(ac, OFSY, (s8) ac->hwcal.y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) AC_WRITE(ac, OFSZ, (s8) ac->hwcal.z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) mutex_unlock(&ac->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static DEVICE_ATTR(calibrate, 0664,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) adxl34x_calibrate_show, adxl34x_calibrate_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static ssize_t adxl34x_rate_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct adxl34x *ac = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return sprintf(buf, "%u\n", RATE(ac->pdata.data_rate));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static ssize_t adxl34x_rate_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct adxl34x *ac = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) error = kstrtou8(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) mutex_lock(&ac->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ac->pdata.data_rate = RATE(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) AC_WRITE(ac, BW_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ac->pdata.data_rate |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) (ac->pdata.low_power_mode ? LOW_POWER : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) mutex_unlock(&ac->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static DEVICE_ATTR(rate, 0664, adxl34x_rate_show, adxl34x_rate_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static ssize_t adxl34x_autosleep_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct adxl34x *ac = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return sprintf(buf, "%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ac->pdata.power_mode & (PCTL_AUTO_SLEEP | PCTL_LINK) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static ssize_t adxl34x_autosleep_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct adxl34x *ac = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) error = kstrtouint(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) mutex_lock(&ac->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ac->pdata.power_mode |= (PCTL_AUTO_SLEEP | PCTL_LINK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ac->pdata.power_mode &= ~(PCTL_AUTO_SLEEP | PCTL_LINK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (!ac->disabled && !ac->suspended && ac->opened)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) AC_WRITE(ac, POWER_CTL, ac->pdata.power_mode | PCTL_MEASURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) mutex_unlock(&ac->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static DEVICE_ATTR(autosleep, 0664,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) adxl34x_autosleep_show, adxl34x_autosleep_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static ssize_t adxl34x_position_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct adxl34x *ac = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ssize_t count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) mutex_lock(&ac->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) count = sprintf(buf, "(%d, %d, %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ac->saved.x, ac->saved.y, ac->saved.z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) mutex_unlock(&ac->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static DEVICE_ATTR(position, S_IRUGO, adxl34x_position_show, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #ifdef ADXL_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static ssize_t adxl34x_write_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct adxl34x *ac = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * This allows basic ADXL register write access for debug purposes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) error = kstrtouint(buf, 16, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) mutex_lock(&ac->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) AC_WRITE(ac, val >> 8, val & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) mutex_unlock(&ac->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static DEVICE_ATTR(write, 0664, NULL, adxl34x_write_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static struct attribute *adxl34x_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) &dev_attr_disable.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) &dev_attr_calibrate.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) &dev_attr_rate.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) &dev_attr_autosleep.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) &dev_attr_position.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #ifdef ADXL_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) &dev_attr_write.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static const struct attribute_group adxl34x_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .attrs = adxl34x_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static int adxl34x_input_open(struct input_dev *input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct adxl34x *ac = input_get_drvdata(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) mutex_lock(&ac->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (!ac->suspended && !ac->disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) __adxl34x_enable(ac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ac->opened = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) mutex_unlock(&ac->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static void adxl34x_input_close(struct input_dev *input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct adxl34x *ac = input_get_drvdata(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) mutex_lock(&ac->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (!ac->suspended && !ac->disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) __adxl34x_disable(ac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) ac->opened = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) mutex_unlock(&ac->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct adxl34x *adxl34x_probe(struct device *dev, int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) bool fifo_delay_default,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) const struct adxl34x_bus_ops *bops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct adxl34x *ac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct input_dev *input_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) const struct adxl34x_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) int err, range, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) int revid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (!irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) dev_err(dev, "no IRQ?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) ac = kzalloc(sizeof(*ac), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) input_dev = input_allocate_device();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (!ac || !input_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) goto err_free_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ac->fifo_delay = fifo_delay_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) "No platform data: Using default initialization\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) pdata = &adxl34x_default_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) ac->pdata = *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) pdata = &ac->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ac->input = input_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ac->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ac->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) ac->bops = bops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) mutex_init(&ac->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) input_dev->name = "ADXL34x accelerometer";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) revid = AC_READ(ac, DEVID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) switch (revid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) case ID_ADXL345:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ac->model = 345;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) case ID_ADXL346:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ac->model = 346;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) dev_err(dev, "Failed to probe %s\n", input_dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) goto err_free_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) snprintf(ac->phys, sizeof(ac->phys), "%s/input0", dev_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) input_dev->phys = ac->phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) input_dev->dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) input_dev->id.product = ac->model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) input_dev->id.bustype = bops->bustype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) input_dev->open = adxl34x_input_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) input_dev->close = adxl34x_input_close;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) input_set_drvdata(input_dev, ac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) __set_bit(ac->pdata.ev_type, input_dev->evbit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (ac->pdata.ev_type == EV_REL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) __set_bit(REL_X, input_dev->relbit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) __set_bit(REL_Y, input_dev->relbit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) __set_bit(REL_Z, input_dev->relbit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /* EV_ABS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) __set_bit(ABS_X, input_dev->absbit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) __set_bit(ABS_Y, input_dev->absbit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) __set_bit(ABS_Z, input_dev->absbit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (pdata->data_range & FULL_RES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) range = ADXL_FULLRES_MAX_VAL; /* Signed 13-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) range = ADXL_FIXEDRES_MAX_VAL; /* Signed 10-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) input_set_abs_params(input_dev, ABS_X, -range, range, 3, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) input_set_abs_params(input_dev, ABS_Y, -range, range, 3, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) input_set_abs_params(input_dev, ABS_Z, -range, range, 3, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) __set_bit(EV_KEY, input_dev->evbit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) __set_bit(pdata->ev_code_tap[ADXL_X_AXIS], input_dev->keybit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) __set_bit(pdata->ev_code_tap[ADXL_Y_AXIS], input_dev->keybit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) __set_bit(pdata->ev_code_tap[ADXL_Z_AXIS], input_dev->keybit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (pdata->ev_code_ff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) ac->int_mask = FREE_FALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) __set_bit(pdata->ev_code_ff, input_dev->keybit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (pdata->ev_code_act_inactivity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) __set_bit(pdata->ev_code_act_inactivity, input_dev->keybit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ac->int_mask |= ACTIVITY | INACTIVITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (pdata->watermark) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) ac->int_mask |= WATERMARK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (FIFO_MODE(pdata->fifo_mode) == FIFO_BYPASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ac->pdata.fifo_mode |= FIFO_STREAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) ac->int_mask |= DATA_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (pdata->tap_axis_control & (TAP_X_EN | TAP_Y_EN | TAP_Z_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ac->int_mask |= SINGLE_TAP | DOUBLE_TAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (FIFO_MODE(pdata->fifo_mode) == FIFO_BYPASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ac->fifo_delay = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) AC_WRITE(ac, POWER_CTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) err = request_threaded_irq(ac->irq, NULL, adxl34x_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) dev_name(dev), ac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) dev_err(dev, "irq %d busy?\n", ac->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) goto err_free_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) err = sysfs_create_group(&dev->kobj, &adxl34x_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) goto err_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) err = input_register_device(input_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) goto err_remove_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) AC_WRITE(ac, OFSX, pdata->x_axis_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ac->hwcal.x = pdata->x_axis_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) AC_WRITE(ac, OFSY, pdata->y_axis_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ac->hwcal.y = pdata->y_axis_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) AC_WRITE(ac, OFSZ, pdata->z_axis_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) ac->hwcal.z = pdata->z_axis_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) AC_WRITE(ac, THRESH_TAP, pdata->tap_threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) AC_WRITE(ac, DUR, pdata->tap_duration);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) AC_WRITE(ac, LATENT, pdata->tap_latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) AC_WRITE(ac, WINDOW, pdata->tap_window);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) AC_WRITE(ac, THRESH_ACT, pdata->activity_threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) AC_WRITE(ac, THRESH_INACT, pdata->inactivity_threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) AC_WRITE(ac, TIME_INACT, pdata->inactivity_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) AC_WRITE(ac, THRESH_FF, pdata->free_fall_threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) AC_WRITE(ac, TIME_FF, pdata->free_fall_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) AC_WRITE(ac, TAP_AXES, pdata->tap_axis_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) AC_WRITE(ac, ACT_INACT_CTL, pdata->act_axis_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) AC_WRITE(ac, BW_RATE, RATE(ac->pdata.data_rate) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) (pdata->low_power_mode ? LOW_POWER : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) AC_WRITE(ac, DATA_FORMAT, pdata->data_range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) AC_WRITE(ac, FIFO_CTL, FIFO_MODE(pdata->fifo_mode) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) SAMPLES(pdata->watermark));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (pdata->use_int2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* Map all INTs to INT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) AC_WRITE(ac, INT_MAP, ac->int_mask | OVERRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* Map all INTs to INT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) AC_WRITE(ac, INT_MAP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (ac->model == 346 && ac->pdata.orientation_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) AC_WRITE(ac, ORIENT_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) ORIENT_DEADZONE(ac->pdata.deadzone_angle) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ORIENT_DIVISOR(ac->pdata.divisor_length));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) ac->orient2d_saved = 1234;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) ac->orient3d_saved = 1234;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (pdata->orientation_enable & ADXL_EN_ORIENTATION_3D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) for (i = 0; i < ARRAY_SIZE(pdata->ev_codes_orient_3d); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) __set_bit(pdata->ev_codes_orient_3d[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) input_dev->keybit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (pdata->orientation_enable & ADXL_EN_ORIENTATION_2D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) for (i = 0; i < ARRAY_SIZE(pdata->ev_codes_orient_2d); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) __set_bit(pdata->ev_codes_orient_2d[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) input_dev->keybit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) ac->pdata.orientation_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) AC_WRITE(ac, INT_ENABLE, ac->int_mask | OVERRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ac->pdata.power_mode &= (PCTL_AUTO_SLEEP | PCTL_LINK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return ac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) err_remove_attr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) sysfs_remove_group(&dev->kobj, &adxl34x_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) err_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) free_irq(ac->irq, ac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) err_free_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) input_free_device(input_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) kfree(ac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) EXPORT_SYMBOL_GPL(adxl34x_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) int adxl34x_remove(struct adxl34x *ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) sysfs_remove_group(&ac->dev->kobj, &adxl34x_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) free_irq(ac->irq, ac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) input_unregister_device(ac->input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) dev_dbg(ac->dev, "unregistered accelerometer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) kfree(ac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) EXPORT_SYMBOL_GPL(adxl34x_remove);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) MODULE_DESCRIPTION("ADXL345/346 Three-Axis Digital Accelerometer Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags