^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Keyboard class input driver for the NVIDIA Tegra SoC internal matrix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * keyboard controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2009-2011, NVIDIA Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/input/matrix_keypad.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define KBC_MAX_KPENT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Maximum row/column supported by Tegra KBC yet is 16x8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define KBC_MAX_GPIO 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Maximum keys supported by Tegra KBC yet is 16 x 8*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define KBC_MAX_KEY (16 * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define KBC_MAX_DEBOUNCE_CNT 0x3ffu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* KBC row scan time and delay for beginning the row scan. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define KBC_ROW_SCAN_TIME 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define KBC_ROW_SCAN_DLY 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* KBC uses a 32KHz clock so a cycle = 1/32Khz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define KBC_CYCLE_MS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* KBC Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* KBC Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define KBC_CONTROL_0 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define KBC_FIFO_TH_CNT_SHIFT(cnt) (cnt << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define KBC_DEBOUNCE_CNT_SHIFT(cnt) (cnt << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define KBC_CONTROL_FIFO_CNT_INT_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define KBC_CONTROL_KEYPRESS_INT_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define KBC_CONTROL_KBC_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* KBC Interrupt Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define KBC_INT_0 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define KBC_INT_FIFO_CNT_INT_STATUS (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define KBC_INT_KEYPRESS_INT_STATUS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define KBC_ROW_CFG0_0 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define KBC_COL_CFG0_0 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define KBC_TO_CNT_0 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define KBC_INIT_DLY_0 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define KBC_RPT_DLY_0 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define KBC_KP_ENT0_0 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define KBC_KP_ENT1_0 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define KBC_ROW0_MASK_0 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define KBC_ROW_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) enum tegra_pin_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PIN_CFG_IGNORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PIN_CFG_COL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PIN_CFG_ROW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Tegra KBC hw support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct tegra_kbc_hw_support {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int max_rows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int max_columns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct tegra_kbc_pin_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) enum tegra_pin_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned char num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct tegra_kbc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned int debounce_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned int repeat_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct tegra_kbc_pin_cfg pin_cfg[KBC_MAX_GPIO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) const struct matrix_keymap_data *keymap_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) bool wakeup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct input_dev *idev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int repoll_dly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned long cp_dly_jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int cp_to_wkup_dly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) bool use_fn_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) bool use_ghost_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) bool keypress_caused_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned short keycode[KBC_MAX_KEY * 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned short current_keys[KBC_MAX_KPENT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int num_pressed_keys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 wakeup_key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) const struct tegra_kbc_hw_support *hw_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int max_keys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int num_rows_and_columns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void tegra_kbc_report_released_keys(struct input_dev *input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned short old_keycodes[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned int old_num_keys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned short new_keycodes[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned int new_num_keys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) for (i = 0; i < old_num_keys; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) for (j = 0; j < new_num_keys; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (old_keycodes[i] == new_keycodes[j])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (j == new_num_keys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) input_report_key(input, old_keycodes[i], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static void tegra_kbc_report_pressed_keys(struct input_dev *input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned char scancodes[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned short keycodes[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned int num_pressed_keys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) for (i = 0; i < num_pressed_keys; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) input_event(input, EV_MSC, MSC_SCAN, scancodes[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) input_report_key(input, keycodes[i], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static void tegra_kbc_report_keys(struct tegra_kbc *kbc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned char scancodes[KBC_MAX_KPENT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned short keycodes[KBC_MAX_KPENT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned int num_down = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) bool fn_keypress = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) bool key_in_same_row = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) bool key_in_same_col = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) for (i = 0; i < KBC_MAX_KPENT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if ((i % 4) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) val = readl(kbc->mmio + KBC_KP_ENT0_0 + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (val & 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned int col = val & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned int row = (val >> 3) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned char scancode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MATRIX_SCAN_CODE(row, col, KBC_ROW_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) scancodes[num_down] = scancode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) keycodes[num_down] = kbc->keycode[scancode];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* If driver uses Fn map, do not report the Fn key. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if ((keycodes[num_down] == KEY_FN) && kbc->use_fn_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) fn_keypress = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) num_down++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) val >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * Matrix keyboard designs are prone to keyboard ghosting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * Ghosting occurs if there are 3 keys such that -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * any 2 of the 3 keys share a row, and any 2 of them share a column.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * If so ignore the key presses for this iteration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (kbc->use_ghost_filter && num_down >= 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) for (i = 0; i < num_down; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u8 curr_col = scancodes[i] & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u8 curr_row = scancodes[i] >> KBC_ROW_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * Find 2 keys such that one key is in the same row
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * and the other is in the same column as the i-th key.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) for (j = i + 1; j < num_down; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u8 col = scancodes[j] & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u8 row = scancodes[j] >> KBC_ROW_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (col == curr_col)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) key_in_same_col = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (row == curr_row)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) key_in_same_row = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * If the platform uses Fn keymaps, translate keys on a Fn keypress.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * Function keycodes are max_keys apart from the plain keycodes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (fn_keypress) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) for (i = 0; i < num_down; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) scancodes[i] += kbc->max_keys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) keycodes[i] = kbc->keycode[scancodes[i]];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Ignore the key presses for this iteration? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (key_in_same_col && key_in_same_row)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) tegra_kbc_report_released_keys(kbc->idev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) kbc->current_keys, kbc->num_pressed_keys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) keycodes, num_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) tegra_kbc_report_pressed_keys(kbc->idev, scancodes, keycodes, num_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) input_sync(kbc->idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) memcpy(kbc->current_keys, keycodes, sizeof(kbc->current_keys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) kbc->num_pressed_keys = num_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static void tegra_kbc_set_fifo_interrupt(struct tegra_kbc *kbc, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) val = readl(kbc->mmio + KBC_CONTROL_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) val |= KBC_CONTROL_FIFO_CNT_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) val &= ~KBC_CONTROL_FIFO_CNT_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) writel(val, kbc->mmio + KBC_CONTROL_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static void tegra_kbc_keypress_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct tegra_kbc *kbc = from_timer(kbc, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) spin_lock_irqsave(&kbc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) val = (readl(kbc->mmio + KBC_INT_0) >> 4) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned long dly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) tegra_kbc_report_keys(kbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * If more than one keys are pressed we need not wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * for the repoll delay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) dly = (val == 1) ? kbc->repoll_dly : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) mod_timer(&kbc->timer, jiffies + msecs_to_jiffies(dly));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Release any pressed keys and exit the polling loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) for (i = 0; i < kbc->num_pressed_keys; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) input_report_key(kbc->idev, kbc->current_keys[i], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) input_sync(kbc->idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) kbc->num_pressed_keys = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* All keys are released so enable the keypress interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) tegra_kbc_set_fifo_interrupt(kbc, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) spin_unlock_irqrestore(&kbc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static irqreturn_t tegra_kbc_isr(int irq, void *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct tegra_kbc *kbc = args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) spin_lock_irqsave(&kbc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * Quickly bail out & reenable interrupts if the fifo threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * count interrupt wasn't the interrupt source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) val = readl(kbc->mmio + KBC_INT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) writel(val, kbc->mmio + KBC_INT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (val & KBC_INT_FIFO_CNT_INT_STATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * Until all keys are released, defer further processing to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * the polling loop in tegra_kbc_keypress_timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) tegra_kbc_set_fifo_interrupt(kbc, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) mod_timer(&kbc->timer, jiffies + kbc->cp_dly_jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) } else if (val & KBC_INT_KEYPRESS_INT_STATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* We can be here only through system resume path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) kbc->keypress_caused_wake = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) spin_unlock_irqrestore(&kbc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static void tegra_kbc_setup_wakekeys(struct tegra_kbc *kbc, bool filter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned int rst_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Either mask all keys or none. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) rst_val = (filter && !kbc->wakeup) ? ~0 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) for (i = 0; i < kbc->hw_support->max_rows; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) writel(rst_val, kbc->mmio + KBC_ROW0_MASK_0 + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static void tegra_kbc_config_pins(struct tegra_kbc *kbc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) for (i = 0; i < KBC_MAX_GPIO; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u32 r_shft = 5 * (i % 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 c_shft = 4 * (i % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 r_mask = 0x1f << r_shft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 c_mask = 0x0f << c_shft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u32 r_offs = (i / 6) * 4 + KBC_ROW_CFG0_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u32 c_offs = (i / 8) * 4 + KBC_COL_CFG0_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 row_cfg = readl(kbc->mmio + r_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u32 col_cfg = readl(kbc->mmio + c_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) row_cfg &= ~r_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) col_cfg &= ~c_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) switch (kbc->pin_cfg[i].type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) case PIN_CFG_ROW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) row_cfg |= ((kbc->pin_cfg[i].num << 1) | 1) << r_shft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) case PIN_CFG_COL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) col_cfg |= ((kbc->pin_cfg[i].num << 1) | 1) << c_shft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) case PIN_CFG_IGNORE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) writel(row_cfg, kbc->mmio + r_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) writel(col_cfg, kbc->mmio + c_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int tegra_kbc_start(struct tegra_kbc *kbc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned int debounce_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ret = clk_prepare_enable(kbc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* Reset the KBC controller to clear all previous status.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) reset_control_assert(kbc->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) reset_control_deassert(kbc->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) tegra_kbc_config_pins(kbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) tegra_kbc_setup_wakekeys(kbc, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) writel(kbc->repeat_cnt, kbc->mmio + KBC_RPT_DLY_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Keyboard debounce count is maximum of 12 bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) debounce_cnt = min(kbc->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) val = KBC_DEBOUNCE_CNT_SHIFT(debounce_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) val |= KBC_FIFO_TH_CNT_SHIFT(1); /* set fifo interrupt threshold to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) val |= KBC_CONTROL_FIFO_CNT_INT_EN; /* interrupt on FIFO threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) val |= KBC_CONTROL_KBC_EN; /* enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) writel(val, kbc->mmio + KBC_CONTROL_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * Compute the delay(ns) from interrupt mode to continuous polling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * mode so the timer routine is scheduled appropriately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) val = readl(kbc->mmio + KBC_INIT_DLY_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) kbc->cp_dly_jiffies = usecs_to_jiffies((val & 0xfffff) * 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) kbc->num_pressed_keys = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * Atomically clear out any remaining entries in the key FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * and enable keyboard interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) val = readl(kbc->mmio + KBC_INT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) val >>= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) val = readl(kbc->mmio + KBC_KP_ENT0_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) val = readl(kbc->mmio + KBC_KP_ENT1_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) writel(0x7, kbc->mmio + KBC_INT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) enable_irq(kbc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static void tegra_kbc_stop(struct tegra_kbc *kbc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) spin_lock_irqsave(&kbc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) val = readl(kbc->mmio + KBC_CONTROL_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) val &= ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) writel(val, kbc->mmio + KBC_CONTROL_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) spin_unlock_irqrestore(&kbc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) disable_irq(kbc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) del_timer_sync(&kbc->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) clk_disable_unprepare(kbc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int tegra_kbc_open(struct input_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct tegra_kbc *kbc = input_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return tegra_kbc_start(kbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static void tegra_kbc_close(struct input_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct tegra_kbc *kbc = input_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return tegra_kbc_stop(kbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static bool tegra_kbc_check_pin_cfg(const struct tegra_kbc *kbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned int *num_rows)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) *num_rows = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) for (i = 0; i < KBC_MAX_GPIO; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) const struct tegra_kbc_pin_cfg *pin_cfg = &kbc->pin_cfg[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) switch (pin_cfg->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) case PIN_CFG_ROW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (pin_cfg->num >= kbc->hw_support->max_rows) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dev_err(kbc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) "pin_cfg[%d]: invalid row number %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) i, pin_cfg->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) (*num_rows)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) case PIN_CFG_COL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (pin_cfg->num >= kbc->hw_support->max_columns) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) dev_err(kbc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) "pin_cfg[%d]: invalid column number %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) i, pin_cfg->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) case PIN_CFG_IGNORE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) dev_err(kbc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) "pin_cfg[%d]: invalid entry type %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) pin_cfg->type, pin_cfg->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static int tegra_kbc_parse_dt(struct tegra_kbc *kbc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct device_node *np = kbc->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u32 prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u32 num_rows = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u32 num_cols = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u32 cols_cfg[KBC_MAX_GPIO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u32 rows_cfg[KBC_MAX_GPIO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) int proplen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (!of_property_read_u32(np, "nvidia,debounce-delay-ms", &prop))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) kbc->debounce_cnt = prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (!of_property_read_u32(np, "nvidia,repeat-delay-ms", &prop))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) kbc->repeat_cnt = prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (of_find_property(np, "nvidia,needs-ghost-filter", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) kbc->use_ghost_filter = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (of_property_read_bool(np, "wakeup-source") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) of_property_read_bool(np, "nvidia,wakeup-source")) /* legacy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) kbc->wakeup = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (!of_get_property(np, "nvidia,kbc-row-pins", &proplen)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dev_err(kbc->dev, "property nvidia,kbc-row-pins not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) num_rows = proplen / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (!of_get_property(np, "nvidia,kbc-col-pins", &proplen)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) dev_err(kbc->dev, "property nvidia,kbc-col-pins not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) num_cols = proplen / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (num_rows > kbc->hw_support->max_rows) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) dev_err(kbc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) "Number of rows is more than supported by hardware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (num_cols > kbc->hw_support->max_columns) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) dev_err(kbc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) "Number of cols is more than supported by hardware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (!of_get_property(np, "linux,keymap", &proplen)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) dev_err(kbc->dev, "property linux,keymap not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (!num_rows || !num_cols || ((num_rows + num_cols) > KBC_MAX_GPIO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) dev_err(kbc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) "keypad rows/columns not properly specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* Set all pins as non-configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) for (i = 0; i < kbc->num_rows_and_columns; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) kbc->pin_cfg[i].type = PIN_CFG_IGNORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ret = of_property_read_u32_array(np, "nvidia,kbc-row-pins",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) rows_cfg, num_rows);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) dev_err(kbc->dev, "Rows configurations are not proper\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ret = of_property_read_u32_array(np, "nvidia,kbc-col-pins",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) cols_cfg, num_cols);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) dev_err(kbc->dev, "Cols configurations are not proper\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) for (i = 0; i < num_rows; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) kbc->pin_cfg[rows_cfg[i]].type = PIN_CFG_ROW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) kbc->pin_cfg[rows_cfg[i]].num = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) for (i = 0; i < num_cols; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) kbc->pin_cfg[cols_cfg[i]].type = PIN_CFG_COL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) kbc->pin_cfg[cols_cfg[i]].num = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static const struct tegra_kbc_hw_support tegra20_kbc_hw_support = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .max_rows = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .max_columns = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static const struct tegra_kbc_hw_support tegra11_kbc_hw_support = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .max_rows = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .max_columns = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static const struct of_device_id tegra_kbc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) { .compatible = "nvidia,tegra114-kbc", .data = &tegra11_kbc_hw_support},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) { .compatible = "nvidia,tegra30-kbc", .data = &tegra20_kbc_hw_support},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) { .compatible = "nvidia,tegra20-kbc", .data = &tegra20_kbc_hw_support},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) MODULE_DEVICE_TABLE(of, tegra_kbc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static int tegra_kbc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct tegra_kbc *kbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) int num_rows = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) unsigned int debounce_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) unsigned int scan_time_rows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) unsigned int keymap_rows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) match = of_match_device(tegra_kbc_of_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) kbc = devm_kzalloc(&pdev->dev, sizeof(*kbc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (!kbc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) dev_err(&pdev->dev, "failed to alloc memory for kbc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) kbc->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) kbc->hw_support = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) kbc->max_keys = kbc->hw_support->max_rows *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) kbc->hw_support->max_columns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) kbc->num_rows_and_columns = kbc->hw_support->max_rows +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) kbc->hw_support->max_columns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) keymap_rows = kbc->max_keys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) spin_lock_init(&kbc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) err = tegra_kbc_parse_dt(kbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (!tegra_kbc_check_pin_cfg(kbc, &num_rows))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) kbc->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (kbc->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) kbc->idev = devm_input_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (!kbc->idev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) dev_err(&pdev->dev, "failed to allocate input device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) timer_setup(&kbc->timer, tegra_kbc_keypress_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) kbc->mmio = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (IS_ERR(kbc->mmio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return PTR_ERR(kbc->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) kbc->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (IS_ERR(kbc->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) dev_err(&pdev->dev, "failed to get keyboard clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return PTR_ERR(kbc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) kbc->rst = devm_reset_control_get(&pdev->dev, "kbc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (IS_ERR(kbc->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) dev_err(&pdev->dev, "failed to get keyboard reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return PTR_ERR(kbc->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * The time delay between two consecutive reads of the FIFO is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * the sum of the repeat time and the time taken for scanning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * the rows. There is an additional delay before the row scanning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * starts. The repoll delay is computed in milliseconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) debounce_cnt = min(kbc->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) scan_time_rows = (KBC_ROW_SCAN_TIME + debounce_cnt) * num_rows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) kbc->repoll_dly = KBC_ROW_SCAN_DLY + scan_time_rows + kbc->repeat_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) kbc->repoll_dly = DIV_ROUND_UP(kbc->repoll_dly, KBC_CYCLE_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) kbc->idev->name = pdev->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) kbc->idev->id.bustype = BUS_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) kbc->idev->dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) kbc->idev->open = tegra_kbc_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) kbc->idev->close = tegra_kbc_close;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (kbc->keymap_data && kbc->use_fn_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) keymap_rows *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) err = matrix_keypad_build_keymap(kbc->keymap_data, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) keymap_rows,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) kbc->hw_support->max_columns,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) kbc->keycode, kbc->idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) dev_err(&pdev->dev, "failed to setup keymap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) __set_bit(EV_REP, kbc->idev->evbit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) input_set_capability(kbc->idev, EV_MSC, MSC_SCAN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) input_set_drvdata(kbc->idev, kbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) err = devm_request_irq(&pdev->dev, kbc->irq, tegra_kbc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) IRQF_TRIGGER_HIGH, pdev->name, kbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) dev_err(&pdev->dev, "failed to request keyboard IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) disable_irq(kbc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) err = input_register_device(kbc->idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) dev_err(&pdev->dev, "failed to register input device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) platform_set_drvdata(pdev, kbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) device_init_wakeup(&pdev->dev, kbc->wakeup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static void tegra_kbc_set_keypress_interrupt(struct tegra_kbc *kbc, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) val = readl(kbc->mmio + KBC_CONTROL_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) val |= KBC_CONTROL_KEYPRESS_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) val &= ~KBC_CONTROL_KEYPRESS_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) writel(val, kbc->mmio + KBC_CONTROL_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static int tegra_kbc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct tegra_kbc *kbc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) mutex_lock(&kbc->idev->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (device_may_wakeup(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) disable_irq(kbc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) del_timer_sync(&kbc->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) tegra_kbc_set_fifo_interrupt(kbc, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) /* Forcefully clear the interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) writel(0x7, kbc->mmio + KBC_INT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * Store the previous resident time of continuous polling mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * Force the keyboard into interrupt mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) kbc->cp_to_wkup_dly = readl(kbc->mmio + KBC_TO_CNT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) writel(0, kbc->mmio + KBC_TO_CNT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) tegra_kbc_setup_wakekeys(kbc, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) msleep(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) kbc->keypress_caused_wake = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* Enable keypress interrupt before going into suspend. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) tegra_kbc_set_keypress_interrupt(kbc, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) enable_irq(kbc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) enable_irq_wake(kbc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (kbc->idev->users)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) tegra_kbc_stop(kbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) mutex_unlock(&kbc->idev->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static int tegra_kbc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct tegra_kbc *kbc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) mutex_lock(&kbc->idev->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (device_may_wakeup(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) disable_irq_wake(kbc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) tegra_kbc_setup_wakekeys(kbc, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* We will use fifo interrupts for key detection. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) tegra_kbc_set_keypress_interrupt(kbc, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* Restore the resident time of continuous polling mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) writel(kbc->cp_to_wkup_dly, kbc->mmio + KBC_TO_CNT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) tegra_kbc_set_fifo_interrupt(kbc, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (kbc->keypress_caused_wake && kbc->wakeup_key) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * We can't report events directly from the ISR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * because timekeeping is stopped when processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * wakeup request and we get a nasty warning when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * we try to call do_gettimeofday() in evdev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) input_report_key(kbc->idev, kbc->wakeup_key, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) input_sync(kbc->idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) input_report_key(kbc->idev, kbc->wakeup_key, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) input_sync(kbc->idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (kbc->idev->users)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) err = tegra_kbc_start(kbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) mutex_unlock(&kbc->idev->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static SIMPLE_DEV_PM_OPS(tegra_kbc_pm_ops, tegra_kbc_suspend, tegra_kbc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static struct platform_driver tegra_kbc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .probe = tegra_kbc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .name = "tegra-kbc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .pm = &tegra_kbc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .of_match_table = tegra_kbc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) module_platform_driver(tegra_kbc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) MODULE_AUTHOR("Rakesh Iyer <riyer@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) MODULE_DESCRIPTION("Tegra matrix keyboard controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) MODULE_ALIAS("platform:tegra-kbc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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