^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* QLogic qedr NIC Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (c) 2015-2016 QLogic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This software is available to you under a choice of one of two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * licenses. You may choose to be licensed under the terms of the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * General Public License (GPL) Version 2, available from the file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * COPYING in the main directory of this source tree, or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * OpenIB.org BSD license below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Redistribution and use in source and binary forms, with or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * without modification, are permitted provided that the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * conditions are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * - Redistributions of source code must retain the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * copyright notice, this list of conditions and the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * - Redistributions in binary form must reproduce the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * copyright notice, this list of conditions and the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * disclaimer in the documentation and /or other materials
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * provided with the distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #ifndef __QEDR_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define __QEDR_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/xarray.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <rdma/ib_addr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/qed/qed_if.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/qed/qed_chain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/qed/qed_rdma_if.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/qed/qede_rdma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/qed/roce_common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include "qedr_hsi_rdma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define QEDR_NODE_DESC "QLogic 579xx RoCE HCA"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DP_NAME(_dev) dev_name(&(_dev)->ibdev.dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IS_IWARP(_dev) ((_dev)->rdma_type == QED_RDMA_TYPE_IWARP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IS_ROCE(_dev) ((_dev)->rdma_type == QED_RDMA_TYPE_ROCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DP_DEBUG(dev, module, fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) pr_debug("(%s) " module ": " fmt, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) DP_NAME(dev) ? DP_NAME(dev) : "", ## __VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define QEDR_MSG_INIT "INIT"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define QEDR_MSG_MISC "MISC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define QEDR_MSG_CQ " CQ"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define QEDR_MSG_MR " MR"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define QEDR_MSG_RQ " RQ"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define QEDR_MSG_SQ " SQ"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define QEDR_MSG_QP " QP"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define QEDR_MSG_SRQ " SRQ"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define QEDR_MSG_GSI " GSI"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define QEDR_MSG_IWARP " IW"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define QEDR_CQ_MAGIC_NUMBER (0x11223344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define FW_PAGE_SIZE (RDMA_RING_PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define FW_PAGE_SHIFT (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct qedr_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct qedr_cnq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct qedr_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct qed_chain pbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct qed_sb_info *sb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) char name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u64 n_comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) __le16 *hw_cons_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u8 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define QEDR_MAX_SGID 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct qedr_device_attr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 vendor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 vendor_part_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 hw_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u64 fw_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u64 node_guid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u64 sys_image_guid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 max_cnq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u8 max_sge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u16 max_inline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 max_sqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 max_rqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u8 max_qp_resp_rd_atomic_resc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 max_qp_req_rd_atomic_resc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u64 max_dev_resp_rd_atomic_resc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 max_cq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 max_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 max_mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u64 max_mr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 max_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 max_mw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 max_mr_mw_fmr_pbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u64 max_mr_mw_fmr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 max_pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 max_ah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u8 max_pkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 max_srq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 max_srq_wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u8 max_srq_sge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u8 max_stats_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 dev_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u64 page_size_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u8 dev_ack_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 reserved_lkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 bad_pkey_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct qed_rdma_events events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define QEDR_ENET_STATE_BIT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct qedr_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct ib_device ibdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct qed_dev *cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct net_device *ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) enum ib_atomic_cap atomic_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) void *rdma_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct qedr_device_attr attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) const struct qed_rdma_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct qed_int_info int_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct qed_sb_info *sb_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct qedr_cnq *cnq_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int num_cnq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int sb_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) void __iomem *db_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u64 db_phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 db_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u16 dpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) union ib_gid *sgid_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Lock for sgid table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) spinlock_t sgid_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u64 guid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 dp_module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u8 dp_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u8 num_hwfns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define QEDR_IS_CMT(dev) ((dev)->num_hwfns > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u8 affin_hwfn_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u8 gsi_ll2_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) uint wq_multiplier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u8 gsi_ll2_mac_address[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int gsi_qp_created;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct qedr_cq *gsi_sqcq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct qedr_cq *gsi_rqcq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct qedr_qp *gsi_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) enum qed_rdma_type rdma_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct xarray qps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct xarray srqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct workqueue_struct *iwarp_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u16 iwarp_max_mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned long enet_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u8 user_dpm_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define QEDR_MAX_SQ_PBL (0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define QEDR_MAX_SQ_PBL_ENTRIES (0x10000 / sizeof(void *))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define QEDR_SQE_ELEMENT_SIZE (sizeof(struct rdma_sq_sge))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define QEDR_MAX_SQE_ELEMENTS_PER_SQE (ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE / \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) QEDR_SQE_ELEMENT_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define QEDR_MAX_SQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) QEDR_SQE_ELEMENT_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define QEDR_MAX_SQE ((QEDR_MAX_SQ_PBL_ENTRIES) *\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) (RDMA_RING_PAGE_SIZE) / \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) (QEDR_SQE_ELEMENT_SIZE) /\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) (QEDR_MAX_SQE_ELEMENTS_PER_SQE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* RQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define QEDR_MAX_RQ_PBL (0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define QEDR_MAX_RQ_PBL_ENTRIES (0x10000 / sizeof(void *))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define QEDR_RQE_ELEMENT_SIZE (sizeof(struct rdma_rq_sge))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define QEDR_MAX_RQE_ELEMENTS_PER_RQE (RDMA_MAX_SGE_PER_RQ_WQE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define QEDR_MAX_RQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) QEDR_RQE_ELEMENT_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define QEDR_MAX_RQE ((QEDR_MAX_RQ_PBL_ENTRIES) *\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) (RDMA_RING_PAGE_SIZE) / \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) (QEDR_RQE_ELEMENT_SIZE) /\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) (QEDR_MAX_RQE_ELEMENTS_PER_RQE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define QEDR_CQE_SIZE (sizeof(union rdma_cqe))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define QEDR_MAX_CQE_PBL_SIZE (512 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define QEDR_MAX_CQE_PBL_ENTRIES (((QEDR_MAX_CQE_PBL_SIZE) / \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) sizeof(u64)) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define QEDR_MAX_CQES ((u32)((QEDR_MAX_CQE_PBL_ENTRIES) * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) (QED_CHAIN_PAGE_SIZE) / QEDR_CQE_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define QEDR_ROCE_MAX_CNQ_SIZE (0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define QEDR_MAX_PORT (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define QEDR_PORT (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define QEDR_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define QEDR_ROCE_PKEY_MAX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define QEDR_ROCE_PKEY_TABLE_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define QEDR_ROCE_PKEY_DEFAULT 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct qedr_pbl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct list_head list_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) void *va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dma_addr_t pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct qedr_ucontext {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct ib_ucontext ibucontext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct qedr_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct qedr_pd *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) void __iomem *dpi_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct rdma_user_mmap_entry *db_mmap_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u64 dpi_phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 dpi_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u16 dpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) bool db_rec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u8 edpm_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) union db_prod32 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct rdma_pwm_val16_data data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) union db_prod64 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct rdma_pwm_val32_data data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u64 raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) enum qedr_cq_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) QEDR_CQ_TYPE_GSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) QEDR_CQ_TYPE_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) QEDR_CQ_TYPE_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct qedr_pbl_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u32 num_pbls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u32 num_pbes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u32 pbl_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u32 pbe_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) bool two_layered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct qedr_userq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct ib_umem *umem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct qedr_pbl_info pbl_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct qedr_pbl *pbl_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u64 buf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) size_t buf_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* doorbell recovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) void __iomem *db_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct qedr_user_db_rec *db_rec_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct rdma_user_mmap_entry *db_mmap_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) void __iomem *db_rec_db2_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) union db_prod32 db_rec_db2_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct qedr_cq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct ib_cq ibcq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) enum qedr_cq_type cq_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u32 sig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u16 icid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Lock to protect multiplem CQ's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) spinlock_t cq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u8 arm_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct qed_chain pbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) void __iomem *db_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) union db_prod64 db;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u8 pbl_toggle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) union rdma_cqe *latest_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) union rdma_cqe *toggle_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u32 cq_cons;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct qedr_userq q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u8 destroyed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u16 cnq_notif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct qedr_pd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct ib_pd ibpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 pd_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct qedr_ucontext *uctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct qedr_xrcd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct ib_xrcd ibxrcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u16 xrcd_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct qedr_qp_hwq_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* WQE Elements */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct qed_chain pbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u64 p_phys_addr_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u32 max_sges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* WQE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u16 prod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u16 cons;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u16 wqe_cons;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u16 gsi_cons;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u16 max_wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* DB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) void __iomem *db;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) union db_prod32 db_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) void __iomem *iwarp_db2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) union db_prod32 iwarp_db2_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define QEDR_INC_SW_IDX(p_info, index) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) p_info->index = (p_info->index + 1) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) qed_chain_get_capacity(p_info->pbl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct qedr_srq_hwq_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 max_sges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u32 max_wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct qed_chain pbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u64 p_phys_addr_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u32 wqe_prod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u32 sge_prod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 wr_prod_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) atomic_t wr_cons_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u32 num_elems;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct rdma_srq_producers *virt_prod_pair_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dma_addr_t phy_prod_pair_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct qedr_srq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct ib_srq ibsrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct qedr_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct qedr_userq usrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct qedr_srq_hwq_info hw_srq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct ib_umem *prod_umem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u16 srq_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u32 srq_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) bool is_xrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* lock to protect srq recv post */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) enum qedr_qp_err_bitmap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) QEDR_QP_ERR_SQ_FULL = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) QEDR_QP_ERR_RQ_FULL = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) QEDR_QP_ERR_BAD_SR = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) QEDR_QP_ERR_BAD_RR = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) QEDR_QP_ERR_SQ_PBL_FULL = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) QEDR_QP_ERR_RQ_PBL_FULL = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) enum qedr_qp_create_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) QEDR_QP_CREATE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) QEDR_QP_CREATE_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) QEDR_QP_CREATE_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) enum qedr_iwarp_cm_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) QEDR_IWARP_CM_WAIT_FOR_CONNECT = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) QEDR_IWARP_CM_WAIT_FOR_DISCONNECT = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct qedr_qp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct ib_qp ibqp; /* must be first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct qedr_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct qedr_qp_hwq_info sq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct qedr_qp_hwq_info rq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u32 max_inline_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Lock for QP's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) spinlock_t q_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct qedr_cq *sq_cq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct qedr_cq *rq_cq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct qedr_srq *srq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) enum qed_roce_qp_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct qedr_pd *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) enum ib_qp_type qp_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) enum qedr_qp_create_type create_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct qed_rdma_qp *qed_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u32 qp_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u16 icid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u16 mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int sgid_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u32 rq_psn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u32 sq_psn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u32 qkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u32 dest_qp_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Relevant to qps created from kernel space only (ULPs) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u8 prev_wqe_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u16 wqe_cons;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u32 err_bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) bool signaled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* SQ shadow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u64 wr_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) enum ib_wc_opcode opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u32 bytes_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u8 wqe_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) bool signaled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dma_addr_t icrc_mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u32 *icrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct qedr_mr *mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) } *wqe_wr_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* RQ shadow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u64 wr_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct ib_sge sg_list[RDMA_MAX_SGE_PER_RQ_WQE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u8 wqe_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u8 smac[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u16 vlan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) } *rqe_wr_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* Relevant to qps created from user space only (applications) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct qedr_userq usq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct qedr_userq urq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* synchronization objects used with iwarp ep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct kref refcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct completion iwarp_cm_comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) unsigned long iwarp_cm_flags; /* enum iwarp_cm_flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct qedr_ah {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct ib_ah ibah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct rdma_ah_attr attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) enum qedr_mr_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) QEDR_MR_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) QEDR_MR_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) QEDR_MR_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) QEDR_MR_FRMR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct mr_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct qedr_pbl *pbl_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct qedr_pbl_info pbl_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct list_head free_pbl_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct list_head inuse_pbl_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u32 completed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u32 completed_handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct qedr_mr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct ib_mr ibmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct ib_umem *umem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct qed_rdma_register_tid_in_params hw_mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) enum qedr_mr_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct qedr_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct mr_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u64 *pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) u32 npages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct qedr_user_mmap_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct rdma_user_mmap_entry rdma_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct qedr_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) u64 io_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) void *address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) size_t length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u16 dpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u8 mmap_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define SET_FIELD2(value, name, flag) ((value) |= ((flag) << (name ## _SHIFT)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define QEDR_RESP_IMM (RDMA_CQE_RESPONDER_IMM_FLG_MASK << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) RDMA_CQE_RESPONDER_IMM_FLG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define QEDR_RESP_RDMA (RDMA_CQE_RESPONDER_RDMA_FLG_MASK << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) RDMA_CQE_RESPONDER_RDMA_FLG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define QEDR_RESP_INV (RDMA_CQE_RESPONDER_INV_FLG_MASK << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) RDMA_CQE_RESPONDER_INV_FLG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static inline void qedr_inc_sw_cons(struct qedr_qp_hwq_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) info->cons = (info->cons + 1) % info->max_wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) info->wqe_cons++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static inline void qedr_inc_sw_prod(struct qedr_qp_hwq_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) info->prod = (info->prod + 1) % info->max_wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static inline int qedr_get_dmac(struct qedr_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct rdma_ah_attr *ah_attr, u8 *mac_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) union ib_gid zero_sgid = { { 0 } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct in6_addr in6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u8 *dmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (!memcmp(&grh->dgid, &zero_sgid, sizeof(union ib_gid))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) DP_ERR(dev, "Local port GID not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) eth_zero_addr(mac_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) memcpy(&in6, grh->dgid.raw, sizeof(in6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) dmac = rdma_ah_retrieve_dmac(ah_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (!dmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ether_addr_copy(mac_addr, dmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct qedr_iw_listener {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct qedr_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct iw_cm_id *cm_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) int backlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) void *qed_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct qedr_iw_ep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct qedr_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct iw_cm_id *cm_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct qedr_qp *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) void *qed_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct kref refcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct qedr_ucontext *get_qedr_ucontext(struct ib_ucontext *ibucontext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return container_of(ibucontext, struct qedr_ucontext, ibucontext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static inline struct qedr_dev *get_qedr_dev(struct ib_device *ibdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return container_of(ibdev, struct qedr_dev, ibdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static inline struct qedr_pd *get_qedr_pd(struct ib_pd *ibpd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return container_of(ibpd, struct qedr_pd, ibpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static inline struct qedr_xrcd *get_qedr_xrcd(struct ib_xrcd *ibxrcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return container_of(ibxrcd, struct qedr_xrcd, ibxrcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static inline struct qedr_cq *get_qedr_cq(struct ib_cq *ibcq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return container_of(ibcq, struct qedr_cq, ibcq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static inline struct qedr_qp *get_qedr_qp(struct ib_qp *ibqp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return container_of(ibqp, struct qedr_qp, ibqp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static inline struct qedr_ah *get_qedr_ah(struct ib_ah *ibah)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return container_of(ibah, struct qedr_ah, ibah);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static inline struct qedr_mr *get_qedr_mr(struct ib_mr *ibmr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return container_of(ibmr, struct qedr_mr, ibmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static inline struct qedr_srq *get_qedr_srq(struct ib_srq *ibsrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return container_of(ibsrq, struct qedr_srq, ibsrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static inline bool qedr_qp_has_srq(struct qedr_qp *qp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return qp->srq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static inline bool qedr_qp_has_sq(struct qedr_qp *qp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_XRC_TGT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static inline bool qedr_qp_has_rq(struct qedr_qp *qp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_XRC_INI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) qp->qp_type == IB_QPT_XRC_TGT || qedr_qp_has_srq(qp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static inline struct qedr_user_mmap_entry *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) get_qedr_mmap_entry(struct rdma_user_mmap_entry *rdma_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return container_of(rdma_entry, struct qedr_user_mmap_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) rdma_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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