^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* QLogic qedr NIC Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (c) 2015-2016 QLogic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This software is available to you under a choice of one of two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * licenses. You may choose to be licensed under the terms of the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * General Public License (GPL) Version 2, available from the file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * COPYING in the main directory of this source tree, or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * OpenIB.org BSD license below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Redistribution and use in source and binary forms, with or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * without modification, are permitted provided that the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * conditions are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * - Redistributions of source code must retain the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * copyright notice, this list of conditions and the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * - Redistributions in binary form must reproduce the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * copyright notice, this list of conditions and the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * disclaimer in the documentation and /or other materials
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * provided with the distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <rdma/ib_verbs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <rdma/ib_addr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <rdma/ib_user_verbs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <rdma/iw_cm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <rdma/ib_mad.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <net/addrconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/qed/qed_chain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/qed/qed_if.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include "qedr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include "verbs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <rdma/qedr-abi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include "qedr_iw_cm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MODULE_DESCRIPTION("QLogic 40G/100G ROCE Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MODULE_AUTHOR("QLogic Corporation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MODULE_LICENSE("Dual BSD/GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define QEDR_WQ_MULTIPLIER_DFT (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static void qedr_ib_dispatch_event(struct qedr_dev *dev, u8 port_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) enum ib_event_type type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct ib_event ibev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ibev.device = &dev->ibdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ibev.element.port_num = port_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ibev.event = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ib_dispatch_event(&ibev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static enum rdma_link_layer qedr_link_layer(struct ib_device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u8 port_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return IB_LINK_LAYER_ETHERNET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static void qedr_get_dev_fw_str(struct ib_device *ibdev, char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct qedr_dev *qedr = get_qedr_dev(ibdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 fw_ver = (u32)qedr->attr.fw_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) (fw_ver >> 24) & 0xFF, (fw_ver >> 16) & 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) (fw_ver >> 8) & 0xFF, fw_ver & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int qedr_roce_port_immutable(struct ib_device *ibdev, u8 port_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct ib_port_immutable *immutable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct ib_port_attr attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) err = qedr_query_port(ibdev, port_num, &attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) immutable->pkey_tbl_len = attr.pkey_tbl_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) immutable->gid_tbl_len = attr.gid_tbl_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) immutable->max_mad_size = IB_MGMT_MAD_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int qedr_iw_port_immutable(struct ib_device *ibdev, u8 port_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct ib_port_immutable *immutable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct ib_port_attr attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) err = qedr_query_port(ibdev, port_num, &attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) immutable->gid_tbl_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) immutable->core_cap_flags = RDMA_CORE_PORT_IWARP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) immutable->max_mad_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* QEDR sysfs interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static ssize_t hw_rev_show(struct device *device, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct qedr_dev *dev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) rdma_device_to_drv_device(device, struct qedr_dev, ibdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return scnprintf(buf, PAGE_SIZE, "0x%x\n", dev->attr.hw_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static DEVICE_ATTR_RO(hw_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static ssize_t hca_type_show(struct device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct qedr_dev *dev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) rdma_device_to_drv_device(device, struct qedr_dev, ibdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return scnprintf(buf, PAGE_SIZE, "FastLinQ QL%x %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) dev->pdev->device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) rdma_protocol_iwarp(&dev->ibdev, 1) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) "iWARP" : "RoCE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static DEVICE_ATTR_RO(hca_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static struct attribute *qedr_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) &dev_attr_hw_rev.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) &dev_attr_hca_type.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const struct attribute_group qedr_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .attrs = qedr_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const struct ib_device_ops qedr_iw_dev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .get_port_immutable = qedr_iw_port_immutable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .iw_accept = qedr_iw_accept,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .iw_add_ref = qedr_iw_qp_add_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .iw_connect = qedr_iw_connect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .iw_create_listen = qedr_iw_create_listen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .iw_destroy_listen = qedr_iw_destroy_listen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .iw_get_qp = qedr_iw_get_qp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .iw_reject = qedr_iw_reject,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .iw_rem_ref = qedr_iw_qp_rem_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .query_gid = qedr_iw_query_gid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int qedr_iw_register_device(struct qedr_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dev->ibdev.node_type = RDMA_NODE_RNIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ib_set_device_ops(&dev->ibdev, &qedr_iw_dev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) memcpy(dev->ibdev.iw_ifname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dev->ndev->name, sizeof(dev->ibdev.iw_ifname));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const struct ib_device_ops qedr_roce_dev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .alloc_xrcd = qedr_alloc_xrcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .dealloc_xrcd = qedr_dealloc_xrcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .get_port_immutable = qedr_roce_port_immutable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .query_pkey = qedr_query_pkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void qedr_roce_register_device(struct qedr_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dev->ibdev.node_type = RDMA_NODE_IB_CA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ib_set_device_ops(&dev->ibdev, &qedr_roce_dev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dev->ibdev.uverbs_cmd_mask |= QEDR_UVERBS(OPEN_XRCD) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) QEDR_UVERBS(CLOSE_XRCD) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) QEDR_UVERBS(CREATE_XSRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const struct ib_device_ops qedr_dev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .driver_id = RDMA_DRIVER_QEDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .uverbs_abi_ver = QEDR_ABI_VERSION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .alloc_mr = qedr_alloc_mr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .alloc_pd = qedr_alloc_pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .alloc_ucontext = qedr_alloc_ucontext,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .create_ah = qedr_create_ah,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .create_cq = qedr_create_cq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .create_qp = qedr_create_qp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .create_srq = qedr_create_srq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .dealloc_pd = qedr_dealloc_pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .dealloc_ucontext = qedr_dealloc_ucontext,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .dereg_mr = qedr_dereg_mr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .destroy_ah = qedr_destroy_ah,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .destroy_cq = qedr_destroy_cq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .destroy_qp = qedr_destroy_qp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .destroy_srq = qedr_destroy_srq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .get_dev_fw_str = qedr_get_dev_fw_str,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .get_dma_mr = qedr_get_dma_mr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .get_link_layer = qedr_link_layer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .map_mr_sg = qedr_map_mr_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .mmap = qedr_mmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .mmap_free = qedr_mmap_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .modify_qp = qedr_modify_qp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .modify_srq = qedr_modify_srq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .poll_cq = qedr_poll_cq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .post_recv = qedr_post_recv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .post_send = qedr_post_send,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .post_srq_recv = qedr_post_srq_recv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .process_mad = qedr_process_mad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .query_device = qedr_query_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .query_port = qedr_query_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .query_qp = qedr_query_qp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .query_srq = qedr_query_srq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .reg_user_mr = qedr_reg_user_mr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .req_notify_cq = qedr_arm_cq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .resize_cq = qedr_resize_cq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) INIT_RDMA_OBJ_SIZE(ib_ah, qedr_ah, ibah),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) INIT_RDMA_OBJ_SIZE(ib_cq, qedr_cq, ibcq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) INIT_RDMA_OBJ_SIZE(ib_pd, qedr_pd, ibpd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) INIT_RDMA_OBJ_SIZE(ib_srq, qedr_srq, ibsrq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) INIT_RDMA_OBJ_SIZE(ib_xrcd, qedr_xrcd, ibxrcd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) INIT_RDMA_OBJ_SIZE(ib_ucontext, qedr_ucontext, ibucontext),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int qedr_register_device(struct qedr_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) dev->ibdev.node_guid = dev->attr.node_guid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) memcpy(dev->ibdev.node_desc, QEDR_NODE_DESC, sizeof(QEDR_NODE_DESC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) dev->ibdev.uverbs_cmd_mask = QEDR_UVERBS(GET_CONTEXT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) QEDR_UVERBS(QUERY_DEVICE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) QEDR_UVERBS(QUERY_PORT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) QEDR_UVERBS(ALLOC_PD) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) QEDR_UVERBS(DEALLOC_PD) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) QEDR_UVERBS(CREATE_COMP_CHANNEL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) QEDR_UVERBS(CREATE_CQ) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) QEDR_UVERBS(RESIZE_CQ) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) QEDR_UVERBS(DESTROY_CQ) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) QEDR_UVERBS(REQ_NOTIFY_CQ) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) QEDR_UVERBS(CREATE_QP) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) QEDR_UVERBS(MODIFY_QP) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) QEDR_UVERBS(QUERY_QP) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) QEDR_UVERBS(DESTROY_QP) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) QEDR_UVERBS(CREATE_SRQ) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) QEDR_UVERBS(DESTROY_SRQ) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) QEDR_UVERBS(QUERY_SRQ) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) QEDR_UVERBS(MODIFY_SRQ) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) QEDR_UVERBS(POST_SRQ_RECV) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) QEDR_UVERBS(REG_MR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) QEDR_UVERBS(DEREG_MR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) QEDR_UVERBS(POLL_CQ) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) QEDR_UVERBS(POST_SEND) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) QEDR_UVERBS(POST_RECV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (IS_IWARP(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) rc = qedr_iw_register_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) qedr_roce_register_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) dev->ibdev.phys_port_cnt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) dev->ibdev.num_comp_vectors = dev->num_cnq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dev->ibdev.dev.parent = &dev->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) rdma_set_device_sysfs_group(&dev->ibdev, &qedr_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ib_set_device_ops(&dev->ibdev, &qedr_dev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) rc = ib_device_set_netdev(&dev->ibdev, dev->ndev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dma_set_max_seg_size(&dev->pdev->dev, UINT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return ib_register_device(&dev->ibdev, "qedr%d", &dev->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* This function allocates fast-path status block memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int qedr_alloc_mem_sb(struct qedr_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct qed_sb_info *sb_info, u16 sb_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct status_block_e4 *sb_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) dma_addr_t sb_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) sb_virt = dma_alloc_coherent(&dev->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (!sb_virt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) rc = dev->ops->common->sb_init(dev->cdev, sb_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) sb_virt, sb_phys, sb_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) QED_SB_TYPE_CNQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) pr_err("Status block initialization failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) dma_free_coherent(&dev->pdev->dev, sizeof(*sb_virt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) sb_virt, sb_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static void qedr_free_mem_sb(struct qedr_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct qed_sb_info *sb_info, int sb_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (sb_info->sb_virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dev->ops->common->sb_release(dev->cdev, sb_info, sb_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) QED_SB_TYPE_CNQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dma_free_coherent(&dev->pdev->dev, sizeof(*sb_info->sb_virt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) (void *)sb_info->sb_virt, sb_info->sb_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static void qedr_free_resources(struct qedr_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (IS_IWARP(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) destroy_workqueue(dev->iwarp_wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) for (i = 0; i < dev->num_cnq; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) kfree(dev->cnq_array);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) kfree(dev->sb_array);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) kfree(dev->sgid_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int qedr_alloc_resources(struct qedr_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct qed_chain_init_params params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .mode = QED_CHAIN_MODE_PBL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .intended_use = QED_CHAIN_USE_TO_CONSUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .cnt_type = QED_CHAIN_CNT_TYPE_U16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .elem_size = sizeof(struct regpair *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct qedr_cnq *cnq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) __le16 *cons_pi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) dev->sgid_tbl = kcalloc(QEDR_MAX_SGID, sizeof(union ib_gid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (!dev->sgid_tbl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) spin_lock_init(&dev->sgid_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) xa_init_flags(&dev->srqs, XA_FLAGS_LOCK_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (IS_IWARP(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) xa_init(&dev->qps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dev->iwarp_wq = create_singlethread_workqueue("qedr_iwarpq");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Allocate Status blocks for CNQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dev->sb_array = kcalloc(dev->num_cnq, sizeof(*dev->sb_array),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (!dev->sb_array) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) dev->cnq_array = kcalloc(dev->num_cnq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) sizeof(*dev->cnq_array), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!dev->cnq_array) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dev->sb_start = dev->ops->rdma_get_start_sb(dev->cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* Allocate CNQ PBLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) params.num_elems = min_t(u32, QED_RDMA_MAX_CNQ_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) QEDR_ROCE_MAX_CNQ_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) for (i = 0; i < dev->num_cnq; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) cnq = &dev->cnq_array[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) rc = qedr_alloc_mem_sb(dev, &dev->sb_array[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dev->sb_start + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) goto err3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) rc = dev->ops->common->chain_alloc(dev->cdev, &cnq->pbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ¶ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) goto err4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) cnq->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) cnq->sb = &dev->sb_array[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) cons_pi = dev->sb_array[i].sb_virt->pi_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) cnq->hw_cons_ptr = &cons_pi[QED_ROCE_PROTOCOL_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) cnq->index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) sprintf(cnq->name, "qedr%d@pci:%s", i, pci_name(dev->pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) DP_DEBUG(dev, QEDR_MSG_INIT, "cnq[%d].cons=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) i, qed_chain_get_cons_idx(&cnq->pbl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) err4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) err3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) for (--i; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) kfree(dev->cnq_array);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) kfree(dev->sb_array);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) kfree(dev->sgid_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static void qedr_pci_set_atomic(struct qedr_dev *dev, struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) int rc = pci_enable_atomic_ops_to_root(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) PCI_EXP_DEVCAP2_ATOMIC_COMP64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev->atomic_cap = IB_ATOMIC_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dev->atomic_cap = IB_ATOMIC_GLOB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static const struct qed_rdma_ops *qed_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static irqreturn_t qedr_irq_handler(int irq, void *handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) u16 hw_comp_cons, sw_comp_cons;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct qedr_cnq *cnq = handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct regpair *cq_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct qedr_cq *cq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) qed_sb_ack(cnq->sb, IGU_INT_DISABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) qed_sb_update_sb_idx(cnq->sb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* Align protocol-index and chain reads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) while (sw_comp_cons != hw_comp_cons) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) cq_handle = (struct regpair *)qed_chain_consume(&cnq->pbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) cq = (struct qedr_cq *)(uintptr_t)HILO_U64(cq_handle->hi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) cq_handle->lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (cq == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) DP_ERR(cnq->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) "Received NULL CQ cq_handle->hi=%d cq_handle->lo=%d sw_comp_cons=%d hw_comp_cons=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) cq_handle->hi, cq_handle->lo, sw_comp_cons,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) hw_comp_cons);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (cq->sig != QEDR_CQ_MAGIC_NUMBER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) DP_ERR(cnq->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) "Problem with cq signature, cq_handle->hi=%d ch_handle->lo=%d cq=%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) cq_handle->hi, cq_handle->lo, cq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) cq->arm_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (!cq->destroyed && cq->ibcq.comp_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) (*cq->ibcq.comp_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) (&cq->ibcq, cq->ibcq.cq_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* The CQ's CNQ notification counter is checked before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * destroying the CQ in a busy-wait loop that waits for all of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * the CQ's CNQ interrupts to be processed. It is increased
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * here, only after the completion handler, to ensure that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * the handler is not running when the CQ is destroyed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) cq->cnq_notif++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) cnq->n_comp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) qed_ops->rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) sw_comp_cons);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) qed_sb_ack(cnq->sb, IGU_INT_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static void qedr_sync_free_irqs(struct qedr_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) u32 vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) u16 idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) for (i = 0; i < dev->int_info.used_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (dev->int_info.msix_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) idx = i * dev->num_hwfns + dev->affin_hwfn_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) vector = dev->int_info.msix[idx].vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) synchronize_irq(vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) free_irq(vector, &dev->cnq_array[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) dev->int_info.used_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int qedr_req_msix_irqs(struct qedr_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int i, rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u16 idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (dev->num_cnq > dev->int_info.msix_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) DP_ERR(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) "Interrupt mismatch: %d CNQ queues > %d MSI-x vectors\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) dev->num_cnq, dev->int_info.msix_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) for (i = 0; i < dev->num_cnq; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) idx = i * dev->num_hwfns + dev->affin_hwfn_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) rc = request_irq(dev->int_info.msix[idx].vector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) qedr_irq_handler, 0, dev->cnq_array[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) &dev->cnq_array[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) DP_ERR(dev, "Request cnq %d irq failed\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) qedr_sync_free_irqs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) DP_DEBUG(dev, QEDR_MSG_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) "Requested cnq irq for %s [entry %d]. Cookie is at %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) dev->cnq_array[i].name, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) &dev->cnq_array[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) dev->int_info.used_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static int qedr_setup_irqs(struct qedr_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Learn Interrupt configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) rc = dev->ops->rdma_set_rdma_int(dev->cdev, dev->num_cnq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) rc = dev->ops->rdma_get_rdma_int(dev->cdev, &dev->int_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) DP_DEBUG(dev, QEDR_MSG_INIT, "get_rdma_int failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (dev->int_info.msix_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) DP_DEBUG(dev, QEDR_MSG_INIT, "rdma msix_cnt = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) dev->int_info.msix_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) rc = qedr_req_msix_irqs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs succeeded\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static int qedr_set_device_attr(struct qedr_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct qed_rdma_device *qed_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct qedr_device_attr *attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u32 page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* Part 1 - query core capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) qed_attr = dev->ops->rdma_query_device(dev->rdma_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* Part 2 - check capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) page_size = ~qed_attr->page_size_caps + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (page_size > PAGE_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) DP_ERR(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) "Kernel PAGE_SIZE is %ld which is smaller than minimum page size (%d) required by qedr\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) PAGE_SIZE, page_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* Part 3 - copy and update capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) attr = &dev->attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) attr->vendor_id = qed_attr->vendor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) attr->vendor_part_id = qed_attr->vendor_part_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) attr->hw_ver = qed_attr->hw_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) attr->fw_ver = qed_attr->fw_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) attr->node_guid = qed_attr->node_guid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) attr->sys_image_guid = qed_attr->sys_image_guid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) attr->max_cnq = qed_attr->max_cnq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) attr->max_sge = qed_attr->max_sge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) attr->max_inline = qed_attr->max_inline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) attr->max_sqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_SQE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) attr->max_rqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_RQE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) attr->max_qp_resp_rd_atomic_resc = qed_attr->max_qp_resp_rd_atomic_resc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) attr->max_qp_req_rd_atomic_resc = qed_attr->max_qp_req_rd_atomic_resc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) attr->max_dev_resp_rd_atomic_resc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) qed_attr->max_dev_resp_rd_atomic_resc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) attr->max_cq = qed_attr->max_cq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) attr->max_qp = qed_attr->max_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) attr->max_mr = qed_attr->max_mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) attr->max_mr_size = qed_attr->max_mr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) attr->max_cqe = min_t(u64, qed_attr->max_cqe, QEDR_MAX_CQES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) attr->max_mw = qed_attr->max_mw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) attr->max_mr_mw_fmr_pbl = qed_attr->max_mr_mw_fmr_pbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) attr->max_mr_mw_fmr_size = qed_attr->max_mr_mw_fmr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) attr->max_pd = qed_attr->max_pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) attr->max_ah = qed_attr->max_ah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) attr->max_pkey = qed_attr->max_pkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) attr->max_srq = qed_attr->max_srq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) attr->max_srq_wr = qed_attr->max_srq_wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) attr->dev_caps = qed_attr->dev_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) attr->page_size_caps = qed_attr->page_size_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) attr->dev_ack_delay = qed_attr->dev_ack_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) attr->reserved_lkey = qed_attr->reserved_lkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) attr->bad_pkey_counter = qed_attr->bad_pkey_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) attr->max_stats_queues = qed_attr->max_stats_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static void qedr_unaffiliated_event(void *context, u8 event_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) pr_err("unaffiliated event not implemented yet\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static void qedr_affiliated_event(void *context, u8 e_code, void *fw_handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define EVENT_TYPE_NOT_DEFINED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define EVENT_TYPE_CQ 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define EVENT_TYPE_QP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define EVENT_TYPE_SRQ 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct qedr_dev *dev = (struct qedr_dev *)context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct regpair *async_handle = (struct regpair *)fw_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u64 roce_handle64 = ((u64) async_handle->hi << 32) + async_handle->lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u8 event_type = EVENT_TYPE_NOT_DEFINED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct ib_event event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct ib_srq *ibsrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct qedr_srq *srq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct ib_cq *ibcq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct ib_qp *ibqp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct qedr_cq *cq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct qedr_qp *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) u16 srq_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (IS_ROCE(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) switch (e_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) case ROCE_ASYNC_EVENT_CQ_OVERFLOW_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) event.event = IB_EVENT_CQ_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) event_type = EVENT_TYPE_CQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) case ROCE_ASYNC_EVENT_SQ_DRAINED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) event.event = IB_EVENT_SQ_DRAINED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) event_type = EVENT_TYPE_QP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) case ROCE_ASYNC_EVENT_QP_CATASTROPHIC_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) event.event = IB_EVENT_QP_FATAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) event_type = EVENT_TYPE_QP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) case ROCE_ASYNC_EVENT_LOCAL_INVALID_REQUEST_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) event.event = IB_EVENT_QP_REQ_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) event_type = EVENT_TYPE_QP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) case ROCE_ASYNC_EVENT_LOCAL_ACCESS_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) event.event = IB_EVENT_QP_ACCESS_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) event_type = EVENT_TYPE_QP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) case ROCE_ASYNC_EVENT_SRQ_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) event.event = IB_EVENT_SRQ_LIMIT_REACHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) event_type = EVENT_TYPE_SRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) case ROCE_ASYNC_EVENT_SRQ_EMPTY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) event.event = IB_EVENT_SRQ_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) event_type = EVENT_TYPE_SRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) case ROCE_ASYNC_EVENT_XRC_DOMAIN_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) event.event = IB_EVENT_QP_ACCESS_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) event_type = EVENT_TYPE_QP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) case ROCE_ASYNC_EVENT_INVALID_XRCETH_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) event.event = IB_EVENT_QP_ACCESS_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) event_type = EVENT_TYPE_QP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) case ROCE_ASYNC_EVENT_XRC_SRQ_CATASTROPHIC_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) event.event = IB_EVENT_CQ_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) event_type = EVENT_TYPE_CQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) DP_ERR(dev, "unsupported event %d on handle=%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) e_code, roce_handle64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) switch (e_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) case QED_IWARP_EVENT_SRQ_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) event.event = IB_EVENT_SRQ_LIMIT_REACHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) event_type = EVENT_TYPE_SRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) case QED_IWARP_EVENT_SRQ_EMPTY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) event.event = IB_EVENT_SRQ_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) event_type = EVENT_TYPE_SRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) DP_ERR(dev, "unsupported event %d on handle=%llx\n", e_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) roce_handle64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) switch (event_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) case EVENT_TYPE_CQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) cq = (struct qedr_cq *)(uintptr_t)roce_handle64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (cq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ibcq = &cq->ibcq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (ibcq->event_handler) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) event.device = ibcq->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) event.element.cq = ibcq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) ibcq->event_handler(&event, ibcq->cq_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) WARN(1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) "Error: CQ event with NULL pointer ibcq. Handle=%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) roce_handle64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) DP_ERR(dev, "CQ event %d on handle %p\n", e_code, cq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) case EVENT_TYPE_QP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) qp = (struct qedr_qp *)(uintptr_t)roce_handle64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (qp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) ibqp = &qp->ibqp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (ibqp->event_handler) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) event.device = ibqp->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) event.element.qp = ibqp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) ibqp->event_handler(&event, ibqp->qp_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) WARN(1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) "Error: QP event with NULL pointer ibqp. Handle=%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) roce_handle64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) DP_ERR(dev, "QP event %d on handle %p\n", e_code, qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) case EVENT_TYPE_SRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) srq_id = (u16)roce_handle64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) xa_lock_irqsave(&dev->srqs, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) srq = xa_load(&dev->srqs, srq_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (srq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) ibsrq = &srq->ibsrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (ibsrq->event_handler) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) event.device = ibsrq->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) event.element.srq = ibsrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) ibsrq->event_handler(&event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ibsrq->srq_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) DP_NOTICE(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) "SRQ event with NULL pointer ibsrq. Handle=%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) roce_handle64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) xa_unlock_irqrestore(&dev->srqs, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) DP_NOTICE(dev, "SRQ event %d on handle %p\n", e_code, srq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static int qedr_init_hw(struct qedr_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct qed_rdma_add_user_out_params out_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct qed_rdma_start_in_params *in_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct qed_rdma_cnq_params *cur_pbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct qed_rdma_events events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) dma_addr_t p_phys_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) u32 page_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) in_params = kzalloc(sizeof(*in_params), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (!in_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) in_params->desired_cnq = dev->num_cnq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) for (i = 0; i < dev->num_cnq; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) cur_pbl = &in_params->cnq_pbl_list[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) page_cnt = qed_chain_get_page_cnt(&dev->cnq_array[i].pbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) cur_pbl->num_pbl_pages = page_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) p_phys_table = qed_chain_get_pbl_phys(&dev->cnq_array[i].pbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) cur_pbl->pbl_ptr = (u64)p_phys_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) events.affiliated_event = qedr_affiliated_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) events.unaffiliated_event = qedr_unaffiliated_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) events.context = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) in_params->events = &events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) in_params->cq_mode = QED_RDMA_CQ_MODE_32_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) in_params->max_mtu = dev->ndev->mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) dev->iwarp_max_mtu = dev->ndev->mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) ether_addr_copy(&in_params->mac_addr[0], dev->ndev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) rc = dev->ops->rdma_init(dev->cdev, in_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) rc = dev->ops->rdma_add_user(dev->rdma_ctx, &out_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) dev->db_addr = out_params.dpi_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) dev->db_phys_addr = out_params.dpi_phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) dev->db_size = out_params.dpi_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) dev->dpi = out_params.dpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) rc = qedr_set_device_attr(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) kfree(in_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) DP_ERR(dev, "Init HW Failed rc = %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static void qedr_stop_hw(struct qedr_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) dev->ops->rdma_remove_user(dev->rdma_ctx, dev->dpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) dev->ops->rdma_stop(dev->rdma_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) struct qed_dev_rdma_info dev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct qedr_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) dev = ib_alloc_device(qedr_dev, ibdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) pr_err("Unable to allocate ib device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) DP_DEBUG(dev, QEDR_MSG_INIT, "qedr add device called\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) dev->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) dev->ndev = ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) dev->cdev = cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) qed_ops = qed_get_rdma_ops();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (!qed_ops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) DP_ERR(dev, "Failed to get qed roce operations\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) goto init_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) dev->ops = qed_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) rc = qed_ops->fill_dev_info(cdev, &dev_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) goto init_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) dev->user_dpm_enabled = dev_info.user_dpm_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) dev->rdma_type = dev_info.rdma_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) dev->num_hwfns = dev_info.common.num_hwfns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (IS_IWARP(dev) && QEDR_IS_CMT(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) rc = dev->ops->iwarp_set_engine_affin(cdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) DP_ERR(dev, "iWARP is disabled over a 100g device Enabling it may impact L2 performance. To enable it run devlink dev param set <dev> name iwarp_cmt value true cmode runtime\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) goto init_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) dev->affin_hwfn_idx = dev->ops->common->get_affin_hwfn_idx(cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) dev->rdma_ctx = dev->ops->rdma_get_rdma_ctx(cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) dev->num_cnq = dev->ops->rdma_get_min_cnq_msix(cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (!dev->num_cnq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) DP_ERR(dev, "Failed. At least one CNQ is required.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) goto init_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) dev->wq_multiplier = QEDR_WQ_MULTIPLIER_DFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) qedr_pci_set_atomic(dev, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) rc = qedr_alloc_resources(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) goto init_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) rc = qedr_init_hw(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) goto alloc_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) rc = qedr_setup_irqs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) goto irq_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) rc = qedr_register_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) DP_ERR(dev, "Unable to allocate register device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) goto reg_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) DP_DEBUG(dev, QEDR_MSG_INIT, "qedr driver loaded successfully\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) reg_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) qedr_sync_free_irqs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) irq_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) qedr_stop_hw(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) alloc_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) qedr_free_resources(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) init_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) ib_dealloc_device(&dev->ibdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) DP_ERR(dev, "qedr driver load failed rc=%d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static void qedr_remove(struct qedr_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /* First unregister with stack to stop all the active traffic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * of the registered clients.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) ib_unregister_device(&dev->ibdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) qedr_stop_hw(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) qedr_sync_free_irqs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) qedr_free_resources(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (IS_IWARP(dev) && QEDR_IS_CMT(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) dev->ops->iwarp_set_engine_affin(dev->cdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) ib_dealloc_device(&dev->ibdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static void qedr_close(struct qedr_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (test_and_clear_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static void qedr_shutdown(struct qedr_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) qedr_close(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) qedr_remove(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static void qedr_open(struct qedr_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static void qedr_mac_address_change(struct qedr_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) union ib_gid *sgid = &dev->sgid_tbl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) u8 guid[8], mac_addr[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /* Update SGID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ether_addr_copy(&mac_addr[0], dev->ndev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) guid[0] = mac_addr[0] ^ 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) guid[1] = mac_addr[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) guid[2] = mac_addr[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) guid[3] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) guid[4] = 0xfe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) guid[5] = mac_addr[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) guid[6] = mac_addr[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) guid[7] = mac_addr[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) sgid->global.subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) memcpy(&sgid->raw[8], guid, sizeof(guid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /* Update LL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) rc = dev->ops->ll2_set_mac_filter(dev->cdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) dev->gsi_ll2_mac_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) dev->ndev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) ether_addr_copy(dev->gsi_ll2_mac_address, dev->ndev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_GID_CHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) DP_ERR(dev, "Error updating mac filter\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) /* event handling via NIC driver ensures that all the NIC specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) * initialization done before RoCE driver notifies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) * event to stack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static void qedr_notify(struct qedr_dev *dev, enum qede_rdma_event event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) case QEDE_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) qedr_open(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) case QEDE_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) qedr_close(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) case QEDE_CLOSE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) qedr_shutdown(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) case QEDE_CHANGE_ADDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) qedr_mac_address_change(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) case QEDE_CHANGE_MTU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (rdma_protocol_iwarp(&dev->ibdev, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (dev->ndev->mtu != dev->iwarp_max_mtu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) DP_NOTICE(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) "Mtu was changed from %d to %d. This will not take affect for iWARP until qedr is reloaded\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) dev->iwarp_max_mtu, dev->ndev->mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) pr_err("Event not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) static struct qedr_driver qedr_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .name = "qedr_driver",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .add = qedr_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .remove = qedr_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .notify = qedr_notify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static int __init qedr_init_module(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) return qede_rdma_register_driver(&qedr_drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) static void __exit qedr_exit_module(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) qede_rdma_unregister_driver(&qedr_drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) module_init(qedr_init_module);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) module_exit(qedr_exit_module);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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