^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* This file is part of the Emulex RoCE Device Driver for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * RoCE (RDMA over Converged Ethernet) adapters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2012-2015 Emulex. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * EMULEX and SLI are trademarks of Emulex.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * www.emulex.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This software is available to you under a choice of one of two licenses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * You may choose to be licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * License (GPL) Version 2, available from the file COPYING in the main
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * directory of this source tree, or the BSD license below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * - Redistributions of source code must retain the above copyright notice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * - Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * notice, this list of conditions and the following disclaimer in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * the documentation and/or other materials provided with the distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Contact Information:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * linux-drivers@emulex.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Emulex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * 3333 Susan Street
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * Costa Mesa, CA 92626
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #ifndef __OCRDMA_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define __OCRDMA_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <rdma/ib_verbs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <rdma/ib_user_verbs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <rdma/ib_addr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <be_roce.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include "ocrdma_sli.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OCRDMA_ROCE_DRV_VERSION "11.0.0.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OCRDMA_ROCE_DRV_DESC "Emulex OneConnect RoCE Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OCRDMA_NODE_DESC "Emulex OneConnect RoCE HCA"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OC_NAME_SH OCRDMA_NODE_DESC "(Skyhawk)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OC_NAME_UNKNOWN OCRDMA_NODE_DESC "(Unknown)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OC_SKH_DEVICE_PF 0x720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OC_SKH_DEVICE_VF 0x728
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OCRDMA_MAX_AH 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OCRDMA_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define convert_to_64bit(lo, hi) ((u64)hi << 32 | (u64)lo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define EQ_INTR_PER_SEC_THRSH_HI 150000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define EQ_INTR_PER_SEC_THRSH_LOW 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define EQ_AIC_MAX_EQD 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define EQ_AIC_MIN_EQD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) void ocrdma_eqd_set_task(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct ocrdma_dev_attr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u8 fw_ver[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 vendor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u16 max_pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u16 max_dpp_pds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u16 max_cq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u16 max_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u16 max_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u16 max_wqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u16 max_rqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u16 max_srq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 max_inline_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int max_send_sge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int max_recv_sge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int max_srq_sge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int max_rdma_sge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int max_mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u64 max_mr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 max_num_mr_pbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int max_mw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int max_map_per_fmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int max_pages_per_frmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u16 max_ord_per_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u16 max_ird_per_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int device_cap_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u8 cq_overflow_detect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u8 srq_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 wqe_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 rqe_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 ird_page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u8 local_ca_ack_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u8 ird;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u8 num_ird_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u8 udp_encap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct ocrdma_dma_mem {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) void *va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dma_addr_t pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct ocrdma_pbl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) void *va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dma_addr_t pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct ocrdma_queue_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) void *va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u16 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u16 entry_size; /* Size of an element in the queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u16 id; /* qid, where to ring the doorbell. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u16 head, tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) bool created;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct ocrdma_aic_obj { /* Adaptive interrupt coalescing (AIC) info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 prev_eqd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u64 eq_intr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u64 prev_eq_intr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct ocrdma_eq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct ocrdma_queue_info q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int cq_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct ocrdma_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) char irq_name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct ocrdma_aic_obj aic_obj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct ocrdma_mq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct ocrdma_queue_info sq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct ocrdma_queue_info cq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) bool rearm_cq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct mqe_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct mutex lock; /* for serializing mailbox commands on MQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) wait_queue_head_t cmd_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u16 cqe_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u16 ext_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) bool cmd_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) bool fw_error_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct ocrdma_hw_mr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 lkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u8 fr_mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u8 remote_atomic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u8 remote_rd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u8 remote_wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u8 local_rd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u8 local_wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u8 mw_bind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u8 rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u64 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct ocrdma_pbl *pbl_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 num_pbls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 num_pbes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 pbl_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 pbe_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u64 va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct ocrdma_mr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct ib_mr ibmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct ib_umem *umem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct ocrdma_hw_mr hwmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u64 *pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 npages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct ocrdma_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct ocrdma_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct ocrdma_pd_resource_mgr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 pd_norm_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u16 pd_norm_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u16 pd_norm_thrsh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u16 max_normal_pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 pd_dpp_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u16 pd_dpp_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u16 pd_dpp_thrsh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u16 max_dpp_pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u16 dpp_page_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned long *pd_norm_bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned long *pd_dpp_bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) bool pd_prealloc_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct stats_mem {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct ocrdma_mqe mqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) void *va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dma_addr_t pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) char *debugfs_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct phy_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u16 auto_speeds_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u16 fixed_speeds_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u16 phy_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u16 interface_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) enum ocrdma_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) OCRDMA_FLAGS_LINK_STATUS_INIT = 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct ocrdma_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct ib_device ibdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct ocrdma_dev_attr attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct mutex dev_lock; /* provides syncronise access to device data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) spinlock_t flush_q_lock ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct ocrdma_cq **cq_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct ocrdma_qp **qp_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct ocrdma_eq *eq_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int eq_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct delayed_work eqd_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u16 base_eqid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u16 max_eq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* provided synchronization to sgid table for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * updating gid entries triggered by notifier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) spinlock_t sgid_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int gsi_qp_created;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct ocrdma_cq *gsi_sqcq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct ocrdma_cq *gsi_rqcq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct ocrdma_av *va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dma_addr_t pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 num_ah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* provide synchronization for av
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * entry allocations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u32 ahid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct ocrdma_pbl pbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) } av_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) void *mbx_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct ocrdma_mq mq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct mqe_ctx mqe_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct be_dev_info nic_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct phy_info phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) char model_number[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u32 hba_port_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct list_head entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u64 *stag_arr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u8 sl; /* service level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) bool pfc_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) atomic_t update_sl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u16 pvid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u32 asic_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ulong last_stats_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct mutex stats_lock; /* provide synch for debugfs operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct stats_mem stats_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct ocrdma_stats rsrc_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct ocrdma_stats rx_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct ocrdma_stats wqe_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct ocrdma_stats tx_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct ocrdma_stats db_err_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct ocrdma_stats tx_qp_err_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct ocrdma_stats rx_qp_err_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct ocrdma_stats tx_dbg_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct ocrdma_stats rx_dbg_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct ocrdma_stats driver_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct ocrdma_stats reset_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct dentry *dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) atomic_t async_err_stats[OCRDMA_MAX_ASYNC_ERRORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) atomic_t cqe_err_stats[OCRDMA_MAX_CQE_ERR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct ocrdma_pd_resource_mgr *pd_mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct ocrdma_cq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct ib_cq ibcq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct ocrdma_cqe *va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u32 phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u32 getp; /* pointer to pending wrs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * return to stack, wrap arounds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * at max_hw_cqe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 max_hw_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) bool phase_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) spinlock_t cq_lock ____cacheline_aligned; /* provide synchronization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * to cq polling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* syncronizes cq completion handler invoked from multiple context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) spinlock_t comp_handler_lock ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u16 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u16 eqn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct ocrdma_ucontext *ucontext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dma_addr_t pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 cqe_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* head of all qp's sq and rq for which cqes need to be flushed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * by the software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct list_head sq_head, rq_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct ocrdma_pd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct ib_pd ibpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct ocrdma_ucontext *uctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int num_dpp_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u32 dpp_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) bool dpp_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct ocrdma_ah {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct ib_ah ibah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct ocrdma_av *av;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u16 sgid_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u8 hdr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct ocrdma_qp_hwq_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u8 *va; /* virtual address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u32 max_sges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u32 head, tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u32 entry_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u32 max_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u32 max_wqe_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u16 dbid; /* qid, where to ring the doorbell. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dma_addr_t pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct ocrdma_srq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct ib_srq ibsrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u8 __iomem *db;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct ocrdma_qp_hwq_info rq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u64 *rqe_wr_id_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u32 *idx_bit_fields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u32 bit_fields_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* provide synchronization to multiple context(s) posting rqe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) spinlock_t q_lock ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct ocrdma_pd *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct ocrdma_qp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct ib_qp ibqp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u8 __iomem *sq_db;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct ocrdma_qp_hwq_info sq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) uint64_t wrid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) uint16_t dpp_wqe_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) uint16_t dpp_wqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) uint8_t signaled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) uint8_t rsvd[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) } *wqe_wr_id_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u32 max_inline_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* provide synchronization to multiple context(s) posting wqe, rqe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) spinlock_t q_lock ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct ocrdma_cq *sq_cq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* list maintained per CQ to flush SQ errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct list_head sq_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u8 __iomem *rq_db;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct ocrdma_qp_hwq_info rq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u64 *rqe_wr_id_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct ocrdma_cq *rq_cq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct ocrdma_srq *srq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* list maintained per CQ to flush RQ errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct list_head rq_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) enum ocrdma_qp_state state; /* QP state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) int cap_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u32 max_ord, max_ird;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct ocrdma_pd *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) enum ib_qp_type qp_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int sgid_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u32 qkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) bool dpp_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u8 *ird_q_va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) bool signaled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct ocrdma_ucontext {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct ib_ucontext ibucontext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct list_head mm_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct mutex mm_list_lock; /* protects list entries of mm type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct ocrdma_pd *cntxt_pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int pd_in_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u32 *va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dma_addr_t pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) } ah_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct ocrdma_mm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u64 phy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned long len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) } key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct list_head entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static inline struct ocrdma_dev *get_ocrdma_dev(struct ib_device *ibdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return container_of(ibdev, struct ocrdma_dev, ibdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static inline struct ocrdma_ucontext *get_ocrdma_ucontext(struct ib_ucontext
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) *ibucontext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return container_of(ibucontext, struct ocrdma_ucontext, ibucontext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static inline struct ocrdma_pd *get_ocrdma_pd(struct ib_pd *ibpd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return container_of(ibpd, struct ocrdma_pd, ibpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static inline struct ocrdma_cq *get_ocrdma_cq(struct ib_cq *ibcq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return container_of(ibcq, struct ocrdma_cq, ibcq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static inline struct ocrdma_qp *get_ocrdma_qp(struct ib_qp *ibqp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return container_of(ibqp, struct ocrdma_qp, ibqp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static inline struct ocrdma_mr *get_ocrdma_mr(struct ib_mr *ibmr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return container_of(ibmr, struct ocrdma_mr, ibmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static inline struct ocrdma_ah *get_ocrdma_ah(struct ib_ah *ibah)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return container_of(ibah, struct ocrdma_ah, ibah);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static inline struct ocrdma_srq *get_ocrdma_srq(struct ib_srq *ibsrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return container_of(ibsrq, struct ocrdma_srq, ibsrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static inline int is_cqe_valid(struct ocrdma_cq *cq, struct ocrdma_cqe *cqe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) int cqe_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) cqe_valid = le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return (cqe_valid == cq->phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static inline int is_cqe_for_sq(struct ocrdma_cqe *cqe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return (le32_to_cpu(cqe->flags_status_srcqpn) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) OCRDMA_CQE_QTYPE) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static inline int is_cqe_invalidated(struct ocrdma_cqe *cqe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return (le32_to_cpu(cqe->flags_status_srcqpn) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) OCRDMA_CQE_INVALIDATE) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static inline int is_cqe_imm(struct ocrdma_cqe *cqe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return (le32_to_cpu(cqe->flags_status_srcqpn) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) OCRDMA_CQE_IMM) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static inline int is_cqe_wr_imm(struct ocrdma_cqe *cqe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return (le32_to_cpu(cqe->flags_status_srcqpn) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) OCRDMA_CQE_WRITE_IMM) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static inline int ocrdma_resolve_dmac(struct ocrdma_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct rdma_ah_attr *ah_attr, u8 *mac_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct in6_addr in6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) memcpy(&in6, rdma_ah_read_grh(ah_attr)->dgid.raw, sizeof(in6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (rdma_is_multicast_addr(&in6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) rdma_get_mcast_mac(&in6, mac_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) else if (rdma_link_local_addr(&in6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) rdma_get_ll_mac(&in6, mac_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) memcpy(mac_addr, ah_attr->roce.dmac, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static inline char *hca_name(struct ocrdma_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) switch (dev->nic_info.pdev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) case OC_SKH_DEVICE_PF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) case OC_SKH_DEVICE_VF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return OC_NAME_SH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return OC_NAME_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static inline int ocrdma_get_eq_table_index(struct ocrdma_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) int eqid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) int indx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) for (indx = 0; indx < dev->eq_cnt; indx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (dev->eq_tbl[indx].q.id == eqid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return indx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static inline u8 ocrdma_get_asic_type(struct ocrdma_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (dev->nic_info.dev_family == 0xF && !dev->asic_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) pci_read_config_dword(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) dev->nic_info.pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) OCRDMA_SLI_ASIC_ID_OFFSET, &dev->asic_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return (dev->asic_id & OCRDMA_SLI_ASIC_GEN_NUM_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) OCRDMA_SLI_ASIC_GEN_NUM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static inline u8 ocrdma_get_pfc_prio(u8 *pfc, u8 prio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return *(pfc + prio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static inline u8 ocrdma_get_app_prio(u8 *app_prio, u8 prio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return *(app_prio + prio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static inline u8 ocrdma_is_enabled_and_synced(u32 state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) { /* May also be used to interpret TC-state, QCN-state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * Appl-state and Logical-link-state in future.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return (state & OCRDMA_STATE_FLAG_ENABLED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) (state & OCRDMA_STATE_FLAG_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static inline u8 ocrdma_get_ae_link_state(u32 ae_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return ((ae_state & OCRDMA_AE_LSC_LS_MASK) >> OCRDMA_AE_LSC_LS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static inline bool ocrdma_is_udp_encap_supported(struct ocrdma_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return (dev->attr.udp_encap & OCRDMA_L3_TYPE_IPV4) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) (dev->attr.udp_encap & OCRDMA_L3_TYPE_IPV6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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