^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This software is available to you under a choice of one of two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * licenses. You may choose to be licensed under the terms of the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * General Public License (GPL) Version 2, available from the file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * COPYING in the main directory of this source tree, or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * OpenIB.org BSD license below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Redistribution and use in source and binary forms, with or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * without modification, are permitted provided that the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * conditions are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * - Redistributions of source code must retain the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * copyright notice, this list of conditions and the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * - Redistributions in binary form must reproduce the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * copyright notice, this list of conditions and the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * disclaimer in the documentation and/or other materials
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * provided with the distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <rdma/ib_user_verbs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "mlx4_ib.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static u32 convert_access(int acc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX4_PERM_ATOMIC : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) (acc & IB_ACCESS_REMOTE_WRITE ? MLX4_PERM_REMOTE_WRITE : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) (acc & IB_ACCESS_REMOTE_READ ? MLX4_PERM_REMOTE_READ : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) (acc & IB_ACCESS_LOCAL_WRITE ? MLX4_PERM_LOCAL_WRITE : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) (acc & IB_ACCESS_MW_BIND ? MLX4_PERM_BIND_MW : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MLX4_PERM_LOCAL_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static enum mlx4_mw_type to_mlx4_type(enum ib_mw_type type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) case IB_MW_TYPE_1: return MLX4_MW_TYPE_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) case IB_MW_TYPE_2: return MLX4_MW_TYPE_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) default: return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct ib_mr *mlx4_ib_get_dma_mr(struct ib_pd *pd, int acc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct mlx4_ib_mr *mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) mr = kzalloc(sizeof(*mr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (!mr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) err = mlx4_mr_alloc(to_mdev(pd->device)->dev, to_mpd(pd)->pdn, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ~0ull, convert_access(acc), 0, 0, &mr->mmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) err = mlx4_mr_enable(to_mdev(pd->device)->dev, &mr->mmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) goto err_mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) mr->ibmr.rkey = mr->ibmr.lkey = mr->mmr.key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) mr->umem = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return &mr->ibmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) err_mr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) (void) mlx4_mr_free(to_mdev(pd->device)->dev, &mr->mmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) err_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) kfree(mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MLX4_MAX_MTT_SHIFT = 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static int mlx4_ib_umem_write_mtt_block(struct mlx4_ib_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct mlx4_mtt *mtt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u64 mtt_size, u64 mtt_shift, u64 len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u64 cur_start_addr, u64 *pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int *start_index, int *npages)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u64 cur_end_addr = cur_start_addr + len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u64 cur_end_addr_aligned = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u64 mtt_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) len += (cur_start_addr & (mtt_size - 1ULL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) cur_end_addr_aligned = round_up(cur_end_addr, mtt_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) len += (cur_end_addr_aligned - cur_end_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (len & (mtt_size - 1ULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) pr_warn("write_block: len %llx is not aligned to mtt_size %llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) len, mtt_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) mtt_entries = (len >> mtt_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * Align the MTT start address to the mtt_size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * Required to handle cases when the MR starts in the middle of an MTT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * record. Was not required in old code since the physical addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * provided by the dma subsystem were page aligned, which was also the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * MTT size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) cur_start_addr = round_down(cur_start_addr, mtt_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* A new block is started ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) for (k = 0; k < mtt_entries; ++k) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) pages[*npages] = cur_start_addr + (mtt_size * k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) (*npages)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Be friendly to mlx4_write_mtt() and pass it chunks of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * appropriate size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (*npages == PAGE_SIZE / sizeof(u64)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) err = mlx4_write_mtt(dev->dev, mtt, *start_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) *npages, pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) (*start_index) += *npages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) *npages = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static inline u64 alignment_of(u64 ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return ilog2(ptr & (~(ptr - 1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int mlx4_ib_umem_calc_block_mtt(u64 next_block_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u64 current_block_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u64 block_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Check whether the alignment of the new block is aligned as well as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * the previous block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Block address must start with zeros till size of entity_size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if ((next_block_start & ((1ULL << block_shift) - 1ULL)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * It is not as well aligned as the previous block-reduce the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * mtt size accordingly. Here we take the last right bit which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * is 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) block_shift = alignment_of(next_block_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * Check whether the alignment of the end of previous block - is it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * aligned as well as the start of the block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (((current_block_end) & ((1ULL << block_shift) - 1ULL)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * It is not as well aligned as the start of the block -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * reduce the mtt size accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) block_shift = alignment_of(current_block_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return block_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int mlx4_ib_umem_write_mtt(struct mlx4_ib_dev *dev, struct mlx4_mtt *mtt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct ib_umem *umem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u64 *pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u64 len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u64 mtt_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u64 cur_start_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u64 mtt_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int start_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int npages = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pages = (u64 *) __get_free_page(GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (!pages)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) mtt_shift = mtt->page_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) mtt_size = 1ULL << mtt_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) for_each_sg(umem->sg_head.sgl, sg, umem->nmap, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (cur_start_addr + len == sg_dma_address(sg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* still the same block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) len += sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * A new block is started ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * If len is malaligned, write an extra mtt entry to cover the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * misaligned area (round up the division)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) err = mlx4_ib_umem_write_mtt_block(dev, mtt, mtt_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) mtt_shift, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) cur_start_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) pages, &start_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) &npages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) cur_start_addr = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) len = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Handle the last block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * If len is malaligned, write an extra mtt entry to cover
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * the misaligned area (round up the division)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) err = mlx4_ib_umem_write_mtt_block(dev, mtt, mtt_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) mtt_shift, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) cur_start_addr, pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) &start_index, &npages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (npages)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) err = mlx4_write_mtt(dev->dev, mtt, start_index, npages, pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) free_page((unsigned long) pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * Calculate optimal mtt size based on contiguous pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * Function will return also the number of pages that are not aligned to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * calculated mtt_size to be added to total number of pages. For that we should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * check the first chunk length & last chunk length and if not aligned to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * mtt_size we should increment the non_aligned_pages number. All chunks in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * middle already handled as part of mtt shift calculation for both their start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * & end addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int mlx4_ib_umem_calc_optimal_mtt_size(struct ib_umem *umem, u64 start_va,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int *num_of_mtts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u64 block_shift = MLX4_MAX_MTT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u64 min_shift = PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u64 last_block_aligned_end = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u64 current_block_start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u64 first_block_start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u64 current_block_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u64 last_block_end = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u64 current_block_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u64 misalignment_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u64 next_block_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u64 total_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) *num_of_mtts = ib_umem_num_dma_blocks(umem, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) for_each_sg(umem->sg_head.sgl, sg, umem->nmap, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * Initialization - save the first chunk start as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * current_block_start - block means contiguous pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (current_block_len == 0 && current_block_start == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) current_block_start = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) first_block_start = current_block_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * Find the bits that are different between the physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * address and the virtual address for the start of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * MR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * umem_get aligned the start_va to a page boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * Therefore, we need to align the start va to the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * misalignment_bits is needed to handle the case of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * single memory region. In this case, the rest of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * logic will not reduce the block size. If we use a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * block size which is bigger than the alignment of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * misalignment bits, we might use the virtual page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * number instead of the physical page number, resulting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * in access to the wrong data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) misalignment_bits =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) (start_va & (~(((u64)(PAGE_SIZE)) - 1ULL))) ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) current_block_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) block_shift = min(alignment_of(misalignment_bits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) block_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * Go over the scatter entries and check if they continue the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * previous scatter entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) next_block_start = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) current_block_end = current_block_start + current_block_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* If we have a split (non-contig.) between two blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (current_block_end != next_block_start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) block_shift = mlx4_ib_umem_calc_block_mtt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) (next_block_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) current_block_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) block_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * If we reached the minimum shift for 4k page we stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * the loop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (block_shift <= min_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * If not saved yet we are in first block - we save the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * length of first block to calculate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * non_aligned_pages number at the end.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) total_len += current_block_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* Start a new block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) current_block_start = next_block_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) current_block_len = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* The scatter entry is another part of the current block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * increase the block size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * An entry in the scatter can be larger than 4k (page) as of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * dma mapping which merge some blocks together.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) current_block_len += sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Account for the last block in the total len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) total_len += current_block_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* Add to the first block the misalignment that it suffers from. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) total_len += (first_block_start & ((1ULL << block_shift) - 1ULL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) last_block_end = current_block_start + current_block_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) last_block_aligned_end = round_up(last_block_end, 1ULL << block_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) total_len += (last_block_aligned_end - last_block_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (total_len & ((1ULL << block_shift) - 1ULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) pr_warn("misaligned total length detected (%llu, %llu)!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) total_len, block_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) *num_of_mtts = total_len >> block_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (block_shift < min_shift) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * If shift is less than the min we set a warning and return the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * min shift.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) pr_warn("umem_calc_optimal_mtt_size - unexpected shift %lld\n", block_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) block_shift = min_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return block_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static struct ib_umem *mlx4_get_umem_mr(struct ib_device *device, u64 start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u64 length, int access_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * Force registering the memory as writable if the underlying pages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * are writable. This is so rereg can change the access permissions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * from readable to writable without having to run through ib_umem_get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (!ib_access_writable(access_flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned long untagged_start = untagged_addr(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct vm_area_struct *vma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) mmap_read_lock(current->mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * FIXME: Ideally this would iterate over all the vmas that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * cover the memory, but for now it requires a single vma to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * entirely cover the MR to support RO mappings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) vma = find_vma(current->mm, untagged_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (vma && vma->vm_end >= untagged_start + length &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) vma->vm_start <= untagged_start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (vma->vm_flags & VM_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) access_flags |= IB_ACCESS_LOCAL_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) access_flags |= IB_ACCESS_LOCAL_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) mmap_read_unlock(current->mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return ib_umem_get(device, start, length, access_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct ib_mr *mlx4_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u64 virt_addr, int access_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct ib_udata *udata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct mlx4_ib_dev *dev = to_mdev(pd->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct mlx4_ib_mr *mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) mr = kzalloc(sizeof(*mr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (!mr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) mr->umem = mlx4_get_umem_mr(pd->device, start, length, access_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (IS_ERR(mr->umem)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) err = PTR_ERR(mr->umem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) shift = mlx4_ib_umem_calc_optimal_mtt_size(mr->umem, start, &n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) err = mlx4_mr_alloc(dev->dev, to_mpd(pd)->pdn, virt_addr, length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) convert_access(access_flags), n, shift, &mr->mmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) goto err_umem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) err = mlx4_ib_umem_write_mtt(dev, &mr->mmr.mtt, mr->umem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) goto err_mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) err = mlx4_mr_enable(dev->dev, &mr->mmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) goto err_mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) mr->ibmr.rkey = mr->ibmr.lkey = mr->mmr.key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) mr->ibmr.length = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) mr->ibmr.page_size = 1U << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return &mr->ibmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) err_mr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) (void) mlx4_mr_free(to_mdev(pd->device)->dev, &mr->mmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) err_umem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ib_umem_release(mr->umem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) err_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) kfree(mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) int mlx4_ib_rereg_user_mr(struct ib_mr *mr, int flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) u64 start, u64 length, u64 virt_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int mr_access_flags, struct ib_pd *pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct ib_udata *udata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct mlx4_ib_dev *dev = to_mdev(mr->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct mlx4_ib_mr *mmr = to_mmr(mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct mlx4_mpt_entry *mpt_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct mlx4_mpt_entry **pmpt_entry = &mpt_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* Since we synchronize this call and mlx4_ib_dereg_mr via uverbs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * we assume that the calls can't run concurrently. Otherwise, a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * race exists.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) err = mlx4_mr_hw_get_mpt(dev->dev, &mmr->mmr, &pmpt_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (flags & IB_MR_REREG_PD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) err = mlx4_mr_hw_change_pd(dev->dev, *pmpt_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) to_mpd(pd)->pdn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) goto release_mpt_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (flags & IB_MR_REREG_ACCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (ib_access_writable(mr_access_flags) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) !mmr->umem->writable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) err = -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) goto release_mpt_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) err = mlx4_mr_hw_change_access(dev->dev, *pmpt_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) convert_access(mr_access_flags));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) goto release_mpt_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (flags & IB_MR_REREG_TRANS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) mlx4_mr_rereg_mem_cleanup(dev->dev, &mmr->mmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ib_umem_release(mmr->umem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) mmr->umem = mlx4_get_umem_mr(mr->device, start, length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) mr_access_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (IS_ERR(mmr->umem)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) err = PTR_ERR(mmr->umem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* Prevent mlx4_ib_dereg_mr from free'ing invalid pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) mmr->umem = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) goto release_mpt_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) n = ib_umem_num_dma_blocks(mmr->umem, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) shift = PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) err = mlx4_mr_rereg_mem_write(dev->dev, &mmr->mmr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) virt_addr, length, n, shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) *pmpt_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ib_umem_release(mmr->umem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) goto release_mpt_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) mmr->mmr.iova = virt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) mmr->mmr.size = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) err = mlx4_ib_umem_write_mtt(dev, &mmr->mmr.mtt, mmr->umem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) mlx4_mr_rereg_mem_cleanup(dev->dev, &mmr->mmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ib_umem_release(mmr->umem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) goto release_mpt_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* If we couldn't transfer the MR to the HCA, just remember to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * return a failure. But dereg_mr will free the resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) err = mlx4_mr_hw_write_mpt(dev->dev, &mmr->mmr, pmpt_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (!err && flags & IB_MR_REREG_ACCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) mmr->mmr.access = mr_access_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) release_mpt_entry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) mlx4_mr_hw_put_mpt(dev->dev, pmpt_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) mlx4_alloc_priv_pages(struct ib_device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct mlx4_ib_mr *mr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) int max_pages)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* Ensure that size is aligned to DMA cacheline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * requirements.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * max_pages is limited to MLX4_MAX_FAST_REG_PAGES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * so page_map_size will never cross PAGE_SIZE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) mr->page_map_size = roundup(max_pages * sizeof(u64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) MLX4_MR_PAGES_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* Prevent cross page boundary allocation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) mr->pages = (__be64 *)get_zeroed_page(GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (!mr->pages)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) mr->page_map = dma_map_single(device->dev.parent, mr->pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) mr->page_map_size, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (dma_mapping_error(device->dev.parent, mr->page_map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) free_page((unsigned long)mr->pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) mlx4_free_priv_pages(struct mlx4_ib_mr *mr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (mr->pages) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct ib_device *device = mr->ibmr.device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dma_unmap_single(device->dev.parent, mr->page_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) mr->page_map_size, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) free_page((unsigned long)mr->pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) mr->pages = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) int mlx4_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct mlx4_ib_mr *mr = to_mmr(ibmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) mlx4_free_priv_pages(mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ret = mlx4_mr_free(to_mdev(ibmr->device)->dev, &mr->mmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (mr->umem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ib_umem_release(mr->umem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) kfree(mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) int mlx4_ib_alloc_mw(struct ib_mw *ibmw, struct ib_udata *udata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct mlx4_ib_dev *dev = to_mdev(ibmw->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct mlx4_ib_mw *mw = to_mmw(ibmw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) err = mlx4_mw_alloc(dev->dev, to_mpd(ibmw->pd)->pdn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) to_mlx4_type(ibmw->type), &mw->mmw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) err = mlx4_mw_enable(dev->dev, &mw->mmw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) goto err_mw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ibmw->rkey = mw->mmw.key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) err_mw:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) mlx4_mw_free(dev->dev, &mw->mmw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) int mlx4_ib_dealloc_mw(struct ib_mw *ibmw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct mlx4_ib_mw *mw = to_mmw(ibmw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) mlx4_mw_free(to_mdev(ibmw->device)->dev, &mw->mmw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct ib_mr *mlx4_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) u32 max_num_sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct mlx4_ib_dev *dev = to_mdev(pd->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct mlx4_ib_mr *mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (mr_type != IB_MR_TYPE_MEM_REG ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) max_num_sg > MLX4_MAX_FAST_REG_PAGES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) mr = kzalloc(sizeof(*mr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (!mr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) err = mlx4_mr_alloc(dev->dev, to_mpd(pd)->pdn, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) max_num_sg, 0, &mr->mmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) err = mlx4_alloc_priv_pages(pd->device, mr, max_num_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) goto err_free_mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) mr->max_pages = max_num_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) err = mlx4_mr_enable(dev->dev, &mr->mmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) goto err_free_pl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) mr->ibmr.rkey = mr->ibmr.lkey = mr->mmr.key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) mr->umem = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return &mr->ibmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) err_free_pl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) mr->ibmr.device = pd->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) mlx4_free_priv_pages(mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) err_free_mr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) (void) mlx4_mr_free(dev->dev, &mr->mmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) err_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) kfree(mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static int mlx4_set_page(struct ib_mr *ibmr, u64 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct mlx4_ib_mr *mr = to_mmr(ibmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (unlikely(mr->npages == mr->max_pages))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) mr->pages[mr->npages++] = cpu_to_be64(addr | MLX4_MTT_FLAG_PRESENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) int mlx4_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) unsigned int *sg_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct mlx4_ib_mr *mr = to_mmr(ibmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) mr->npages = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ib_dma_sync_single_for_cpu(ibmr->device, mr->page_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) mr->page_map_size, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) rc = ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, mlx4_set_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ib_dma_sync_single_for_device(ibmr->device, mr->page_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) mr->page_map_size, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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