^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright(c) 2015, 2016 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This file is provided under a dual BSD/GPLv2 license. When using or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * redistributing this file, you may do so under either license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * GPL LICENSE SUMMARY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * it under the terms of version 2 of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This program is distributed in the hope that it will be useful, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * BSD LICENSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * - Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * notice, this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * - Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * notice, this list of conditions and the following disclaimer in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * the documentation and/or other materials provided with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * - Neither the name of Intel Corporation nor the names of its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * contributors may be used to endorse or promote products derived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* QSFP support common definitions, for hfi driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define QSFP_DEV 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define QSFP_PWR_LAG_MSEC 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define QSFP_MODPRS_LAG_MSEC 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* 128 byte pages, per SFF 8636 rev 2.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define QSFP_MAX_NUM_PAGES 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Below are masks for QSFP pins. Pins are the same for HFI0 and HFI1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * _N means asserted low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define QSFP_HFI0_I2CCLK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define QSFP_HFI0_I2CDAT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define QSFP_HFI0_RESET_N BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define QSFP_HFI0_INT_N BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define QSFP_HFI0_MODPRST_N BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* QSFP is paged at 256 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define QSFP_PAGESIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Reads/writes cannot cross 128 byte boundaries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define QSFP_RW_BOUNDARY 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* number of bytes in i2c offset for QSFP devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define __QSFP_OFFSET_SIZE 1 /* num address bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define QSFP_OFFSET_SIZE (__QSFP_OFFSET_SIZE << 8) /* shifted value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Defined fields that Intel requires of qualified cables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Byte 0 is Identifier, not checked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Byte 1 is reserved "status MSB" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define QSFP_MONITOR_VAL_START 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define QSFP_MONITOR_VAL_END 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define QSFP_MONITOR_RANGE (QSFP_MONITOR_VAL_END - QSFP_MONITOR_VAL_START + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define QSFP_TX_CTRL_BYTE_OFFS 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define QSFP_PWR_CTRL_BYTE_OFFS 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define QSFP_CDR_CTRL_BYTE_OFFS 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define QSFP_PAGE_SELECT_BYTE_OFFS 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Byte 128 is Identifier: must be 0x0c for QSFP, or 0x0d for QSFP+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define QSFP_MOD_ID_OFFS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * Byte 129 is "Extended Identifier".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * For bits [7:6]: 0:1.5W, 1:2.0W, 2:2.5W, 3:3.5W
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * For bits [1:0]: 0:Unused, 1:4W, 2:4.5W, 3:5W
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define QSFP_MOD_PWR_OFFS 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Byte 130 is Connector type. Not Intel req'd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Bytes 131..138 are Transceiver types, bit maps for various tech, none IB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Byte 139 is encoding. code 0x01 is 8b10b. Not Intel req'd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* byte 140 is nominal bit-rate, in units of 100Mbits/sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define QSFP_NOM_BIT_RATE_100_OFFS 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Byte 141 is Extended Rate Select. Not Intel req'd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Bytes 142..145 are lengths for various fiber types. Not Intel req'd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Byte 146 is length for Copper. Units of 1 meter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define QSFP_MOD_LEN_OFFS 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Byte 147 is Device technology. D0..3 not Intel req'd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * D4..7 select from 15 choices, translated by table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define QSFP_MOD_TECH_OFFS 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) extern const char *const hfi1_qsfp_devtech[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Active Equalization includes fiber, copper full EQ, and copper near Eq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define QSFP_IS_ACTIVE(tech) ((0xA2FF >> ((tech) >> 4)) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Active Equalization includes fiber, copper full EQ, and copper far Eq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define QSFP_IS_ACTIVE_FAR(tech) ((0x32FF >> ((tech) >> 4)) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Attenuation should be valid for copper other than full/near Eq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define QSFP_HAS_ATTEN(tech) ((0x4D00 >> ((tech) >> 4)) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Length is only valid if technology is "copper" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define QSFP_IS_CU(tech) ((0xED00 >> ((tech) >> 4)) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define QSFP_TECH_1490 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define QSFP_OUI(oui) (((unsigned)oui[0] << 16) | ((unsigned)oui[1] << 8) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) oui[2])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define QSFP_OUI_AMPHENOL 0x415048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define QSFP_OUI_FINISAR 0x009065
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define QSFP_OUI_GORE 0x002177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Bytes 148..163 are Vendor Name, Left-justified Blank-filled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define QSFP_VEND_OFFS 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define QSFP_VEND_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Byte 164 is IB Extended transceiver codes Bits D0..3 are SDR,DDR,QDR,EDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define QSFP_IBXCV_OFFS 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Bytes 165..167 are Vendor OUI number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define QSFP_VOUI_OFFS 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define QSFP_VOUI_LEN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Bytes 168..183 are Vendor Part Number, string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define QSFP_PN_OFFS 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define QSFP_PN_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Bytes 184,185 are Vendor Rev. Left Justified, Blank-filled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define QSFP_REV_OFFS 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define QSFP_REV_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * Bytes 186,187 are Wavelength, if Optical. Not Intel req'd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * If copper, they are attenuation in dB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * Byte 186 is at 2.5Gb/sec (SDR), Byte 187 at 5.0Gb/sec (DDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define QSFP_ATTEN_OFFS 186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define QSFP_ATTEN_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * Bytes 188,189 are Wavelength tolerance, if optical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * If copper, they are attenuation in dB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * Byte 188 is at 12.5 Gb/s, Byte 189 at 25 Gb/s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define QSFP_CU_ATTEN_7G_OFFS 188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define QSFP_CU_ATTEN_12G_OFFS 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Byte 190 is Max Case Temp. Not Intel req'd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Byte 191 is LSB of sum of bytes 128..190. Not Intel req'd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define QSFP_CC_OFFS 191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define QSFP_EQ_INFO_OFFS 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define QSFP_CDR_INFO_OFFS 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Bytes 196..211 are Serial Number, String */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define QSFP_SN_OFFS 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define QSFP_SN_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Bytes 212..219 are date-code YYMMDD (MM==1 for Jan) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define QSFP_DATE_OFFS 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define QSFP_DATE_LEN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Bytes 218,219 are optional lot-code, string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define QSFP_LOT_OFFS 218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define QSFP_LOT_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Bytes 220, 221 indicate monitoring options, Not Intel req'd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Byte 222 indicates nominal bitrate in units of 250Mbits/sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define QSFP_NOM_BIT_RATE_250_OFFS 222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Byte 223 is LSB of sum of bytes 192..222 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define QSFP_CC_EXT_OFFS 223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * Interrupt flag masks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define QSFP_DATA_NOT_READY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define QSFP_HIGH_TEMP_ALARM 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define QSFP_LOW_TEMP_ALARM 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define QSFP_HIGH_TEMP_WARNING 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define QSFP_LOW_TEMP_WARNING 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define QSFP_HIGH_VCC_ALARM 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define QSFP_LOW_VCC_ALARM 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define QSFP_HIGH_VCC_WARNING 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define QSFP_LOW_VCC_WARNING 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define QSFP_HIGH_POWER_ALARM 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define QSFP_LOW_POWER_ALARM 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define QSFP_HIGH_POWER_WARNING 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define QSFP_LOW_POWER_WARNING 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define QSFP_HIGH_BIAS_ALARM 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define QSFP_LOW_BIAS_ALARM 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define QSFP_HIGH_BIAS_WARNING 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define QSFP_LOW_BIAS_WARNING 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define QSFP_ATTEN_SDR(attenarray) (attenarray[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define QSFP_ATTEN_DDR(attenarray) (attenarray[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * struct qsfp_data encapsulates state of QSFP device for one port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * it will be part of port-specific data if a board supports QSFP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * Since multiple board-types use QSFP, and their pport_data structs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * differ (in the chip-specific section), we need a pointer to its head.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * Avoiding premature optimization, we will have one work_struct per port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * and let the qsfp_lock arbitrate access to common resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct qsfp_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Helps to find our way */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct hfi1_pportdata *ppd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct work_struct qsfp_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u8 cache[QSFP_MAX_NUM_PAGES * 128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* protect qsfp data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) spinlock_t qsfp_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u8 check_interrupt_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u8 reset_needed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u8 limiting_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u8 cache_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u8 cache_refresh_required;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int refresh_qsfp_cache(struct hfi1_pportdata *ppd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct qsfp_data *cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int get_qsfp_power_class(u8 power_byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int qsfp_mod_present(struct hfi1_pportdata *ppd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int get_cable_info(struct hfi1_devdata *dd, u32 port_num, u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 len, u8 *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int i2c_write(struct hfi1_pportdata *ppd, u32 target, int i2c_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int offset, void *bp, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int i2c_read(struct hfi1_pportdata *ppd, u32 target, int i2c_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int offset, void *bp, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int qsfp_write(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int qsfp_read(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int one_qsfp_write(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int one_qsfp_read(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct hfi1_asic_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int set_up_i2c(struct hfi1_devdata *dd, struct hfi1_asic_data *ad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) void clean_up_i2c(struct hfi1_devdata *dd, struct hfi1_asic_data *ad);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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