^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) #ifndef _QP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #define _QP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright(c) 2015 - 2018 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is provided under a dual BSD/GPLv2 license. When using or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * redistributing this file, you may do so under either license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * GPL LICENSE SUMMARY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * it under the terms of version 2 of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * This program is distributed in the hope that it will be useful, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * BSD LICENSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * - Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * notice, this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * - Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * notice, this list of conditions and the following disclaimer in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * the documentation and/or other materials provided with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * - Neither the name of Intel Corporation nor the names of its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * contributors may be used to endorse or promote products derived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/hash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <rdma/rdmavt_qp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include "verbs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include "sdma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include "verbs_txreq.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) extern unsigned int hfi1_qp_table_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) extern const struct rvt_operation_params hfi1_post_parms[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * Driver specific s_flags starting at bit 31 down to HFI1_S_MIN_BIT_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * HFI1_S_AHG_VALID - ahg header valid on chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * HFI1_S_AHG_CLEAR - have send engine clear ahg state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * HFI1_S_WAIT_PIO_DRAIN - qp waiting for PIOs to drain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * HFI1_S_WAIT_TID_SPACE - a QP is waiting for TID resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * HFI1_S_WAIT_TID_RESP - waiting for a TID RDMA WRITE response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * HFI1_S_WAIT_HALT - halt the first leg send engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * HFI1_S_MIN_BIT_MASK - the lowest bit that can be used by hfi1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define HFI1_S_AHG_VALID 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define HFI1_S_AHG_CLEAR 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define HFI1_S_WAIT_PIO_DRAIN 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define HFI1_S_WAIT_TID_SPACE 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define HFI1_S_WAIT_TID_RESP 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define HFI1_S_WAIT_HALT 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define HFI1_S_MIN_BIT_MASK 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * overload wait defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define HFI1_S_ANY_WAIT_IO (RVT_S_ANY_WAIT_IO | HFI1_S_WAIT_PIO_DRAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define HFI1_S_ANY_WAIT (HFI1_S_ANY_WAIT_IO | RVT_S_ANY_WAIT_SEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define HFI1_S_ANY_TID_WAIT_SEND (RVT_S_WAIT_SSN_CREDIT | RVT_S_WAIT_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * Send if not busy or waiting for I/O and either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * a RC response is pending or we can process send work requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static inline int hfi1_send_ok(struct rvt_qp *qp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct hfi1_qp_priv *priv = qp->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return !(qp->s_flags & (RVT_S_BUSY | HFI1_S_ANY_WAIT_IO)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) (verbs_txreq_queued(iowait_get_ib_work(&priv->s_iowait)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) (qp->s_flags & RVT_S_RESP_PENDING) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) !(qp->s_flags & RVT_S_ANY_WAIT_SEND));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * free_ahg - clear ahg from QP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static inline void clear_ahg(struct rvt_qp *qp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct hfi1_qp_priv *priv = qp->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) priv->s_ahg->ahgcount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) qp->s_flags &= ~(HFI1_S_AHG_VALID | HFI1_S_AHG_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (priv->s_sde && qp->s_ahgidx >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) sdma_ahg_free(priv->s_sde, qp->s_ahgidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) qp->s_ahgidx = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * hfi1_qp_wakeup - wake up on the indicated event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @qp: the QP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @flag: flag the qp on which the qp is stalled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) void hfi1_qp_wakeup(struct rvt_qp *qp, u32 flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct sdma_engine *qp_to_sdma_engine(struct rvt_qp *qp, u8 sc5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct send_context *qp_to_send_context(struct rvt_qp *qp, u8 sc5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) void qp_iter_print(struct seq_file *s, struct rvt_qp_iter *iter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) bool _hfi1_schedule_send(struct rvt_qp *qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) bool hfi1_schedule_send(struct rvt_qp *qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) void hfi1_migrate_qp(struct rvt_qp *qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * Functions provided by hfi1 driver for rdmavt to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) void *qp_priv_alloc(struct rvt_dev_info *rdi, struct rvt_qp *qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) void qp_priv_free(struct rvt_dev_info *rdi, struct rvt_qp *qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned free_all_qps(struct rvt_dev_info *rdi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) void notify_qp_reset(struct rvt_qp *qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int get_pmtu_from_attr(struct rvt_dev_info *rdi, struct rvt_qp *qp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct ib_qp_attr *attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) void flush_qp_waiters(struct rvt_qp *qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) void notify_error_qp(struct rvt_qp *qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) void stop_send_queue(struct rvt_qp *qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) void quiesce_qp(struct rvt_qp *qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 mtu_from_qp(struct rvt_dev_info *rdi, struct rvt_qp *qp, u32 pmtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int mtu_to_path_mtu(u32 mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) void hfi1_error_port_qps(struct hfi1_ibport *ibp, u8 sl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) void hfi1_qp_unbusy(struct rvt_qp *qp, struct iowait_work *wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #endif /* _QP_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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