^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright(c) 2015-2018 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This file is provided under a dual BSD/GPLv2 license. When using or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * redistributing this file, you may do so under either license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * GPL LICENSE SUMMARY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * it under the terms of version 2 of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This program is distributed in the hope that it will be useful, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * BSD LICENSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * - Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * notice, this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * - Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * notice, this list of conditions and the following disclaimer in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * the documentation and/or other materials provided with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * - Neither the name of Intel Corporation nor the names of its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * contributors may be used to endorse or promote products derived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include "hfi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include "qp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include "trace.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SC(name) SEND_CTXT_##name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Send Context functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static void sc_wait_for_packet_egress(struct send_context *sc, int pause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * Set the CM reset bit and wait for it to clear. Use the provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * sendctrl register. This routine has no locking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) void __cm_reset(struct hfi1_devdata *dd, u64 sendctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) write_csr(dd, SEND_CTRL, sendctrl | SEND_CTRL_CM_RESET_SMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) sendctrl = read_csr(dd, SEND_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if ((sendctrl & SEND_CTRL_CM_RESET_SMASK) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* global control of PIO send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) void pio_send_control(struct hfi1_devdata *dd, int op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u64 reg, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int write = 1; /* write sendctrl back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int flush = 0; /* re-read sendctrl to make sure it is flushed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) spin_lock_irqsave(&dd->sendctrl_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) reg = read_csr(dd, SEND_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) switch (op) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) case PSC_GLOBAL_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) reg |= SEND_CTRL_SEND_ENABLE_SMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) case PSC_DATA_VL_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) for (i = 0; i < ARRAY_SIZE(dd->vld); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (!dd->vld[i].mtu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) mask |= BIT_ULL(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Disallow sending on VLs not enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) mask = (mask & SEND_CTRL_UNSUPPORTED_VL_MASK) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) SEND_CTRL_UNSUPPORTED_VL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) reg = (reg & ~SEND_CTRL_UNSUPPORTED_VL_SMASK) | mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) case PSC_GLOBAL_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) reg &= ~SEND_CTRL_SEND_ENABLE_SMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) case PSC_GLOBAL_VLARB_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) reg |= SEND_CTRL_VL_ARBITER_ENABLE_SMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) case PSC_GLOBAL_VLARB_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) reg &= ~SEND_CTRL_VL_ARBITER_ENABLE_SMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) case PSC_CM_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) __cm_reset(dd, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) write = 0; /* CSR already written (and flushed) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) case PSC_DATA_VL_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) reg |= SEND_CTRL_UNSUPPORTED_VL_SMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) flush = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dd_dev_err(dd, "%s: invalid control %d\n", __func__, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) write_csr(dd, SEND_CTRL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (flush)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) (void)read_csr(dd, SEND_CTRL); /* flush write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* number of send context memory pools */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define NUM_SC_POOLS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Send Context Size (SCS) wildcards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SCS_POOL_0 -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SCS_POOL_1 -2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Send Context Count (SCC) wildcards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SCC_PER_VL -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SCC_PER_CPU -2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SCC_PER_KRCVQ -3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Send Context Size (SCS) constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SCS_ACK_CREDITS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SCS_VL15_CREDITS 102 /* 3 pkts of 2048B data + 128B header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PIO_THRESHOLD_CEILING 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PIO_WAIT_BATCH_SIZE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* default send context sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static struct sc_config_sizes sc_config_sizes[SC_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) [SC_KERNEL] = { .size = SCS_POOL_0, /* even divide, pool 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .count = SCC_PER_VL }, /* one per NUMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) [SC_ACK] = { .size = SCS_ACK_CREDITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .count = SCC_PER_KRCVQ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) [SC_USER] = { .size = SCS_POOL_0, /* even divide, pool 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .count = SCC_PER_CPU }, /* one per CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) [SC_VL15] = { .size = SCS_VL15_CREDITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .count = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* send context memory pool configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct mem_pool_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int centipercent; /* % of memory, in 100ths of 1% */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int absolute_blocks; /* absolute block count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* default memory pool configuration: 100% in pool 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static struct mem_pool_config sc_mem_pool_config[NUM_SC_POOLS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* centi%, abs blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { 10000, -1 }, /* pool 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { 0, -1 }, /* pool 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* memory pool information, used when calculating final sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct mem_pool_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int centipercent; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * 100th of 1% of memory to use, -1 if blocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * already set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int count; /* count of contexts in the pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int blocks; /* block size of the pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int size; /* context size, in blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * Convert a pool wildcard to a valid pool index. The wildcards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * start at -1 and increase negatively. Map them as:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * -1 => 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * -2 => 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * Return -1 on non-wildcard input, otherwise convert to a pool number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int wildcard_to_pool(int wc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (wc >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return -1; /* non-wildcard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return -wc - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const char *sc_type_names[SC_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "ack",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "vl15"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const char *sc_type_name(int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (index < 0 || index >= SC_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return "unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return sc_type_names[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * Read the send context memory pool configuration and send context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * size configuration. Replace any wildcards and come up with final
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * counts and sizes for the send context types.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int init_sc_pools_and_sizes(struct hfi1_devdata *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct mem_pool_info mem_pool_info[NUM_SC_POOLS] = { { 0 } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int total_blocks = (chip_pio_mem_size(dd) / PIO_BLOCK_SIZE) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int total_contexts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int fixed_blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int pool_blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int used_blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int cp_total; /* centipercent total */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int ab_total; /* absolute block total */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int extra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * When SDMA is enabled, kernel context pio packet size is capped by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * "piothreshold". Reduce pio buffer allocation for kernel context by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * setting it to a fixed size. The allocation allows 3-deep buffering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * of the largest pio packets plus up to 128 bytes header, sufficient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * to maintain verbs performance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * When SDMA is disabled, keep the default pooling allocation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (HFI1_CAP_IS_KSET(SDMA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u16 max_pkt_size = (piothreshold < PIO_THRESHOLD_CEILING) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) piothreshold : PIO_THRESHOLD_CEILING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) sc_config_sizes[SC_KERNEL].size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 3 * (max_pkt_size + 128) / PIO_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * Step 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * - copy the centipercents/absolute sizes from the pool config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * - sanity check these values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * - add up centipercents, then later check for full value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * - add up absolute blocks, then later check for over-commit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) cp_total = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ab_total = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) for (i = 0; i < NUM_SC_POOLS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int cp = sc_mem_pool_config[i].centipercent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int ab = sc_mem_pool_config[i].absolute_blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * A negative value is "unused" or "invalid". Both *can*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * be valid, but centipercent wins, so check that first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (cp >= 0) { /* centipercent valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) cp_total += cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) } else if (ab >= 0) { /* absolute blocks valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ab_total += ab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) } else { /* neither valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dd_dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) "Send context memory pool %d: both the block count and centipercent are invalid\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) mem_pool_info[i].centipercent = cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) mem_pool_info[i].blocks = ab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* do not use both % and absolute blocks for different pools */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (cp_total != 0 && ab_total != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dd_dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) "All send context memory pools must be described as either centipercent or blocks, no mixing between pools\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* if any percentages are present, they must add up to 100% x 100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (cp_total != 0 && cp_total != 10000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dd_dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) "Send context memory pool centipercent is %d, expecting 10000\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) cp_total);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* the absolute pool total cannot be more than the mem total */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (ab_total > total_blocks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) dd_dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) "Send context memory pool absolute block count %d is larger than the memory size %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ab_total, total_blocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * Step 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * - copy from the context size config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * - replace context type wildcard counts with real values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * - add up non-memory pool block sizes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * - add up memory pool user counts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) fixed_blocks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) for (i = 0; i < SC_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int count = sc_config_sizes[i].count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int size = sc_config_sizes[i].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * Sanity check count: Either a positive value or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * one of the expected wildcards is valid. The positive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * value is checked later when we compare against total
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * memory available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (i == SC_ACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) count = dd->n_krcv_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) } else if (i == SC_KERNEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) count = INIT_SC_PER_VL * num_vls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) } else if (count == SCC_PER_CPU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) count = dd->num_rcv_contexts - dd->n_krcv_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) } else if (count < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dd_dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) "%s send context invalid count wildcard %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) sc_type_name(i), count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (total_contexts + count > chip_send_contexts(dd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) count = chip_send_contexts(dd) - total_contexts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) total_contexts += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * Sanity check pool: The conversion will return a pool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * number or -1 if a fixed (non-negative) value. The fixed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * value is checked later when we compare against
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * total memory available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) pool = wildcard_to_pool(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (pool == -1) { /* non-wildcard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) fixed_blocks += size * count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) } else if (pool < NUM_SC_POOLS) { /* valid wildcard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) mem_pool_info[pool].count += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) } else { /* invalid wildcard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) dd_dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) "%s send context invalid pool wildcard %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) sc_type_name(i), size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dd->sc_sizes[i].count = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dd->sc_sizes[i].size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (fixed_blocks > total_blocks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) dd_dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) "Send context fixed block count, %u, larger than total block count %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) fixed_blocks, total_blocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* step 3: calculate the blocks in the pools, and pool context sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) pool_blocks = total_blocks - fixed_blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (ab_total > pool_blocks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dd_dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) "Send context fixed pool sizes, %u, larger than pool block count %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ab_total, pool_blocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* subtract off the fixed pool blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) pool_blocks -= ab_total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) for (i = 0; i < NUM_SC_POOLS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct mem_pool_info *pi = &mem_pool_info[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* % beats absolute blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (pi->centipercent >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) pi->blocks = (pool_blocks * pi->centipercent) / 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (pi->blocks == 0 && pi->count != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dd_dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) "Send context memory pool %d has %u contexts, but no blocks\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) i, pi->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (pi->count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* warn about wasted blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (pi->blocks != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) dd_dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) "Send context memory pool %d has %u blocks, but zero contexts\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) i, pi->blocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) pi->size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) pi->size = pi->blocks / pi->count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* step 4: fill in the context type sizes from the pool sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) used_blocks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) for (i = 0; i < SC_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (dd->sc_sizes[i].size < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned pool = wildcard_to_pool(dd->sc_sizes[i].size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) WARN_ON_ONCE(pool >= NUM_SC_POOLS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) dd->sc_sizes[i].size = mem_pool_info[pool].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* make sure we are not larger than what is allowed by the HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define PIO_MAX_BLOCKS 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (dd->sc_sizes[i].size > PIO_MAX_BLOCKS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dd->sc_sizes[i].size = PIO_MAX_BLOCKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* calculate our total usage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) used_blocks += dd->sc_sizes[i].size * dd->sc_sizes[i].count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) extra = total_blocks - used_blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (extra != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dd_dev_info(dd, "unused send context blocks: %d\n", extra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return total_contexts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int init_send_contexts(struct hfi1_devdata *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u16 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int ret, i, j, context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ret = init_credit_return(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dd->hw_to_sw = kmalloc_array(TXE_NUM_CONTEXTS, sizeof(u8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dd->send_contexts = kcalloc(dd->num_send_contexts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) sizeof(struct send_context_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (!dd->send_contexts || !dd->hw_to_sw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) kfree(dd->hw_to_sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) kfree(dd->send_contexts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) free_credit_return(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* hardware context map starts with invalid send context indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) for (i = 0; i < TXE_NUM_CONTEXTS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dd->hw_to_sw[i] = INVALID_SCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * All send contexts have their credit sizes. Allocate credits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * for each context one after another from the global space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) context = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) base = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) for (i = 0; i < SC_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct sc_config_sizes *scs = &dd->sc_sizes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) for (j = 0; j < scs->count; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct send_context_info *sci =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) &dd->send_contexts[context];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) sci->type = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) sci->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) sci->credits = scs->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) context++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) base += scs->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * Allocate a software index and hardware context of the given type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * Must be called with dd->sc_lock held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static int sc_hw_alloc(struct hfi1_devdata *dd, int type, u32 *sw_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u32 *hw_context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct send_context_info *sci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) u32 context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) for (index = 0, sci = &dd->send_contexts[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) index < dd->num_send_contexts; index++, sci++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (sci->type == type && sci->allocated == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) sci->allocated = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* use a 1:1 mapping, but make them non-equal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) context = chip_send_contexts(dd) - index - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dd->hw_to_sw[context] = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) *sw_index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) *hw_context = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return 0; /* success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dd_dev_err(dd, "Unable to locate a free type %d send context\n", type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * Free the send context given by its software index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * Must be called with dd->sc_lock held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static void sc_hw_free(struct hfi1_devdata *dd, u32 sw_index, u32 hw_context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct send_context_info *sci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) sci = &dd->send_contexts[sw_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (!sci->allocated) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) dd_dev_err(dd, "%s: sw_index %u not allocated? hw_context %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) __func__, sw_index, hw_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) sci->allocated = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) dd->hw_to_sw[hw_context] = INVALID_SCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* return the base context of a context in a group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static inline u32 group_context(u32 context, u32 group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return (context >> group) << group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* return the size of a group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static inline u32 group_size(u32 group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return 1 << group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * Obtain the credit return addresses, kernel virtual and bus, for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * given sc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * To understand this routine:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * o va and dma are arrays of struct credit_return. One for each physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * send context, per NUMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * o Each send context always looks in its relative location in a struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * credit_return for its credit return.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * o Each send context in a group must have its return address CSR programmed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * with the same value. Use the address of the first send context in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static void cr_group_addresses(struct send_context *sc, dma_addr_t *dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u32 gc = group_context(sc->hw_context, sc->group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) u32 index = sc->hw_context & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) sc->hw_free = &sc->dd->cr_base[sc->node].va[gc].cr[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) *dma = (unsigned long)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) &((struct credit_return *)sc->dd->cr_base[sc->node].dma)[gc];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * Work queue function triggered in error interrupt routine for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * kernel contexts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static void sc_halted(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct send_context *sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) sc = container_of(work, struct send_context, halt_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) sc_restart(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * Calculate PIO block threshold for this send context using the given MTU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * Trigger a return when one MTU plus optional header of credits remain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * Parameter mtu is in bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * Parameter hdrqentsize is in DWORDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * Return value is what to write into the CSR: trigger return when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * unreturned credits pass this count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) u32 sc_mtu_to_threshold(struct send_context *sc, u32 mtu, u32 hdrqentsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) u32 release_credits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) u32 threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* add in the header size, then divide by the PIO block size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) mtu += hdrqentsize << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) release_credits = DIV_ROUND_UP(mtu, PIO_BLOCK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* check against this context's credits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (sc->credits <= release_credits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) threshold = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) threshold = sc->credits - release_credits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * Calculate credit threshold in terms of percent of the allocated credits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * Trigger when unreturned credits equal or exceed the percentage of the whole.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * Return value is what to write into the CSR: trigger return when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * unreturned credits pass this count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) u32 sc_percent_to_threshold(struct send_context *sc, u32 percent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return (sc->credits * percent) / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * Set the credit return threshold.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) void sc_set_cr_threshold(struct send_context *sc, u32 new_threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) u32 old_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) int force_return = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) spin_lock_irqsave(&sc->credit_ctrl_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) old_threshold = (sc->credit_ctrl >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) SC(CREDIT_CTRL_THRESHOLD_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) & SC(CREDIT_CTRL_THRESHOLD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (new_threshold != old_threshold) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) sc->credit_ctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) (sc->credit_ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) & ~SC(CREDIT_CTRL_THRESHOLD_SMASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) | ((new_threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) & SC(CREDIT_CTRL_THRESHOLD_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) << SC(CREDIT_CTRL_THRESHOLD_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) write_kctxt_csr(sc->dd, sc->hw_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) SC(CREDIT_CTRL), sc->credit_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* force a credit return on change to avoid a possible stall */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) force_return = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) spin_unlock_irqrestore(&sc->credit_ctrl_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (force_return)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) sc_return_credits(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * set_pio_integrity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * Set the CHECK_ENABLE register for the send context 'sc'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) void set_pio_integrity(struct send_context *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct hfi1_devdata *dd = sc->dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) u32 hw_context = sc->hw_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) int type = sc->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) write_kctxt_csr(dd, hw_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) SC(CHECK_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) hfi1_pkt_default_send_ctxt_mask(dd, type));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static u32 get_buffers_allocated(struct send_context *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u32 ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) for_each_possible_cpu(cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ret += *per_cpu_ptr(sc->buffers_allocated, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static void reset_buffers_allocated(struct send_context *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) for_each_possible_cpu(cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) (*per_cpu_ptr(sc->buffers_allocated, cpu)) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * Allocate a NUMA relative send context structure of the given type along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * with a HW context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct send_context *sc_alloc(struct hfi1_devdata *dd, int type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) uint hdrqentsize, int numa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) struct send_context_info *sci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct send_context *sc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) u64 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) u32 thresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) u32 sw_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) u32 hw_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u8 opval, opmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* do not allocate while frozen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (dd->flags & HFI1_FROZEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) sc = kzalloc_node(sizeof(*sc), GFP_KERNEL, numa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (!sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) sc->buffers_allocated = alloc_percpu(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (!sc->buffers_allocated) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) kfree(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) dd_dev_err(dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) "Cannot allocate buffers_allocated per cpu counters\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) spin_lock_irqsave(&dd->sc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ret = sc_hw_alloc(dd, type, &sw_index, &hw_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) spin_unlock_irqrestore(&dd->sc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) free_percpu(sc->buffers_allocated);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) kfree(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) sci = &dd->send_contexts[sw_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) sci->sc = sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) sc->dd = dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) sc->node = numa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) sc->type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) spin_lock_init(&sc->alloc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) spin_lock_init(&sc->release_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) spin_lock_init(&sc->credit_ctrl_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) seqlock_init(&sc->waitlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) INIT_LIST_HEAD(&sc->piowait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) INIT_WORK(&sc->halt_work, sc_halted);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) init_waitqueue_head(&sc->halt_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* grouping is always single context for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) sc->group = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) sc->sw_index = sw_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) sc->hw_context = hw_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) cr_group_addresses(sc, &dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) sc->credits = sci->credits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) sc->size = sc->credits * PIO_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /* PIO Send Memory Address details */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define PIO_ADDR_CONTEXT_MASK 0xfful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define PIO_ADDR_CONTEXT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) sc->base_addr = dd->piobase + ((hw_context & PIO_ADDR_CONTEXT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) << PIO_ADDR_CONTEXT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* set base and credits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) reg = ((sci->credits & SC(CTRL_CTXT_DEPTH_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) << SC(CTRL_CTXT_DEPTH_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) | ((sci->base & SC(CTRL_CTXT_BASE_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) << SC(CTRL_CTXT_BASE_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) write_kctxt_csr(dd, hw_context, SC(CTRL), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) set_pio_integrity(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* unmask all errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) write_kctxt_csr(dd, hw_context, SC(ERR_MASK), (u64)-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* set the default partition key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) write_kctxt_csr(dd, hw_context, SC(CHECK_PARTITION_KEY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) (SC(CHECK_PARTITION_KEY_VALUE_MASK) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) DEFAULT_PKEY) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) SC(CHECK_PARTITION_KEY_VALUE_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* per context type checks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (type == SC_USER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) opval = USER_OPCODE_CHECK_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) opmask = USER_OPCODE_CHECK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) opval = OPCODE_CHECK_VAL_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) opmask = OPCODE_CHECK_MASK_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* set the send context check opcode mask and value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) write_kctxt_csr(dd, hw_context, SC(CHECK_OPCODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ((u64)opmask << SC(CHECK_OPCODE_MASK_SHIFT)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ((u64)opval << SC(CHECK_OPCODE_VALUE_SHIFT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* set up credit return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) reg = dma & SC(CREDIT_RETURN_ADDR_ADDRESS_SMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) write_kctxt_csr(dd, hw_context, SC(CREDIT_RETURN_ADDR), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * Calculate the initial credit return threshold.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * For Ack contexts, set a threshold for half the credits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * For User contexts use the given percentage. This has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * sanitized on driver start-up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * For Kernel contexts, use the default MTU plus a header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * or half the credits, whichever is smaller. This should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * work for both the 3-deep buffering allocation and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * pooling allocation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (type == SC_ACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) thresh = sc_percent_to_threshold(sc, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) } else if (type == SC_USER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) thresh = sc_percent_to_threshold(sc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) user_credit_return_threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) } else { /* kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) thresh = min(sc_percent_to_threshold(sc, 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) sc_mtu_to_threshold(sc, hfi1_max_mtu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) hdrqentsize));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) reg = thresh << SC(CREDIT_CTRL_THRESHOLD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* add in early return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (type == SC_USER && HFI1_CAP_IS_USET(EARLY_CREDIT_RETURN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) reg |= SC(CREDIT_CTRL_EARLY_RETURN_SMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) else if (HFI1_CAP_IS_KSET(EARLY_CREDIT_RETURN)) /* kernel, ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) reg |= SC(CREDIT_CTRL_EARLY_RETURN_SMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /* set up write-through credit_ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) sc->credit_ctrl = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) write_kctxt_csr(dd, hw_context, SC(CREDIT_CTRL), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /* User send contexts should not allow sending on VL15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (type == SC_USER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) reg = 1ULL << 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) write_kctxt_csr(dd, hw_context, SC(CHECK_VL), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) spin_unlock_irqrestore(&dd->sc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * Allocate shadow ring to track outstanding PIO buffers _after_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * unlocking. We don't know the size until the lock is held and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * we can't allocate while the lock is held. No one is using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * the context yet, so allocate it now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * User contexts do not get a shadow ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (type != SC_USER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) * Size the shadow ring 1 larger than the number of credits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * so head == tail can mean empty.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) sc->sr_size = sci->credits + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) sc->sr = kcalloc_node(sc->sr_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) sizeof(union pio_shadow_ring),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) GFP_KERNEL, numa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (!sc->sr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) sc_free(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) hfi1_cdbg(PIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) "Send context %u(%u) %s group %u credits %u credit_ctrl 0x%llx threshold %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) sw_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) hw_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) sc_type_name(type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) sc->group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) sc->credits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) sc->credit_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) thresh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /* free a per-NUMA send context structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) void sc_free(struct send_context *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct hfi1_devdata *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) u32 sw_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) u32 hw_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (!sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) sc->flags |= SCF_IN_FREE; /* ensure no restarts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) dd = sc->dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (!list_empty(&sc->piowait))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) dd_dev_err(dd, "piowait list not empty!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) sw_index = sc->sw_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) hw_context = sc->hw_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) sc_disable(sc); /* make sure the HW is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) flush_work(&sc->halt_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) spin_lock_irqsave(&dd->sc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) dd->send_contexts[sw_index].sc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* clear/disable all registers set in sc_alloc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) write_kctxt_csr(dd, hw_context, SC(CTRL), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) write_kctxt_csr(dd, hw_context, SC(CHECK_ENABLE), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) write_kctxt_csr(dd, hw_context, SC(ERR_MASK), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) write_kctxt_csr(dd, hw_context, SC(CHECK_PARTITION_KEY), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) write_kctxt_csr(dd, hw_context, SC(CHECK_OPCODE), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) write_kctxt_csr(dd, hw_context, SC(CREDIT_RETURN_ADDR), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) write_kctxt_csr(dd, hw_context, SC(CREDIT_CTRL), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* release the index and context for re-use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) sc_hw_free(dd, sw_index, hw_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) spin_unlock_irqrestore(&dd->sc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) kfree(sc->sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) free_percpu(sc->buffers_allocated);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) kfree(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /* disable the context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) void sc_disable(struct send_context *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) u64 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) struct pio_buf *pbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) LIST_HEAD(wake_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (!sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) /* do all steps, even if already disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) spin_lock_irq(&sc->alloc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) reg = read_kctxt_csr(sc->dd, sc->hw_context, SC(CTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) reg &= ~SC(CTRL_CTXT_ENABLE_SMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) sc->flags &= ~SCF_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) sc_wait_for_packet_egress(sc, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) write_kctxt_csr(sc->dd, sc->hw_context, SC(CTRL), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * Flush any waiters. Once the context is disabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * credit return interrupts are stopped (although there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * could be one in-process when the context is disabled).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * Wait one microsecond for any lingering interrupts, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) * proceed with the flush.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) spin_lock(&sc->release_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (sc->sr) { /* this context has a shadow ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) while (sc->sr_tail != sc->sr_head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) pbuf = &sc->sr[sc->sr_tail].pbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (pbuf->cb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) (*pbuf->cb)(pbuf->arg, PRC_SC_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) sc->sr_tail++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (sc->sr_tail >= sc->sr_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) sc->sr_tail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) spin_unlock(&sc->release_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) write_seqlock(&sc->waitlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (!list_empty(&sc->piowait))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) list_move(&sc->piowait, &wake_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) write_sequnlock(&sc->waitlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) while (!list_empty(&wake_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct iowait *wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct rvt_qp *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct hfi1_qp_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) wait = list_first_entry(&wake_list, struct iowait, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) qp = iowait_to_qp(wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) priv = qp->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) list_del_init(&priv->s_iowait.list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) priv->s_iowait.lock = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) hfi1_qp_wakeup(qp, RVT_S_WAIT_PIO | HFI1_S_WAIT_PIO_DRAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) spin_unlock_irq(&sc->alloc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /* return SendEgressCtxtStatus.PacketOccupancy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static u64 packet_occupancy(u64 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return (reg &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_PACKET_OCCUPANCY_SMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) >> SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_PACKET_OCCUPANCY_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /* is egress halted on the context? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static bool egress_halted(u64 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) return !!(reg & SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_HALT_STATUS_SMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* is the send context halted? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static bool is_sc_halted(struct hfi1_devdata *dd, u32 hw_context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) return !!(read_kctxt_csr(dd, hw_context, SC(STATUS)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) SC(STATUS_CTXT_HALTED_SMASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * sc_wait_for_packet_egress
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * @sc: valid send context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * @pause: wait for credit return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) * Wait for packet egress, optionally pause for credit return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * Egress halt and Context halt are not necessarily the same thing, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * check for both.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * NOTE: The context halt bit may not be set immediately. Because of this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * it is necessary to check the SW SFC_HALTED bit (set in the IRQ) and the HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * context bit to determine if the context is halted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static void sc_wait_for_packet_egress(struct send_context *sc, int pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct hfi1_devdata *dd = sc->dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) u64 reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) u64 reg_prev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) u32 loop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) reg_prev = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) reg = read_csr(dd, sc->hw_context * 8 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) SEND_EGRESS_CTXT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) /* done if any halt bits, SW or HW are set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (sc->flags & SCF_HALTED ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) is_sc_halted(dd, sc->hw_context) || egress_halted(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) reg = packet_occupancy(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (reg == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) /* counter is reset if occupancy count changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (reg != reg_prev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) loop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (loop > 50000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /* timed out - bounce the link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) dd_dev_err(dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) "%s: context %u(%u) timeout waiting for packets to egress, remaining count %u, bouncing link\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) __func__, sc->sw_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) sc->hw_context, (u32)reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) queue_work(dd->pport->link_wq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) &dd->pport->link_bounce_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) loop++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /* Add additional delay to ensure chip returns all credits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) pause_for_credit_return(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) void sc_wait(struct hfi1_devdata *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) for (i = 0; i < dd->num_send_contexts; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) struct send_context *sc = dd->send_contexts[i].sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (!sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) sc_wait_for_packet_egress(sc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) * Restart a context after it has been halted due to error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) * If the first step fails - wait for the halt to be asserted, return early.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) * Otherwise complain about timeouts but keep going.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) * It is expected that allocations (enabled flag bit) have been shut off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) * already (only applies to kernel contexts).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) int sc_restart(struct send_context *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) struct hfi1_devdata *dd = sc->dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) u64 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) u32 loop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) /* bounce off if not halted, or being free'd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (!(sc->flags & SCF_HALTED) || (sc->flags & SCF_IN_FREE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) dd_dev_info(dd, "restarting send context %u(%u)\n", sc->sw_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) sc->hw_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) * Step 1: Wait for the context to actually halt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) * The error interrupt is asynchronous to actually setting halt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) * on the context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) loop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) reg = read_kctxt_csr(dd, sc->hw_context, SC(STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (reg & SC(STATUS_CTXT_HALTED_SMASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if (loop > 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) dd_dev_err(dd, "%s: context %u(%u) not halting, skipping\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) __func__, sc->sw_index, sc->hw_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) return -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) loop++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * Step 2: Ensure no users are still trying to write to PIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) * For kernel contexts, we have already turned off buffer allocation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) * Now wait for the buffer count to go to zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) * For user contexts, the user handling code has cut off write access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) * to the context's PIO pages before calling this routine and will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * restore write access after this routine returns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (sc->type != SC_USER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) /* kernel context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) loop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) count = get_buffers_allocated(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) if (count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (loop > 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) dd_dev_err(dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) "%s: context %u(%u) timeout waiting for PIO buffers to zero, remaining %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) __func__, sc->sw_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) sc->hw_context, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) loop++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) * Step 3: Wait for all packets to egress.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) * This is done while disabling the send context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) * Step 4: Disable the context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) * This is a superset of the halt. After the disable, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * errors can be cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) sc_disable(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) * Step 5: Enable the context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) * This enable will clear the halted flag and per-send context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) * error flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) return sc_enable(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) * PIO freeze processing. To be called after the TXE block is fully frozen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) * Go through all frozen send contexts and disable them. The contexts are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) * already stopped by the freeze.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) void pio_freeze(struct hfi1_devdata *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) struct send_context *sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) for (i = 0; i < dd->num_send_contexts; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) sc = dd->send_contexts[i].sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) * Don't disable unallocated, unfrozen, or user send contexts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) * User send contexts will be disabled when the process
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) * calls into the driver to reset its context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (!sc || !(sc->flags & SCF_FROZEN) || sc->type == SC_USER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) /* only need to disable, the context is already stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) sc_disable(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) * Unfreeze PIO for kernel send contexts. The precondition for calling this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) * is that all PIO send contexts have been disabled and the SPC freeze has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) * been cleared. Now perform the last step and re-enable each kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) * User (PSM) processing will occur when PSM calls into the kernel to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) * acknowledge the freeze.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) void pio_kernel_unfreeze(struct hfi1_devdata *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) struct send_context *sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) for (i = 0; i < dd->num_send_contexts; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) sc = dd->send_contexts[i].sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (!sc || !(sc->flags & SCF_FROZEN) || sc->type == SC_USER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (sc->flags & SCF_LINK_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) sc_enable(sc); /* will clear the sc frozen flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) * pio_kernel_linkup() - Re-enable send contexts after linkup event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) * @dd: valid devive data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) * When the link goes down, the freeze path is taken. However, a link down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) * event is different from a freeze because if the send context is re-enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) * whowever is sending data will start sending data again, which will hang
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) * any QP that is sending data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) * The freeze path now looks at the type of event that occurs and takes this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) * path for link down event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) void pio_kernel_linkup(struct hfi1_devdata *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) struct send_context *sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) for (i = 0; i < dd->num_send_contexts; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) sc = dd->send_contexts[i].sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) if (!sc || !(sc->flags & SCF_LINK_DOWN) || sc->type == SC_USER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) sc_enable(sc); /* will clear the sc link down flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * Wait for the SendPioInitCtxt.PioInitInProgress bit to clear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) * -ETIMEDOUT - if we wait too long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) * -EIO - if there was an error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) static int pio_init_wait_progress(struct hfi1_devdata *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) u64 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) int max, count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /* max is the longest possible HW init time / delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) max = (dd->icode == ICODE_FPGA_EMULATION) ? 120 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) reg = read_csr(dd, SEND_PIO_INIT_CTXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (!(reg & SEND_PIO_INIT_CTXT_PIO_INIT_IN_PROGRESS_SMASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (count >= max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) return reg & SEND_PIO_INIT_CTXT_PIO_INIT_ERR_SMASK ? -EIO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) * Reset all of the send contexts to their power-on state. Used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) * only during manual init - no lock against sc_enable needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) void pio_reset_all(struct hfi1_devdata *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) /* make sure the init engine is not busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) ret = pio_init_wait_progress(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) /* ignore any timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if (ret == -EIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) /* clear the error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) write_csr(dd, SEND_PIO_ERR_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) SEND_PIO_ERR_CLEAR_PIO_INIT_SM_IN_ERR_SMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) /* reset init all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) write_csr(dd, SEND_PIO_INIT_CTXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) SEND_PIO_INIT_CTXT_PIO_ALL_CTXT_INIT_SMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) ret = pio_init_wait_progress(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) dd_dev_err(dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) "PIO send context init %s while initializing all PIO blocks\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) ret == -ETIMEDOUT ? "is stuck" : "had an error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /* enable the context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) int sc_enable(struct send_context *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) u64 sc_ctrl, reg, pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) struct hfi1_devdata *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (!sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) dd = sc->dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) * Obtain the allocator lock to guard against any allocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) * attempts (which should not happen prior to context being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) * enabled). On the release/disable side we don't need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) * worry about locking since the releaser will not do anything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) * if the context accounting values have not changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) spin_lock_irqsave(&sc->alloc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) sc_ctrl = read_kctxt_csr(dd, sc->hw_context, SC(CTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if ((sc_ctrl & SC(CTRL_CTXT_ENABLE_SMASK)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) goto unlock; /* already enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) /* IMPORTANT: only clear free and fill if transitioning 0 -> 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) *sc->hw_free = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) sc->free = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) sc->alloc_free = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) sc->fill = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) sc->fill_wrap = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) sc->sr_head = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) sc->sr_tail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) sc->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) /* the alloc lock insures no fast path allocation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) reset_buffers_allocated(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) * Clear all per-context errors. Some of these will be set when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) * we are re-enabling after a context halt. Now that the context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) * is disabled, the halt will not clear until after the PIO init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) * engine runs below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) reg = read_kctxt_csr(dd, sc->hw_context, SC(ERR_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) write_kctxt_csr(dd, sc->hw_context, SC(ERR_CLEAR), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) * The HW PIO initialization engine can handle only one init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) * request at a time. Serialize access to each device's engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) spin_lock(&dd->sc_init_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) * Since access to this code block is serialized and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) * each access waits for the initialization to complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) * before releasing the lock, the PIO initialization engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) * should not be in use, so we don't have to wait for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) * InProgress bit to go down.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) pio = ((sc->hw_context & SEND_PIO_INIT_CTXT_PIO_CTXT_NUM_MASK) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) SEND_PIO_INIT_CTXT_PIO_CTXT_NUM_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) SEND_PIO_INIT_CTXT_PIO_SINGLE_CTXT_INIT_SMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) write_csr(dd, SEND_PIO_INIT_CTXT, pio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) * Wait until the engine is done. Give the chip the required time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) * so, hopefully, we read the register just once.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) ret = pio_init_wait_progress(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) spin_unlock(&dd->sc_init_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) dd_dev_err(dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) "sctxt%u(%u): Context not enabled due to init failure %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) sc->sw_index, sc->hw_context, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) * All is well. Enable the context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) sc_ctrl |= SC(CTRL_CTXT_ENABLE_SMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) write_kctxt_csr(dd, sc->hw_context, SC(CTRL), sc_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) * Read SendCtxtCtrl to force the write out and prevent a timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) * hazard where a PIO write may reach the context before the enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) read_kctxt_csr(dd, sc->hw_context, SC(CTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) sc->flags |= SCF_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) spin_unlock_irqrestore(&sc->alloc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) /* force a credit return on the context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) void sc_return_credits(struct send_context *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) if (!sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) /* a 0->1 transition schedules a credit return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) write_kctxt_csr(sc->dd, sc->hw_context, SC(CREDIT_FORCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) SC(CREDIT_FORCE_FORCE_RETURN_SMASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) * Ensure that the write is flushed and the credit return is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) * scheduled. We care more about the 0 -> 1 transition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) read_kctxt_csr(sc->dd, sc->hw_context, SC(CREDIT_FORCE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) /* set back to 0 for next time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) write_kctxt_csr(sc->dd, sc->hw_context, SC(CREDIT_FORCE), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) /* allow all in-flight packets to drain on the context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) void sc_flush(struct send_context *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) if (!sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) sc_wait_for_packet_egress(sc, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) /* drop all packets on the context, no waiting until they are sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) void sc_drop(struct send_context *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) if (!sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) dd_dev_info(sc->dd, "%s: context %u(%u) - not implemented\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) __func__, sc->sw_index, sc->hw_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) * Start the software reaction to a context halt or SPC freeze:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) * - mark the context as halted or frozen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) * - stop buffer allocations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) * Called from the error interrupt. Other work is deferred until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) * out of the interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) void sc_stop(struct send_context *sc, int flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) /* stop buffer allocations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) spin_lock_irqsave(&sc->alloc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) /* mark the context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) sc->flags |= flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) sc->flags &= ~SCF_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) spin_unlock_irqrestore(&sc->alloc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) wake_up(&sc->halt_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) #define BLOCK_DWORDS (PIO_BLOCK_SIZE / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) #define dwords_to_blocks(x) DIV_ROUND_UP(x, BLOCK_DWORDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) * The send context buffer "allocator".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) * @sc: the PIO send context we are allocating from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) * @len: length of whole packet - including PBC - in dwords
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) * @cb: optional callback to call when the buffer is finished sending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) * @arg: argument for cb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) * Return a pointer to a PIO buffer, NULL if not enough room, -ECOMM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) * when link is down.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) struct pio_buf *sc_buffer_alloc(struct send_context *sc, u32 dw_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) pio_release_cb cb, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) struct pio_buf *pbuf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) unsigned long avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) unsigned long blocks = dwords_to_blocks(dw_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) u32 fill_wrap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) int trycount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) u32 head, next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) spin_lock_irqsave(&sc->alloc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if (!(sc->flags & SCF_ENABLED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) spin_unlock_irqrestore(&sc->alloc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) return ERR_PTR(-ECOMM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) avail = (unsigned long)sc->credits - (sc->fill - sc->alloc_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) if (blocks > avail) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) /* not enough room */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) if (unlikely(trycount)) { /* already tried to get more room */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) spin_unlock_irqrestore(&sc->alloc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) /* copy from receiver cache line and recalculate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) sc->alloc_free = READ_ONCE(sc->free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) avail =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) (unsigned long)sc->credits -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) (sc->fill - sc->alloc_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (blocks > avail) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) /* still no room, actively update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) sc_release_update(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) sc->alloc_free = READ_ONCE(sc->free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) trycount++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) goto retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) /* there is enough room */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) this_cpu_inc(*sc->buffers_allocated);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) /* read this once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) head = sc->sr_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) /* "allocate" the buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) sc->fill += blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) fill_wrap = sc->fill_wrap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) sc->fill_wrap += blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) if (sc->fill_wrap >= sc->credits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) sc->fill_wrap = sc->fill_wrap - sc->credits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) * Fill the parts that the releaser looks at before moving the head.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) * The only necessary piece is the sent_at field. The credits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) * we have just allocated cannot have been returned yet, so the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) * cb and arg will not be looked at for a "while". Put them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) * on this side of the memory barrier anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) pbuf = &sc->sr[head].pbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) pbuf->sent_at = sc->fill;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) pbuf->cb = cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) pbuf->arg = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) pbuf->sc = sc; /* could be filled in at sc->sr init time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) /* make sure this is in memory before updating the head */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) /* calculate next head index, do not store */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) next = head + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) if (next >= sc->sr_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) next = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) * update the head - must be last! - the releaser can look at fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) * in pbuf once we move the head
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) smp_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) sc->sr_head = next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) spin_unlock_irqrestore(&sc->alloc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) /* finish filling in the buffer outside the lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) pbuf->start = sc->base_addr + fill_wrap * PIO_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) pbuf->end = sc->base_addr + sc->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) pbuf->qw_written = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) pbuf->carry_bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) pbuf->carry.val64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) return pbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) * There are at least two entities that can turn on credit return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) * interrupts and they can overlap. Avoid problems by implementing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) * a count scheme that is enforced by a lock. The lock is needed because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) * the count and CSR write must be paired.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) * Start credit return interrupts. This is managed by a count. If already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) * on, just increment the count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) void sc_add_credit_return_intr(struct send_context *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) /* lock must surround both the count change and the CSR update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) spin_lock_irqsave(&sc->credit_ctrl_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if (sc->credit_intr_count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) sc->credit_ctrl |= SC(CREDIT_CTRL_CREDIT_INTR_SMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) write_kctxt_csr(sc->dd, sc->hw_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) SC(CREDIT_CTRL), sc->credit_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) sc->credit_intr_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) spin_unlock_irqrestore(&sc->credit_ctrl_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) * Stop credit return interrupts. This is managed by a count. Decrement the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) * count, if the last user, then turn the credit interrupts off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) void sc_del_credit_return_intr(struct send_context *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) WARN_ON(sc->credit_intr_count == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) /* lock must surround both the count change and the CSR update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) spin_lock_irqsave(&sc->credit_ctrl_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) sc->credit_intr_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) if (sc->credit_intr_count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) sc->credit_ctrl &= ~SC(CREDIT_CTRL_CREDIT_INTR_SMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) write_kctxt_csr(sc->dd, sc->hw_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) SC(CREDIT_CTRL), sc->credit_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) spin_unlock_irqrestore(&sc->credit_ctrl_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) * The caller must be careful when calling this. All needint calls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) * must be paired with !needint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) void hfi1_sc_wantpiobuf_intr(struct send_context *sc, u32 needint)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) if (needint)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) sc_add_credit_return_intr(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) sc_del_credit_return_intr(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) trace_hfi1_wantpiointr(sc, needint, sc->credit_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) if (needint)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) sc_return_credits(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) * sc_piobufavail - callback when a PIO buffer is available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) * @sc: the send context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) * This is called from the interrupt handler when a PIO buffer is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) * available after hfi1_verbs_send() returned an error that no buffers were
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) * available. Disable the interrupt if there are no more QPs waiting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) static void sc_piobufavail(struct send_context *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) struct hfi1_devdata *dd = sc->dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) struct list_head *list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) struct rvt_qp *qps[PIO_WAIT_BATCH_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) struct rvt_qp *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) struct hfi1_qp_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) uint i, n = 0, top_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) if (dd->send_contexts[sc->sw_index].type != SC_KERNEL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) dd->send_contexts[sc->sw_index].type != SC_VL15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) list = &sc->piowait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) * Note: checking that the piowait list is empty and clearing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) * the buffer available interrupt needs to be atomic or we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) * could end up with QPs on the wait list with the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) * disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) write_seqlock_irqsave(&sc->waitlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) while (!list_empty(list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) struct iowait *wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) if (n == ARRAY_SIZE(qps))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) wait = list_first_entry(list, struct iowait, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) iowait_get_priority(wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) qp = iowait_to_qp(wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) priv = qp->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) list_del_init(&priv->s_iowait.list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) priv->s_iowait.lock = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) if (n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) priv = qps[top_idx]->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) top_idx = iowait_priority_update_top(wait,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) &priv->s_iowait,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) n, top_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) /* refcount held until actual wake up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) qps[n++] = qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) * If there had been waiters and there are more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) * insure that we redo the force to avoid a potential hang.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) if (n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) hfi1_sc_wantpiobuf_intr(sc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) if (!list_empty(list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) hfi1_sc_wantpiobuf_intr(sc, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) write_sequnlock_irqrestore(&sc->waitlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) /* Wake up the top-priority one first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) if (n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) hfi1_qp_wakeup(qps[top_idx],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) RVT_S_WAIT_PIO | HFI1_S_WAIT_PIO_DRAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) for (i = 0; i < n; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) if (i != top_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) hfi1_qp_wakeup(qps[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) RVT_S_WAIT_PIO | HFI1_S_WAIT_PIO_DRAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) /* translate a send credit update to a bit code of reasons */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) static inline int fill_code(u64 hw_free)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) int code = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) if (hw_free & CR_STATUS_SMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) code |= PRC_STATUS_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) if (hw_free & CR_CREDIT_RETURN_DUE_TO_PBC_SMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) code |= PRC_PBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) if (hw_free & CR_CREDIT_RETURN_DUE_TO_THRESHOLD_SMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) code |= PRC_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) if (hw_free & CR_CREDIT_RETURN_DUE_TO_ERR_SMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) code |= PRC_FILL_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) if (hw_free & CR_CREDIT_RETURN_DUE_TO_FORCE_SMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) code |= PRC_SC_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) return code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) /* use the jiffies compare to get the wrap right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) #define sent_before(a, b) time_before(a, b) /* a < b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) * The send context buffer "releaser".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) void sc_release_update(struct send_context *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) struct pio_buf *pbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) u64 hw_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) u32 head, tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) unsigned long old_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) unsigned long free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) unsigned long extra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) int code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) if (!sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) spin_lock_irqsave(&sc->release_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) /* update free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) hw_free = le64_to_cpu(*sc->hw_free); /* volatile read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) old_free = sc->free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) extra = (((hw_free & CR_COUNTER_SMASK) >> CR_COUNTER_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) - (old_free & CR_COUNTER_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) & CR_COUNTER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) free = old_free + extra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) trace_hfi1_piofree(sc, extra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) /* call sent buffer callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) code = -1; /* code not yet set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) head = READ_ONCE(sc->sr_head); /* snapshot the head */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) tail = sc->sr_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) while (head != tail) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) pbuf = &sc->sr[tail].pbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) if (sent_before(free, pbuf->sent_at)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) /* not sent yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) if (pbuf->cb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) if (code < 0) /* fill in code on first user */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) code = fill_code(hw_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) (*pbuf->cb)(pbuf->arg, code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) tail++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) if (tail >= sc->sr_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) tail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) sc->sr_tail = tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) /* make sure tail is updated before free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) smp_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) sc->free = free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) spin_unlock_irqrestore(&sc->release_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) sc_piobufavail(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) * Send context group releaser. Argument is the send context that caused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) * the interrupt. Called from the send context interrupt handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) * Call release on all contexts in the group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) * This routine takes the sc_lock without an irqsave because it is only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) * called from an interrupt handler. Adjust if that changes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) void sc_group_release_update(struct hfi1_devdata *dd, u32 hw_context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) struct send_context *sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) u32 sw_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) u32 gc, gc_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) spin_lock(&dd->sc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) sw_index = dd->hw_to_sw[hw_context];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) if (unlikely(sw_index >= dd->num_send_contexts)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) dd_dev_err(dd, "%s: invalid hw (%u) to sw (%u) mapping\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) __func__, hw_context, sw_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) sc = dd->send_contexts[sw_index].sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) if (unlikely(!sc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) gc = group_context(hw_context, sc->group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) gc_end = gc + group_size(sc->group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) for (; gc < gc_end; gc++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) sw_index = dd->hw_to_sw[gc];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) if (unlikely(sw_index >= dd->num_send_contexts)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) dd_dev_err(dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) "%s: invalid hw (%u) to sw (%u) mapping\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) __func__, hw_context, sw_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) sc_release_update(dd->send_contexts[sw_index].sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) spin_unlock(&dd->sc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) * pio_select_send_context_vl() - select send context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) * @dd: devdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) * @selector: a spreading factor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) * @vl: this vl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) * This function returns a send context based on the selector and a vl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) * The mapping fields are protected by RCU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) struct send_context *pio_select_send_context_vl(struct hfi1_devdata *dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) u32 selector, u8 vl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) struct pio_vl_map *m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) struct pio_map_elem *e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) struct send_context *rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) * NOTE This should only happen if SC->VL changed after the initial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) * checks on the QP/AH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) * Default will return VL0's send context below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) if (unlikely(vl >= num_vls)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) rval = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) rcu_read_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) m = rcu_dereference(dd->pio_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) if (unlikely(!m)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) rcu_read_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) return dd->vld[0].sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) e = m->map[vl & m->mask];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) rval = e->ksc[selector & e->mask];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) rcu_read_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) rval = !rval ? dd->vld[0].sc : rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) * pio_select_send_context_sc() - select send context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) * @dd: devdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) * @selector: a spreading factor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) * @sc5: the 5 bit sc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) * This function returns an send context based on the selector and an sc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) struct send_context *pio_select_send_context_sc(struct hfi1_devdata *dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) u32 selector, u8 sc5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) u8 vl = sc_to_vlt(dd, sc5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) return pio_select_send_context_vl(dd, selector, vl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) * Free the indicated map struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) static void pio_map_free(struct pio_vl_map *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) for (i = 0; m && i < m->actual_vls; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) kfree(m->map[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) kfree(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) * Handle RCU callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) static void pio_map_rcu_callback(struct rcu_head *list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) struct pio_vl_map *m = container_of(list, struct pio_vl_map, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) pio_map_free(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) * Set credit return threshold for the kernel send context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) static void set_threshold(struct hfi1_devdata *dd, int scontext, int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) u32 thres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) thres = min(sc_percent_to_threshold(dd->kernel_send_context[scontext],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) sc_mtu_to_threshold(dd->kernel_send_context[scontext],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) dd->vld[i].mtu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) dd->rcd[0]->rcvhdrqentsize));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) sc_set_cr_threshold(dd->kernel_send_context[scontext], thres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) * pio_map_init - called when #vls change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) * @dd: hfi1_devdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) * @port: port number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) * @num_vls: number of vls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) * @vl_scontexts: per vl send context mapping (optional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) * This routine changes the mapping based on the number of vls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) * vl_scontexts is used to specify a non-uniform vl/send context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) * loading. NULL implies auto computing the loading and giving each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) * VL an uniform distribution of send contexts per VL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) * The auto algorithm computers the sc_per_vl and the number of extra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) * send contexts. Any extra send contexts are added from the last VL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) * on down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) * rcu locking is used here to control access to the mapping fields.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) * If either the num_vls or num_send_contexts are non-power of 2, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) * array sizes in the struct pio_vl_map and the struct pio_map_elem are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) * rounded up to the next highest power of 2 and the first entry is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) * reused in a round robin fashion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) * If an error occurs the map change is not done and the mapping is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) * chaged.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) int pio_map_init(struct hfi1_devdata *dd, u8 port, u8 num_vls, u8 *vl_scontexts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) int extra, sc_per_vl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) int scontext = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) int num_kernel_send_contexts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) u8 lvl_scontexts[OPA_MAX_VLS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) struct pio_vl_map *oldmap, *newmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) if (!vl_scontexts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) for (i = 0; i < dd->num_send_contexts; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) if (dd->send_contexts[i].type == SC_KERNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) num_kernel_send_contexts++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) /* truncate divide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) sc_per_vl = num_kernel_send_contexts / num_vls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) /* extras */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) extra = num_kernel_send_contexts % num_vls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) vl_scontexts = lvl_scontexts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) /* add extras from last vl down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) for (i = num_vls - 1; i >= 0; i--, extra--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) vl_scontexts[i] = sc_per_vl + (extra > 0 ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) /* build new map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) newmap = kzalloc(sizeof(*newmap) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) roundup_pow_of_two(num_vls) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) sizeof(struct pio_map_elem *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) if (!newmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) goto bail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) newmap->actual_vls = num_vls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) newmap->vls = roundup_pow_of_two(num_vls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) newmap->mask = (1 << ilog2(newmap->vls)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) for (i = 0; i < newmap->vls; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) /* save for wrap around */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) int first_scontext = scontext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) if (i < newmap->actual_vls) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) int sz = roundup_pow_of_two(vl_scontexts[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) /* only allocate once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) newmap->map[i] = kzalloc(sizeof(*newmap->map[i]) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) sz * sizeof(struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) send_context *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) if (!newmap->map[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) goto bail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) newmap->map[i]->mask = (1 << ilog2(sz)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) * assign send contexts and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) * adjust credit return threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) for (j = 0; j < sz; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) if (dd->kernel_send_context[scontext]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) newmap->map[i]->ksc[j] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) dd->kernel_send_context[scontext];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) set_threshold(dd, scontext, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) if (++scontext >= first_scontext +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) vl_scontexts[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) /* wrap back to first send context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) scontext = first_scontext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) /* just re-use entry without allocating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) newmap->map[i] = newmap->map[i % num_vls];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) scontext = first_scontext + vl_scontexts[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) /* newmap in hand, save old map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) spin_lock_irq(&dd->pio_map_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) oldmap = rcu_dereference_protected(dd->pio_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) lockdep_is_held(&dd->pio_map_lock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) /* publish newmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) rcu_assign_pointer(dd->pio_map, newmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) spin_unlock_irq(&dd->pio_map_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) /* success, free any old map after grace period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) if (oldmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) call_rcu(&oldmap->list, pio_map_rcu_callback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) bail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) /* free any partial allocation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) pio_map_free(newmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) void free_pio_map(struct hfi1_devdata *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) /* Free PIO map if allocated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) if (rcu_access_pointer(dd->pio_map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) spin_lock_irq(&dd->pio_map_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) pio_map_free(rcu_access_pointer(dd->pio_map));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) RCU_INIT_POINTER(dd->pio_map, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) spin_unlock_irq(&dd->pio_map_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) synchronize_rcu();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) kfree(dd->kernel_send_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) dd->kernel_send_context = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) int init_pervl_scs(struct hfi1_devdata *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) u64 mask, all_vl_mask = (u64)0x80ff; /* VLs 0-7, 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) u64 data_vls_mask = (u64)0x00ff; /* VLs 0-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) u32 ctxt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) struct hfi1_pportdata *ppd = dd->pport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) dd->vld[15].sc = sc_alloc(dd, SC_VL15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) dd->rcd[0]->rcvhdrqentsize, dd->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) if (!dd->vld[15].sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) hfi1_init_ctxt(dd->vld[15].sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) dd->vld[15].mtu = enum_to_mtu(OPA_MTU_2048);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) dd->kernel_send_context = kcalloc_node(dd->num_send_contexts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) sizeof(struct send_context *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) GFP_KERNEL, dd->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) if (!dd->kernel_send_context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) goto freesc15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) dd->kernel_send_context[0] = dd->vld[15].sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) for (i = 0; i < num_vls; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) * Since this function does not deal with a specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) * receive context but we need the RcvHdrQ entry size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) * use the size from rcd[0]. It is guaranteed to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) * valid at this point and will remain the same for all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) * receive contexts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) dd->vld[i].sc = sc_alloc(dd, SC_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) dd->rcd[0]->rcvhdrqentsize, dd->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) if (!dd->vld[i].sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) goto nomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) dd->kernel_send_context[i + 1] = dd->vld[i].sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) hfi1_init_ctxt(dd->vld[i].sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) /* non VL15 start with the max MTU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) dd->vld[i].mtu = hfi1_max_mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) for (i = num_vls; i < INIT_SC_PER_VL * num_vls; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) dd->kernel_send_context[i + 1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) sc_alloc(dd, SC_KERNEL, dd->rcd[0]->rcvhdrqentsize, dd->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) if (!dd->kernel_send_context[i + 1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) goto nomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) hfi1_init_ctxt(dd->kernel_send_context[i + 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) sc_enable(dd->vld[15].sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) ctxt = dd->vld[15].sc->hw_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) mask = all_vl_mask & ~(1LL << 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) write_kctxt_csr(dd, ctxt, SC(CHECK_VL), mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) dd_dev_info(dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) "Using send context %u(%u) for VL15\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) dd->vld[15].sc->sw_index, ctxt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) for (i = 0; i < num_vls; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) sc_enable(dd->vld[i].sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) ctxt = dd->vld[i].sc->hw_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) mask = all_vl_mask & ~(data_vls_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) write_kctxt_csr(dd, ctxt, SC(CHECK_VL), mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) for (i = num_vls; i < INIT_SC_PER_VL * num_vls; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) sc_enable(dd->kernel_send_context[i + 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) ctxt = dd->kernel_send_context[i + 1]->hw_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) mask = all_vl_mask & ~(data_vls_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) write_kctxt_csr(dd, ctxt, SC(CHECK_VL), mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) if (pio_map_init(dd, ppd->port - 1, num_vls, NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) goto nomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) nomem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) for (i = 0; i < num_vls; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) sc_free(dd->vld[i].sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) dd->vld[i].sc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) for (i = num_vls; i < INIT_SC_PER_VL * num_vls; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) sc_free(dd->kernel_send_context[i + 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) kfree(dd->kernel_send_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) dd->kernel_send_context = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) freesc15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) sc_free(dd->vld[15].sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) int init_credit_return(struct hfi1_devdata *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) dd->cr_base = kcalloc(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) node_affinity.num_possible_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) sizeof(struct credit_return_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) if (!dd->cr_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) for_each_node_with_cpus(i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) int bytes = TXE_NUM_CONTEXTS * sizeof(struct credit_return);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) set_dev_node(&dd->pcidev->dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) dd->cr_base[i].va = dma_alloc_coherent(&dd->pcidev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) &dd->cr_base[i].dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) if (!dd->cr_base[i].va) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) set_dev_node(&dd->pcidev->dev, dd->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) dd_dev_err(dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) "Unable to allocate credit return DMA range for NUMA %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) set_dev_node(&dd->pcidev->dev, dd->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) void free_credit_return(struct hfi1_devdata *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) if (!dd->cr_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) for (i = 0; i < node_affinity.num_possible_nodes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) if (dd->cr_base[i].va) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) dma_free_coherent(&dd->pcidev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) TXE_NUM_CONTEXTS *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) sizeof(struct credit_return),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) dd->cr_base[i].va,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) dd->cr_base[i].dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) kfree(dd->cr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) dd->cr_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) void seqfile_dump_sci(struct seq_file *s, u32 i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) struct send_context_info *sci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) struct send_context *sc = sci->sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) u64 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) seq_printf(s, "SCI %u: type %u base %u credits %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) i, sci->type, sci->base, sci->credits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) seq_printf(s, " flags 0x%x sw_inx %u hw_ctxt %u grp %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) sc->flags, sc->sw_index, sc->hw_context, sc->group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) seq_printf(s, " sr_size %u credits %u sr_head %u sr_tail %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) sc->sr_size, sc->credits, sc->sr_head, sc->sr_tail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) seq_printf(s, " fill %lu free %lu fill_wrap %u alloc_free %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) sc->fill, sc->free, sc->fill_wrap, sc->alloc_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) seq_printf(s, " credit_intr_count %u credit_ctrl 0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) sc->credit_intr_count, sc->credit_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) reg = read_kctxt_csr(sc->dd, sc->hw_context, SC(CREDIT_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) seq_printf(s, " *hw_free %llu CurrentFree %llu LastReturned %llu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) (le64_to_cpu(*sc->hw_free) & CR_COUNTER_SMASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) CR_COUNTER_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) (reg >> SC(CREDIT_STATUS_CURRENT_FREE_COUNTER_SHIFT)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) SC(CREDIT_STATUS_CURRENT_FREE_COUNTER_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) reg & SC(CREDIT_STATUS_LAST_RETURNED_COUNTER_SMASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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