^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright(c) 2018 - 2020 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This file is provided under a dual BSD/GPLv2 license. When using or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * redistributing this file, you may do so under either license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * GPL LICENSE SUMMARY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * it under the terms of version 2 of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * This program is distributed in the hope that it will be useful, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * BSD LICENSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * - Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * notice, this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * - Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * notice, this list of conditions and the following disclaimer in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * the documentation and/or other materials provided with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * - Neither the name of Intel Corporation nor the names of its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * contributors may be used to endorse or promote products derived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include "hfi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include "affinity.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include "sdma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include "netdev.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * msix_initialize() - Calculate, request and configure MSIx IRQs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @dd: valid hfi1 devdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int msix_initialize(struct hfi1_devdata *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct hfi1_msix_entry *entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * MSIx interrupt count:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * one for the general, "slow path" interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * one per used SDMA engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * one per kernel receive context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * one for each VNIC context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * ...any new IRQs should be added here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) total = 1 + dd->num_sdma + dd->n_krcv_queues + dd->num_netdev_contexts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (total >= CCE_NUM_MSIX_VECTORS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ret = pci_alloc_irq_vectors(dd->pcidev, total, total, PCI_IRQ_MSIX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) dd_dev_err(dd, "pci_alloc_irq_vectors() failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) entries = kcalloc(total, sizeof(*dd->msix_info.msix_entries),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (!entries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) pci_free_irq_vectors(dd->pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) dd->msix_info.msix_entries = entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) spin_lock_init(&dd->msix_info.msix_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) bitmap_zero(dd->msix_info.in_use_msix, total);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) dd->msix_info.max_requested = total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) dd_dev_info(dd, "%u MSI-X interrupts allocated\n", total);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * msix_request_irq() - Allocate a free MSIx IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @dd: valid devdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * @arg: context information for the IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * @handler: IRQ handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @thread: IRQ thread handler (could be NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @idx: zero base idx if multiple devices are needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @type: affinty IRQ type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * Allocated an MSIx vector if available, and then create the appropriate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * meta data needed to keep track of the pci IRQ request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * < 0 Error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * >= 0 MSIx vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int msix_request_irq(struct hfi1_devdata *dd, void *arg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) irq_handler_t handler, irq_handler_t thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) enum irq_type type, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned long nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct hfi1_msix_entry *me;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Allocate an MSIx vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) spin_lock(&dd->msix_info.msix_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) nr = find_first_zero_bit(dd->msix_info.in_use_msix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) dd->msix_info.max_requested);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (nr < dd->msix_info.max_requested)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) __set_bit(nr, dd->msix_info.in_use_msix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) spin_unlock(&dd->msix_info.msix_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (nr == dd->msix_info.max_requested)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (type < IRQ_SDMA || type >= IRQ_OTHER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) irq = pci_irq_vector(dd->pcidev, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ret = pci_request_irq(dd->pcidev, nr, handler, thread, arg, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dd_dev_err(dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) "%s: request for IRQ %d failed, MSIx %lx, err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) name, irq, nr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) spin_lock(&dd->msix_info.msix_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) __clear_bit(nr, dd->msix_info.in_use_msix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) spin_unlock(&dd->msix_info.msix_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * assign arg after pci_request_irq call, so it will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * cleaned up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) me = &dd->msix_info.msix_entries[nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) me->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) me->arg = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) me->type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* This is a request, so a failure is not fatal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ret = hfi1_get_irq_affinity(dd, me);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) dd_dev_err(dd, "%s: unable to pin IRQ %d\n", name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int msix_request_rcd_irq_common(struct hfi1_ctxtdata *rcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) irq_handler_t handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) irq_handler_t thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int nr = msix_request_irq(rcd->dd, rcd, handler, thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) rcd->is_vnic ? IRQ_NETDEVCTXT : IRQ_RCVCTXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (nr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * Set the interrupt register and mask for this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * context's interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) rcd->ireg = (IS_RCVAVAIL_START + rcd->ctxt) / 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) rcd->imask = ((u64)1) << ((IS_RCVAVAIL_START + rcd->ctxt) % 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) rcd->msix_intr = nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) remap_intr(rcd->dd, IS_RCVAVAIL_START + rcd->ctxt, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * msix_request_rcd_irq() - Helper function for RCVAVAIL IRQs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * @rcd: valid rcd context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int msix_request_rcd_irq(struct hfi1_ctxtdata *rcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) char name[MAX_NAME_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) snprintf(name, sizeof(name), DRIVER_NAME "_%d kctxt%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) rcd->dd->unit, rcd->ctxt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return msix_request_rcd_irq_common(rcd, receive_context_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) receive_context_thread, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * msix_request_rcd_irq() - Helper function for RCVAVAIL IRQs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * for netdev context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * @rcd: valid netdev contexti
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int msix_netdev_request_rcd_irq(struct hfi1_ctxtdata *rcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) char name[MAX_NAME_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) snprintf(name, sizeof(name), DRIVER_NAME "_%d nd kctxt%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) rcd->dd->unit, rcd->ctxt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return msix_request_rcd_irq_common(rcd, receive_context_interrupt_napi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) NULL, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * msix_request_smda_ira() - Helper for getting SDMA IRQ resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @sde: valid sdma engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int msix_request_sdma_irq(struct sdma_engine *sde)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) char name[MAX_NAME_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) snprintf(name, sizeof(name), DRIVER_NAME "_%d sdma%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) sde->dd->unit, sde->this_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) nr = msix_request_irq(sde->dd, sde, sdma_interrupt, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) IRQ_SDMA, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (nr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) sde->msix_intr = nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) remap_sdma_interrupts(sde->dd, sde->this_idx, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * msix_request_general_irq(void) - Helper for getting general IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * @dd: valid device data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int msix_request_general_irq(struct hfi1_devdata *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) char name[MAX_NAME_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) snprintf(name, sizeof(name), DRIVER_NAME "_%d", dd->unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) nr = msix_request_irq(dd, dd, general_interrupt, NULL, IRQ_GENERAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (nr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* general interrupt must be MSIx vector 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) msix_free_irq(dd, (u8)nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) dd_dev_err(dd, "Invalid index %d for GENERAL IRQ\n", nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * enable_sdma_src() - Helper to enable SDMA IRQ srcs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * @dd: valid devdata structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * @i: index of SDMA engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static void enable_sdma_srcs(struct hfi1_devdata *dd, int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) set_intr_bits(dd, IS_SDMA_START + i, IS_SDMA_START + i, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) set_intr_bits(dd, IS_SDMA_PROGRESS_START + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) IS_SDMA_PROGRESS_START + i, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) set_intr_bits(dd, IS_SDMA_IDLE_START + i, IS_SDMA_IDLE_START + i, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) set_intr_bits(dd, IS_SDMAENG_ERR_START + i, IS_SDMAENG_ERR_START + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * msix_request_irqs() - Allocate all MSIx IRQs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * @dd: valid devdata structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * Helper function to request the used MSIx IRQs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int msix_request_irqs(struct hfi1_devdata *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int ret = msix_request_general_irq(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) for (i = 0; i < dd->num_sdma; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct sdma_engine *sde = &dd->per_sdma[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ret = msix_request_sdma_irq(sde);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) enable_sdma_srcs(sde->dd, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) for (i = 0; i < dd->n_krcv_queues; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct hfi1_ctxtdata *rcd = hfi1_rcd_get_by_index_safe(dd, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (rcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ret = msix_request_rcd_irq(rcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) hfi1_rcd_put(rcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * msix_free_irq() - Free the specified MSIx resources and IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * @dd: valid devdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * @msix_intr: MSIx vector to free.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) void msix_free_irq(struct hfi1_devdata *dd, u8 msix_intr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct hfi1_msix_entry *me;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (msix_intr >= dd->msix_info.max_requested)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) me = &dd->msix_info.msix_entries[msix_intr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (!me->arg) /* => no irq, no affinity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) hfi1_put_irq_affinity(dd, me);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) pci_free_irq(dd->pcidev, msix_intr, me->arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) me->arg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) spin_lock(&dd->msix_info.msix_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) __clear_bit(msix_intr, dd->msix_info.in_use_msix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) spin_unlock(&dd->msix_info.msix_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * hfi1_clean_up_msix_interrupts() - Free all MSIx IRQ resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * @dd: valid device data data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * Free the MSIx and associated PCI resources, if they have been allocated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) void msix_clean_up_interrupts(struct hfi1_devdata *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct hfi1_msix_entry *me = dd->msix_info.msix_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* remove irqs - must happen before disabling/turning off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) for (i = 0; i < dd->msix_info.max_requested; i++, me++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) msix_free_irq(dd, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* clean structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) kfree(dd->msix_info.msix_entries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dd->msix_info.msix_entries = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) dd->msix_info.max_requested = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) pci_free_irq_vectors(dd->pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * msix_netdev_syncrhonize_irq() - netdev IRQ synchronize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * @dd: valid devdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) void msix_netdev_synchronize_irq(struct hfi1_devdata *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int ctxt_count = hfi1_netdev_ctxt_count(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) for (i = 0; i < ctxt_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct hfi1_ctxtdata *rcd = hfi1_netdev_get_ctxt(dd, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct hfi1_msix_entry *me;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) me = &dd->msix_info.msix_entries[rcd->msix_intr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) synchronize_irq(me->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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