Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Copyright(c) 2015 - 2017 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * This file is provided under a dual BSD/GPLv2 license.  When using or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * redistributing this file, you may do so under either license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * GPL LICENSE SUMMARY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * it under the terms of version 2 of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * This program is distributed in the hope that it will be useful, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * WITHOUT ANY WARRANTY; without even the implied warranty of
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * BSD LICENSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * modification, are permitted provided that the following conditions
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *  - Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *    notice, this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *  - Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *    notice, this list of conditions and the following disclaimer in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *    the documentation and/or other materials provided with the
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *  - Neither the name of Intel Corporation nor the names of its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  *    contributors may be used to endorse or promote products derived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  *    from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #ifndef _HFI1_MAD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define _HFI1_MAD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #include <rdma/ib_pma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #include <rdma/opa_smi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #include <rdma/opa_port_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #include "opa_compat.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * OPA Traps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define OPA_TRAP_GID_NOW_IN_SERVICE             cpu_to_be16(64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define OPA_TRAP_GID_OUT_OF_SERVICE             cpu_to_be16(65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define OPA_TRAP_ADD_MULTICAST_GROUP            cpu_to_be16(66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define OPA_TRAL_DEL_MULTICAST_GROUP            cpu_to_be16(67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define OPA_TRAP_UNPATH                         cpu_to_be16(68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define OPA_TRAP_REPATH                         cpu_to_be16(69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define OPA_TRAP_PORT_CHANGE_STATE              cpu_to_be16(128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define OPA_TRAP_LINK_INTEGRITY                 cpu_to_be16(129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define OPA_TRAP_EXCESSIVE_BUFFER_OVERRUN       cpu_to_be16(130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define OPA_TRAP_FLOW_WATCHDOG                  cpu_to_be16(131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define OPA_TRAP_CHANGE_CAPABILITY              cpu_to_be16(144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define OPA_TRAP_CHANGE_SYSGUID                 cpu_to_be16(145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define OPA_TRAP_BAD_M_KEY                      cpu_to_be16(256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define OPA_TRAP_BAD_P_KEY                      cpu_to_be16(257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define OPA_TRAP_BAD_Q_KEY                      cpu_to_be16(258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define OPA_TRAP_SWITCH_BAD_PKEY                cpu_to_be16(259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define OPA_SMA_TRAP_DATA_LINK_WIDTH            cpu_to_be16(2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  * Generic trap/notice other local changes flags (trap 144).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define	OPA_NOTICE_TRAP_LWDE_CHG        0x08 /* Link Width Downgrade Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 					      * changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 					      */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define OPA_NOTICE_TRAP_LSE_CHG         0x04 /* Link Speed Enable changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define OPA_NOTICE_TRAP_LWE_CHG         0x02 /* Link Width Enable changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define OPA_NOTICE_TRAP_NODE_DESC_CHG   0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) struct opa_mad_notice_attr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	u8 generic_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	u8 prod_type_msb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	__be16 prod_type_lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	__be16 trap_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	__be16 toggle_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	__be32 issuer_lid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	__be32 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	union ib_gid issuer_gid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			u8	details[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		} raw_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			union ib_gid	gid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		} __packed ntc_64_65_66_67;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			__be32	lid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		} __packed ntc_128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			__be32	lid;		/* where violation happened */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			u8	port_num;	/* where violation happened */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		} __packed ntc_129_130_131;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			__be32	lid;		/* LID where change occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			__be32	new_cap_mask;	/* new capability mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			__be16	reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			__be16	cap_mask3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			__be16	change_flags;	/* low 4 bits only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		} __packed ntc_144;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			__be64	new_sys_guid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			__be32	lid;		/* lid where sys guid changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		} __packed ntc_145;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			__be32	lid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			__be32	dr_slid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			u8	method;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			u8	dr_trunc_hop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			__be16	attr_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			__be32	attr_mod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			__be64	mkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			u8	dr_rtn_path[30];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		} __packed ntc_256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			__be32		lid1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			__be32		lid2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			__be32		key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			u8		sl;	/* SL: high 5 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			u8		reserved3[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			union ib_gid	gid1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			union ib_gid	gid2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			__be32		qp1;	/* high 8 bits reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			__be32		qp2;	/* high 8 bits reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		} __packed ntc_257_258;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			__be16		flags;	/* low 8 bits reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			__be16		pkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			__be32		lid1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			__be32		lid2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			u8		sl;	/* SL: high 5 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			u8		reserved4[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			union ib_gid	gid1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			union ib_gid	gid2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			__be32		qp1;	/* high 8 bits reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			__be32		qp2;	/* high 8 bits reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		} __packed ntc_259;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			__be32	lid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		} __packed ntc_2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	u8	class_data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IB_VLARB_LOWPRI_0_31    1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define IB_VLARB_LOWPRI_32_63   2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define IB_VLARB_HIGHPRI_0_31   3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define IB_VLARB_HIGHPRI_32_63  4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define OPA_MAX_PREEMPT_CAP         32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define OPA_VLARB_LOW_ELEMENTS       0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define OPA_VLARB_HIGH_ELEMENTS      1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define OPA_VLARB_PREEMPT_ELEMENTS   2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define OPA_VLARB_PREEMPT_MATRIX     3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define IB_PMA_PORT_COUNTERS_CONG       cpu_to_be16(0xFF00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define LINK_SPEED_25G		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define LINK_SPEED_12_5G	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define LINK_WIDTH_DEFAULT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define DECIMAL_FACTORING	1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)  * The default link width is multiplied by 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  * to get accurate value after division.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define FACTOR_LINK_WIDTH	(LINK_WIDTH_DEFAULT * DECIMAL_FACTORING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct ib_pma_portcounters_cong {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	u8 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	__be16 port_check_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	__be16 symbol_error_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	u8 link_error_recovery_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	u8 link_downed_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	__be16 port_rcv_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	__be16 port_rcv_remphys_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	__be16 port_rcv_switch_relay_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	__be16 port_xmit_discards;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	u8 port_xmit_constraint_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	u8 port_rcv_constraint_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	u8 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	u8 link_overrun_errors; /* LocalLink: 7:4, BufferOverrun: 3:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	__be16 reserved3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	__be16 vl15_dropped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	__be64 port_xmit_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	__be64 port_rcv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	__be64 port_xmit_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	__be64 port_rcv_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	__be64 port_xmit_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	__be64 port_adr_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define IB_SMP_UNSUP_VERSION    cpu_to_be16(0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define IB_SMP_UNSUP_METHOD     cpu_to_be16(0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define IB_SMP_UNSUP_METH_ATTR  cpu_to_be16(0x000C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define IB_SMP_INVALID_FIELD    cpu_to_be16(0x001C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define OPA_MAX_PREEMPT_CAP         32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define OPA_VLARB_LOW_ELEMENTS       0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define OPA_VLARB_HIGH_ELEMENTS      1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define OPA_VLARB_PREEMPT_ELEMENTS   2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define OPA_VLARB_PREEMPT_MATRIX     3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define HFI1_XMIT_RATE_UNSUPPORTED               0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define HFI1_XMIT_RATE_PICO                      0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* number of 4nsec cycles equaling 2secs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define HFI1_CONG_TIMER_PSINTERVAL               0x1DCD64EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define IB_CC_SVCTYPE_RC 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define IB_CC_SVCTYPE_UC 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define IB_CC_SVCTYPE_RD 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define IB_CC_SVCTYPE_UD 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)  * There should be an equivalent IB #define for the following, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  * I cannot find it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define OPA_CC_LOG_TYPE_HFI	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct opa_hfi1_cong_log_event_internal {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	u32 lqpn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	u32 rqpn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	u8 sl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	u8 svc_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	u32 rlid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	u64 timestamp; /* wider than 32 bits to detect 32 bit rollover */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct opa_hfi1_cong_log_event {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	u8 local_qp_cn_entry[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	u8 remote_qp_number_cn_entry[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	u8 sl_svc_type_cn_entry; /* 5 bits SL, 3 bits svc type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	__be32 remote_lid_cn_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	__be32 timestamp_cn_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define OPA_CONG_LOG_ELEMS	96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct opa_hfi1_cong_log {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	u8 log_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	u8 congestion_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	__be16 threshold_event_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	__be32 current_time_stamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	u8 threshold_cong_event_map[OPA_MAX_SLS / 8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	struct opa_hfi1_cong_log_event events[OPA_CONG_LOG_ELEMS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define IB_CC_TABLE_CAP_DEFAULT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Port control flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define IB_CC_CCS_PC_SL_BASED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct opa_congestion_setting_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	u8 ccti_increase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	__be16 ccti_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	u8 trigger_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	u8 ccti_min; /* min CCTI for cc table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct opa_congestion_setting_entry_shadow {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	u8 ccti_increase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	u16 ccti_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	u8 trigger_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	u8 ccti_min; /* min CCTI for cc table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct opa_congestion_setting_attr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	__be32 control_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	__be16 port_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	struct opa_congestion_setting_entry entries[OPA_MAX_SLS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct opa_congestion_setting_attr_shadow {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	u32 control_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	u16 port_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	struct opa_congestion_setting_entry_shadow entries[OPA_MAX_SLS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define IB_CC_TABLE_ENTRY_INCREASE_DEFAULT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define IB_CC_TABLE_ENTRY_TIMER_DEFAULT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* 64 Congestion Control table entries in a single MAD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define IB_CCT_ENTRIES 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define IB_CCT_MIN_ENTRIES (IB_CCT_ENTRIES * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct ib_cc_table_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	__be16 entry; /* shift:2, multiplier:14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct ib_cc_table_entry_shadow {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	u16 entry; /* shift:2, multiplier:14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct ib_cc_table_attr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	__be16 ccti_limit; /* max CCTI for cc table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	struct ib_cc_table_entry ccti_entries[IB_CCT_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct ib_cc_table_attr_shadow {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	u16 ccti_limit; /* max CCTI for cc table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	struct ib_cc_table_entry_shadow ccti_entries[IB_CCT_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define CC_TABLE_SHADOW_MAX \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	(IB_CC_TABLE_CAP_DEFAULT * IB_CCT_ENTRIES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct cc_table_shadow {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	u16 ccti_limit; /* max CCTI for cc table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	struct ib_cc_table_entry_shadow entries[CC_TABLE_SHADOW_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)  * struct cc_state combines the (active) per-port congestion control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)  * table, and the (active) per-SL congestion settings. cc_state data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)  * may need to be read in code paths that we want to be fast, so it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)  * is an RCU protected structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct cc_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	struct rcu_head rcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	struct cc_table_shadow cct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	struct opa_congestion_setting_attr_shadow cong_setting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)  * OPA BufferControl MAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* attribute modifier macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define OPA_AM_NPORT_SHIFT	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define OPA_AM_NPORT_MASK	0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define OPA_AM_NPORT_SMASK	(OPA_AM_NPORT_MASK << OPA_AM_NPORT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define OPA_AM_NPORT(am)	(((am) >> OPA_AM_NPORT_SHIFT) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 					OPA_AM_NPORT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define OPA_AM_NBLK_SHIFT	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define OPA_AM_NBLK_MASK	0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define OPA_AM_NBLK_SMASK	(OPA_AM_NBLK_MASK << OPA_AM_NBLK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define OPA_AM_NBLK(am)		(((am) >> OPA_AM_NBLK_SHIFT) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 					OPA_AM_NBLK_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define OPA_AM_START_BLK_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define OPA_AM_START_BLK_MASK	0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define OPA_AM_START_BLK_SMASK	(OPA_AM_START_BLK_MASK << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 					OPA_AM_START_BLK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define OPA_AM_START_BLK(am)	(((am) >> OPA_AM_START_BLK_SHIFT) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 					OPA_AM_START_BLK_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define OPA_AM_PORTNUM_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define OPA_AM_PORTNUM_MASK	0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define OPA_AM_PORTNUM_SMASK	(OPA_AM_PORTNUM_MASK << OPA_AM_PORTNUM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define OPA_AM_PORTNUM(am)	(((am) >> OPA_AM_PORTNUM_SHIFT) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 					OPA_AM_PORTNUM_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define OPA_AM_ASYNC_SHIFT	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define OPA_AM_ASYNC_MASK	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define OPA_AM_ASYNC_SMASK	(OPA_AM_ASYNC_MASK << OPA_AM_ASYNC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define OPA_AM_ASYNC(am)	(((am) >> OPA_AM_ASYNC_SHIFT) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 					OPA_AM_ASYNC_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define OPA_AM_START_SM_CFG_SHIFT	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define OPA_AM_START_SM_CFG_MASK	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define OPA_AM_START_SM_CFG_SMASK	(OPA_AM_START_SM_CFG_MASK << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 						OPA_AM_START_SM_CFG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define OPA_AM_START_SM_CFG(am)		(((am) >> OPA_AM_START_SM_CFG_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 						& OPA_AM_START_SM_CFG_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define OPA_AM_CI_ADDR_SHIFT	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define OPA_AM_CI_ADDR_MASK	0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define OPA_AM_CI_ADDR_SMASK	(OPA_AM_CI_ADDR_MASK << OPA_CI_ADDR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define OPA_AM_CI_ADDR(am)	(((am) >> OPA_AM_CI_ADDR_SHIFT) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 					OPA_AM_CI_ADDR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define OPA_AM_CI_LEN_SHIFT	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define OPA_AM_CI_LEN_MASK	0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define OPA_AM_CI_LEN_SMASK	(OPA_AM_CI_LEN_MASK << OPA_CI_LEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define OPA_AM_CI_LEN(am)	(((am) >> OPA_AM_CI_LEN_SHIFT) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 					OPA_AM_CI_LEN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* error info macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define OPA_EI_STATUS_SMASK	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define OPA_EI_CODE_SMASK	0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct vl_limit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	__be16 dedicated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	__be16 shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct buffer_control {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	__be16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	__be16 overall_shared_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	struct vl_limit vl[OPA_MAX_VLS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct sc2vlnt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	u8 vlnt[32]; /* 5 bit VL, 3 bits reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)  * The PortSamplesControl.CounterMasks field is an array of 3 bit fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)  * which specify the N'th counter's capabilities. See ch. 16.1.3.2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)  * We support 5 counters which only count the mandatory quantities.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define COUNTER_MASK(q, n) (q << ((9 - n) * 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define COUNTER_MASK0_9 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	cpu_to_be32(COUNTER_MASK(1, 0) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		    COUNTER_MASK(1, 1) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		    COUNTER_MASK(1, 2) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		    COUNTER_MASK(1, 3) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		    COUNTER_MASK(1, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) void hfi1_event_pkey_change(struct hfi1_devdata *dd, u8 port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) void hfi1_handle_trap_timer(struct timer_list *t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u16 tx_link_width(u16 link_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u64 get_xmit_wait_counters(struct hfi1_pportdata *ppd, u16 link_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 			   u16 link_speed, int vl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)  * get_link_speed - determine whether 12.5G or 25G speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)  * @link_speed: the speed of active link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)  * @return: Return 2 if link speed identified as 12.5G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)  * or return 1 if link speed is 25G.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)  * The function indirectly calculate required link speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)  * value for convert_xmit_counter function. If the link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)  * speed is 25G, the function return as 1 as it is required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)  * by xmit counter conversion formula :-( 25G / link_speed).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)  * This conversion will provide value 1 if current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)  * link speed is 25G or 2 if 12.5G.This is done to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)  * 12.5 float number conversion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static inline u16 get_link_speed(u16 link_speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	return (link_speed == 1) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		 LINK_SPEED_12_5G : LINK_SPEED_25G;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)  * convert_xmit_counter - calculate flit times for given xmit counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)  * value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)  * @xmit_wait_val: current xmit counter value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)  * @link_width: width of active link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)  * @link_speed: speed of active link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)  * @return: return xmit counter value in flit times.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static inline u64 convert_xmit_counter(u64 xmit_wait_val, u16 link_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 				       u16 link_speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	return (xmit_wait_val * 2 * (FACTOR_LINK_WIDTH / link_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 		 * link_speed) / DECIMAL_FACTORING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #endif				/* _HFI1_MAD_H */