Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Copyright(c) 2015 - 2020 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * This file is provided under a dual BSD/GPLv2 license.  When using or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * redistributing this file, you may do so under either license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * GPL LICENSE SUMMARY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * it under the terms of version 2 of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * This program is distributed in the hope that it will be useful, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * WITHOUT ANY WARRANTY; without even the implied warranty of
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * BSD LICENSE
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * Redistribution and use in source and binary forms, with or without
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *  - Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *    notice, this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *  - Redistributions in binary form must reproduce the above copyright
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *    the documentation and/or other materials provided with the
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *  - Neither the name of Intel Corporation nor the names of its
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  *    from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #ifndef _COMMON_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define _COMMON_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #include <rdma/hfi/hfi1_user.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * This file contains defines, structures, etc. that are used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * to communicate between kernel and user code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /* version of protocol header (known to chip also). In the long run,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * we should be able to generate and accept a range of version numbers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * for now we only accept one, and it's compiled in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define IPS_PROTO_VERSION 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * These are compile time constants that you may want to enable or disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  * if you are trying to debug problems with code or performance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  * HFI1_VERBOSE_TRACING define as 1 if you want additional tracing in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  * fast path code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  * HFI1_TRACE_REGWRITES define as 1 if you want register writes to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  * traced in fast path code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  * _HFI1_TRACING define as 0 if you want to remove all tracing in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  * compilation unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /* driver/hw feature set bitmask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define HFI1_CAP_USER_SHIFT      24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define HFI1_CAP_MASK            ((1UL << HFI1_CAP_USER_SHIFT) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) /* locked flag - if set, only HFI1_CAP_WRITABLE_MASK bits can be set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define HFI1_CAP_LOCKED_SHIFT    63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define HFI1_CAP_LOCKED_MASK     0x1ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define HFI1_CAP_LOCKED_SMASK    (HFI1_CAP_LOCKED_MASK << HFI1_CAP_LOCKED_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) /* extra bits used between kernel and user processes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define HFI1_CAP_MISC_SHIFT      (HFI1_CAP_USER_SHIFT * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define HFI1_CAP_MISC_MASK       ((1ULL << (HFI1_CAP_LOCKED_SHIFT - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 					   HFI1_CAP_MISC_SHIFT)) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define HFI1_CAP_KSET(cap) ({ hfi1_cap_mask |= HFI1_CAP_##cap; hfi1_cap_mask; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define HFI1_CAP_KCLEAR(cap)						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	({								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		hfi1_cap_mask &= ~HFI1_CAP_##cap;			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		hfi1_cap_mask;						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define HFI1_CAP_USET(cap)						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	({								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		hfi1_cap_mask |= (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		hfi1_cap_mask;						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define HFI1_CAP_UCLEAR(cap)						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	({								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		hfi1_cap_mask &= ~(HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		hfi1_cap_mask;						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define HFI1_CAP_SET(cap)						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	({								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		hfi1_cap_mask |= (HFI1_CAP_##cap | (HFI1_CAP_##cap <<	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 						  HFI1_CAP_USER_SHIFT)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		hfi1_cap_mask;						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HFI1_CAP_CLEAR(cap)						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	({								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		hfi1_cap_mask &= ~(HFI1_CAP_##cap |			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 				  (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		hfi1_cap_mask;						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define HFI1_CAP_LOCK()							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	({ hfi1_cap_mask |= HFI1_CAP_LOCKED_SMASK; hfi1_cap_mask; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define HFI1_CAP_LOCKED() (!!(hfi1_cap_mask & HFI1_CAP_LOCKED_SMASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  * The set of capability bits that can be changed after initial load
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  * This set is the same for kernel and user contexts. However, for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  * user contexts, the set can be further filtered by using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  * HFI1_CAP_RESERVED_MASK bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define HFI1_CAP_WRITABLE_MASK   (HFI1_CAP_SDMA_AHG |			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 				  HFI1_CAP_HDRSUPP |			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 				  HFI1_CAP_MULTI_PKT_EGR |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 				  HFI1_CAP_NODROP_RHQ_FULL |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 				  HFI1_CAP_NODROP_EGR_FULL |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 				  HFI1_CAP_ALLOW_PERM_JKEY |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 				  HFI1_CAP_STATIC_RATE_CTRL |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 				  HFI1_CAP_PRINT_UNIMPL |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 				  HFI1_CAP_TID_UNMAP |			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 				  HFI1_CAP_OPFN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  * A set of capability bits that are "global" and are not allowed to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)  * set in the user bitmask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define HFI1_CAP_RESERVED_MASK   ((HFI1_CAP_SDMA |			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 				   HFI1_CAP_USE_SDMA_HEAD |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 				   HFI1_CAP_EXTENDED_PSN |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 				   HFI1_CAP_PRINT_UNIMPL |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 				   HFI1_CAP_NO_INTEGRITY |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 				   HFI1_CAP_PKEY_CHECK |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 				   HFI1_CAP_TID_RDMA |			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 				   HFI1_CAP_OPFN |			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 				   HFI1_CAP_AIP) <<			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 				  HFI1_CAP_USER_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  * Set of capabilities that need to be enabled for kernel context in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)  * order to be allowed for user contexts, as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define HFI1_CAP_MUST_HAVE_KERN (HFI1_CAP_STATIC_RATE_CTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Default enabled capabilities (both kernel and user) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define HFI1_CAP_MASK_DEFAULT    (HFI1_CAP_HDRSUPP |			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 				 HFI1_CAP_NODROP_RHQ_FULL |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 				 HFI1_CAP_NODROP_EGR_FULL |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 				 HFI1_CAP_SDMA |			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 				 HFI1_CAP_PRINT_UNIMPL |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 				 HFI1_CAP_STATIC_RATE_CTRL |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 				 HFI1_CAP_PKEY_CHECK |			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 				 HFI1_CAP_MULTI_PKT_EGR |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 				 HFI1_CAP_EXTENDED_PSN |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 				 HFI1_CAP_AIP |				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 				 ((HFI1_CAP_HDRSUPP |			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 				   HFI1_CAP_MULTI_PKT_EGR |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 				   HFI1_CAP_STATIC_RATE_CTRL |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 				   HFI1_CAP_PKEY_CHECK |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 				   HFI1_CAP_EARLY_CREDIT_RETURN) <<	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 				  HFI1_CAP_USER_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  * A bitmask of kernel/global capabilities that should be communicated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  * to user level processes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define HFI1_CAP_K2U (HFI1_CAP_SDMA |			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		     HFI1_CAP_EXTENDED_PSN |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		     HFI1_CAP_PKEY_CHECK |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		     HFI1_CAP_NO_INTEGRITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define HFI1_USER_SWVERSION ((HFI1_USER_SWMAJOR << HFI1_SWMAJOR_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			     HFI1_USER_SWMINOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #ifndef HFI1_KERN_TYPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define HFI1_KERN_TYPE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)  * Similarly, this is the kernel version going back to the user.  It's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)  * slightly different, in that we want to tell if the driver was built as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  * part of a Intel release, or from the driver from openfabrics.org,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  * kernel.org, or a standard distribution, for support reasons.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)  * The high bit is 0 for non-Intel and 1 for Intel-built/supplied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  * It's returned by the driver to the user code during initialization in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  * spi_sw_version field of hfi1_base_info, so the user code can in turn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)  * check for compatibility with the kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define HFI1_KERN_SWVERSION ((HFI1_KERN_TYPE << 31) | HFI1_USER_SWVERSION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  * Define the driver version number.  This is something that refers only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)  * to the driver itself, not the software interfaces it supports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #ifndef HFI1_DRIVER_VERSION_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define HFI1_DRIVER_VERSION_BASE "0.9-294"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* create the final driver version string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #ifdef HFI1_IDSTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define HFI1_DRIVER_VERSION HFI1_DRIVER_VERSION_BASE " " HFI1_IDSTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define HFI1_DRIVER_VERSION HFI1_DRIVER_VERSION_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  * Diagnostics can send a packet by writing the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  * struct to the diag packet special file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)  * This allows a custom PBC qword, so that special modes and deliberate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)  * changes to CRCs can be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define _DIAG_PKT_VERS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct diag_pkt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	__u16 version;		/* structure version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	__u16 unit;		/* which device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	__u16 sw_index;		/* send sw index to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	__u16 len;		/* data length, in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	__u16 port;		/* port number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	__u16 unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	__u32 flags;		/* call flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	__u64 data;		/* user data pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	__u64 pbc;		/* PBC for the packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* diag_pkt flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define F_DIAGPKT_WAIT 0x1	/* wait until packet is sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)  * The next set of defines are for packet headers, and chip register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)  * and memory bits that are visible to and/or used by user-mode software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)  * Receive Header Flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define RHF_PKT_LEN_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define RHF_PKT_LEN_MASK	0xfffull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define RHF_PKT_LEN_SMASK (RHF_PKT_LEN_MASK << RHF_PKT_LEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define RHF_RCV_TYPE_SHIFT	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define RHF_RCV_TYPE_MASK	0x7ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define RHF_RCV_TYPE_SMASK (RHF_RCV_TYPE_MASK << RHF_RCV_TYPE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define RHF_USE_EGR_BFR_SHIFT	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define RHF_USE_EGR_BFR_MASK	0x1ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define RHF_USE_EGR_BFR_SMASK (RHF_USE_EGR_BFR_MASK << RHF_USE_EGR_BFR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define RHF_EGR_INDEX_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define RHF_EGR_INDEX_MASK	0x7ffull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define RHF_EGR_INDEX_SMASK (RHF_EGR_INDEX_MASK << RHF_EGR_INDEX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define RHF_DC_INFO_SHIFT	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define RHF_DC_INFO_MASK	0x1ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define RHF_DC_INFO_SMASK (RHF_DC_INFO_MASK << RHF_DC_INFO_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define RHF_RCV_SEQ_SHIFT	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define RHF_RCV_SEQ_MASK	0xfull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define RHF_RCV_SEQ_SMASK (RHF_RCV_SEQ_MASK << RHF_RCV_SEQ_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define RHF_EGR_OFFSET_SHIFT	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define RHF_EGR_OFFSET_MASK	0xfffull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define RHF_EGR_OFFSET_SMASK (RHF_EGR_OFFSET_MASK << RHF_EGR_OFFSET_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define RHF_HDRQ_OFFSET_SHIFT	44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define RHF_HDRQ_OFFSET_MASK	0x1ffull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define RHF_HDRQ_OFFSET_SMASK (RHF_HDRQ_OFFSET_MASK << RHF_HDRQ_OFFSET_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define RHF_K_HDR_LEN_ERR	(0x1ull << 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define RHF_DC_UNC_ERR		(0x1ull << 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define RHF_DC_ERR		(0x1ull << 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define RHF_RCV_TYPE_ERR_SHIFT	56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define RHF_RCV_TYPE_ERR_MASK	0x7ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define RHF_RCV_TYPE_ERR_SMASK (RHF_RCV_TYPE_ERR_MASK << RHF_RCV_TYPE_ERR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define RHF_TID_ERR		(0x1ull << 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define RHF_LEN_ERR		(0x1ull << 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define RHF_ECC_ERR		(0x1ull << 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define RHF_RESERVED		(0x1ull << 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define RHF_ICRC_ERR		(0x1ull << 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define RHF_ERROR_SMASK 0xffe0000000000000ull		/* bits 63:53 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* RHF receive types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define RHF_RCV_TYPE_EXPECTED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define RHF_RCV_TYPE_EAGER    1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define RHF_RCV_TYPE_IB       2 /* normal IB, IB Raw, or IPv6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define RHF_RCV_TYPE_ERROR    3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define RHF_RCV_TYPE_BYPASS   4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define RHF_RCV_TYPE_INVALID5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define RHF_RCV_TYPE_INVALID6 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define RHF_RCV_TYPE_INVALID7 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* RHF receive type error - expected packet errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define RHF_RTE_EXPECTED_FLOW_SEQ_ERR	0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define RHF_RTE_EXPECTED_FLOW_GEN_ERR	0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* RHF receive type error - eager packet errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define RHF_RTE_EAGER_NO_ERR		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* RHF receive type error - IB packet errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define RHF_RTE_IB_NO_ERR		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* RHF receive type error - error packet errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define RHF_RTE_ERROR_NO_ERR		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define RHF_RTE_ERROR_OP_CODE_ERR	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define RHF_RTE_ERROR_KHDR_MIN_LEN_ERR	0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define RHF_RTE_ERROR_KHDR_HCRC_ERR	0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define RHF_RTE_ERROR_KHDR_KVER_ERR	0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define RHF_RTE_ERROR_CONTEXT_ERR	0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define RHF_RTE_ERROR_KHDR_TID_ERR	0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* RHF receive type error - bypass packet errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define RHF_RTE_BYPASS_NO_ERR		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* MAX RcvSEQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define RHF_MAX_SEQ 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* IB - LRH header constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define HFI1_LRH_GRH 0x0003      /* 1. word of IB LRH - next header: GRH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define HFI1_LRH_BTH 0x0002      /* 1. word of IB LRH - next header: BTH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* misc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define SC15_PACKET 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define SIZE_OF_CRC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define SIZE_OF_LT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define MAX_16B_PADDING 12 /* CRC = 4, LT = 1, Pad = 0 to 7 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define LIM_MGMT_P_KEY       0x7FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define FULL_MGMT_P_KEY      0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define DEFAULT_P_KEY LIM_MGMT_P_KEY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define HFI1_PSM_IOC_BASE_SEQ 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* Number of BTH.PSN bits used for sequence number in expected rcvs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define HFI1_KDETH_BTH_SEQ_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define HFI1_KDETH_BTH_SEQ_MASK (BIT(HFI1_KDETH_BTH_SEQ_SHIFT) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static inline __u64 rhf_to_cpu(const __le32 *rbuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	return __le64_to_cpu(*((__le64 *)rbuf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static inline u64 rhf_err_flags(u64 rhf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	return rhf & RHF_ERROR_SMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static inline u32 rhf_rcv_type(u64 rhf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	return (rhf >> RHF_RCV_TYPE_SHIFT) & RHF_RCV_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static inline u32 rhf_rcv_type_err(u64 rhf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	return (rhf >> RHF_RCV_TYPE_ERR_SHIFT) & RHF_RCV_TYPE_ERR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* return size is in bytes, not DWORDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static inline u32 rhf_pkt_len(u64 rhf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	return ((rhf & RHF_PKT_LEN_SMASK) >> RHF_PKT_LEN_SHIFT) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static inline u32 rhf_egr_index(u64 rhf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	return (rhf >> RHF_EGR_INDEX_SHIFT) & RHF_EGR_INDEX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static inline u32 rhf_rcv_seq(u64 rhf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	return (rhf >> RHF_RCV_SEQ_SHIFT) & RHF_RCV_SEQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* returned offset is in DWORDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static inline u32 rhf_hdrq_offset(u64 rhf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	return (rhf >> RHF_HDRQ_OFFSET_SHIFT) & RHF_HDRQ_OFFSET_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static inline u64 rhf_use_egr_bfr(u64 rhf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	return rhf & RHF_USE_EGR_BFR_SMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static inline u64 rhf_dc_info(u64 rhf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	return rhf & RHF_DC_INFO_SMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static inline u32 rhf_egr_buf_offset(u64 rhf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	return (rhf >> RHF_EGR_OFFSET_SHIFT) & RHF_EGR_OFFSET_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #endif /* _COMMON_H */