^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) #ifndef _CHIP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #define _CHIP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright(c) 2015 - 2020 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is provided under a dual BSD/GPLv2 license. When using or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * redistributing this file, you may do so under either license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * GPL LICENSE SUMMARY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * it under the terms of version 2 of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * This program is distributed in the hope that it will be useful, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * BSD LICENSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * - Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * notice, this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * - Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * notice, this list of conditions and the following disclaimer in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * the documentation and/or other materials provided with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * - Neither the name of Intel Corporation nor the names of its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * contributors may be used to endorse or promote products derived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * This file contains all of the defines that is specific to the HFI chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define BITS_PER_REGISTER (BITS_PER_BYTE * sizeof(u64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define NUM_INTERRUPT_SOURCES 768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RXE_NUM_CONTEXTS 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RXE_PER_CONTEXT_SIZE 0x1000 /* 4k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RXE_NUM_TID_FLOWS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RXE_NUM_DATA_VL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TXE_NUM_CONTEXTS 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TXE_NUM_SDMA_ENGINES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define NUM_CONTEXTS_PER_SET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define VL_ARB_HIGH_PRIO_TABLE_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define VL_ARB_LOW_PRIO_TABLE_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define VL_ARB_TABLE_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TXE_NUM_32_BIT_COUNTER 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TXE_NUM_64_BIT_COUNTER 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TXE_NUM_DATA_VL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TXE_PIO_SIZE (32 * 0x100000) /* 32 MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PIO_BLOCK_SIZE 64 /* bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SDMA_BLOCK_SIZE 64 /* bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RCV_BUF_BLOCK_SIZE 64 /* bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PIO_CMASK 0x7ff /* counter mask for free and fill counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MAX_EAGER_ENTRIES 2048 /* max receive eager entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MAX_TID_PAIR_ENTRIES 1024 /* max receive expected pairs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Virtual? Allocation Unit, defined as AU = 8*2^vAU, 64 bytes, AU is fixed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * at 64 bytes for all generation one devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CM_VAU 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* HFI link credit count, AKA receive buffer depth (RBUF_DEPTH) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CM_GLOBAL_CREDITS 0x880
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Number of PKey entries in the HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MAX_PKEY_VALUES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #include "chip_registers.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RXE_PER_CONTEXT_USER (RXE + RXE_PER_CONTEXT_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TXE_PIO_SEND (TXE + TXE_PIO_SEND_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* PBC flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PBC_INTR BIT_ULL(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PBC_DC_INFO_SHIFT (30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PBC_DC_INFO BIT_ULL(PBC_DC_INFO_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PBC_TEST_EBP BIT_ULL(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PBC_PACKET_BYPASS BIT_ULL(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PBC_CREDIT_RETURN BIT_ULL(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PBC_INSERT_BYPASS_ICRC BIT_ULL(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PBC_TEST_BAD_ICRC BIT_ULL(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PBC_FECN BIT_ULL(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* PbcInsertHcrc field settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PBC_IHCRC_LKDETH 0x0 /* insert @ local KDETH offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PBC_IHCRC_GKDETH 0x1 /* insert @ global KDETH offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PBC_IHCRC_NONE 0x2 /* no HCRC inserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* PBC fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PBC_STATIC_RATE_CONTROL_COUNT_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PBC_STATIC_RATE_CONTROL_COUNT_MASK 0xffffull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PBC_STATIC_RATE_CONTROL_COUNT_SMASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) (PBC_STATIC_RATE_CONTROL_COUNT_MASK << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PBC_STATIC_RATE_CONTROL_COUNT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PBC_INSERT_HCRC_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PBC_INSERT_HCRC_MASK 0x3ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PBC_INSERT_HCRC_SMASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) (PBC_INSERT_HCRC_MASK << PBC_INSERT_HCRC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PBC_VL_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PBC_VL_MASK 0xfull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PBC_VL_SMASK (PBC_VL_MASK << PBC_VL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PBC_LENGTH_DWS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PBC_LENGTH_DWS_MASK 0xfffull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PBC_LENGTH_DWS_SMASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) (PBC_LENGTH_DWS_MASK << PBC_LENGTH_DWS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Credit Return Fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CR_COUNTER_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CR_COUNTER_MASK 0x7ffull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CR_COUNTER_SMASK (CR_COUNTER_MASK << CR_COUNTER_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CR_STATUS_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CR_STATUS_MASK 0x1ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CR_STATUS_SMASK (CR_STATUS_MASK << CR_STATUS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CR_CREDIT_RETURN_DUE_TO_PBC_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CR_CREDIT_RETURN_DUE_TO_PBC_MASK 0x1ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CR_CREDIT_RETURN_DUE_TO_PBC_SMASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) (CR_CREDIT_RETURN_DUE_TO_PBC_MASK << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) CR_CREDIT_RETURN_DUE_TO_PBC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CR_CREDIT_RETURN_DUE_TO_THRESHOLD_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CR_CREDIT_RETURN_DUE_TO_THRESHOLD_MASK 0x1ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CR_CREDIT_RETURN_DUE_TO_THRESHOLD_SMASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) (CR_CREDIT_RETURN_DUE_TO_THRESHOLD_MASK << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) CR_CREDIT_RETURN_DUE_TO_THRESHOLD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CR_CREDIT_RETURN_DUE_TO_ERR_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CR_CREDIT_RETURN_DUE_TO_ERR_MASK 0x1ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CR_CREDIT_RETURN_DUE_TO_ERR_SMASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) (CR_CREDIT_RETURN_DUE_TO_ERR_MASK << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) CR_CREDIT_RETURN_DUE_TO_ERR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CR_CREDIT_RETURN_DUE_TO_FORCE_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CR_CREDIT_RETURN_DUE_TO_FORCE_MASK 0x1ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CR_CREDIT_RETURN_DUE_TO_FORCE_SMASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) (CR_CREDIT_RETURN_DUE_TO_FORCE_MASK << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) CR_CREDIT_RETURN_DUE_TO_FORCE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Specific IRQ sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CCE_ERR_INT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define RXE_ERR_INT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MISC_ERR_INT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PIO_ERR_INT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SDMA_ERR_INT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define EGRESS_ERR_INT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define TXE_ERR_INT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define PBC_INT 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define GPIO_ASSERT_INT 241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define QSFP1_INT 242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define QSFP2_INT 243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TCRIT_INT 244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* interrupt source ranges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define IS_FIRST_SOURCE CCE_ERR_INT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define IS_GENERAL_ERR_START 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define IS_SDMAENG_ERR_START 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define IS_SENDCTXT_ERR_START 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define IS_SDMA_START 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define IS_SDMA_PROGRESS_START 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define IS_SDMA_IDLE_START 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define IS_VARIOUS_START 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define IS_DC_START 248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define IS_RCVAVAIL_START 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define IS_RCVURGENT_START 416
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define IS_SENDCREDIT_START 576
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define IS_RESERVED_START 736
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define IS_LAST_SOURCE 767
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* derived interrupt source values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define IS_GENERAL_ERR_END 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define IS_SDMAENG_ERR_END 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define IS_SENDCTXT_ERR_END 191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define IS_SDMA_END 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define IS_SDMA_PROGRESS_END 223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IS_SDMA_IDLE_END 239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define IS_VARIOUS_END 244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IS_DC_END 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define IS_RCVAVAIL_END 415
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IS_RCVURGENT_END 575
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define IS_SENDCREDIT_END 735
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IS_RESERVED_END IS_LAST_SOURCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* DCC_CFG_PORT_CONFIG logical link states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define LSTATE_DOWN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define LSTATE_INIT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define LSTATE_ARMED 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define LSTATE_ACTIVE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* DCC_CFG_RESET reset states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define LCB_RX_FPE_TX_FPE_INTO_RESET (DCC_CFG_RESET_RESET_LCB | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) DCC_CFG_RESET_RESET_TX_FPE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) DCC_CFG_RESET_RESET_RX_FPE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) DCC_CFG_RESET_ENABLE_CCLK_BCC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* 0x17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define LCB_RX_FPE_TX_FPE_OUT_OF_RESET DCC_CFG_RESET_ENABLE_CCLK_BCC /* 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* DC8051_STS_CUR_STATE port values (physical link states) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define PLS_DISABLED 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define PLS_OFFLINE 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define PLS_OFFLINE_QUIET 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define PLS_OFFLINE_PLANNED_DOWN_INFORM 0x91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define PLS_OFFLINE_READY_TO_QUIET_LT 0x92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define PLS_OFFLINE_REPORT_FAILURE 0x93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define PLS_OFFLINE_READY_TO_QUIET_BCC 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define PLS_OFFLINE_QUIET_DURATION 0x95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define PLS_POLLING 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define PLS_POLLING_QUIET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define PLS_POLLING_ACTIVE 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define PLS_CONFIGPHY 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define PLS_CONFIGPHY_DEBOUCE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define PLS_CONFIGPHY_ESTCOMM 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define PLS_CONFIGPHY_ESTCOMM_TXRX_HUNT 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define PLS_CONFIGPHY_ESTCOMM_LOCAL_COMPLETE 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define PLS_CONFIGPHY_OPTEQ 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define PLS_CONFIGPHY_OPTEQ_OPTIMIZING 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define PLS_CONFIGPHY_OPTEQ_LOCAL_COMPLETE 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define PLS_CONFIGPHY_VERIFYCAP 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define PLS_CONFIGPHY_VERIFYCAP_EXCHANGE 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define PLS_CONFIGPHY_VERIFYCAP_LOCAL_COMPLETE 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define PLS_CONFIGLT 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define PLS_CONFIGLT_CONFIGURE 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define PLS_CONFIGLT_LINK_TRANSFER_ACTIVE 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define PLS_LINKUP 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define PLS_PHYTEST 0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define PLS_INTERNAL_SERDES_LOOPBACK 0xe1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define PLS_QUICK_LINKUP 0xe2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* DC_DC8051_CFG_HOST_CMD_0.REQ_TYPE - 8051 host commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define HCMD_LOAD_CONFIG_DATA 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define HCMD_READ_CONFIG_DATA 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define HCMD_CHANGE_PHY_STATE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define HCMD_SEND_LCB_IDLE_MSG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define HCMD_MISC 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define HCMD_READ_LCB_IDLE_MSG 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define HCMD_READ_LCB_CSR 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define HCMD_WRITE_LCB_CSR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define HCMD_INTERFACE_TEST 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* DC_DC8051_CFG_HOST_CMD_1.RETURN_CODE - 8051 host command return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define HCMD_SUCCESS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* DC_DC8051_DBG_ERR_INFO_SET_BY_8051.ERROR - error flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define SPICO_ROM_FAILED BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define UNKNOWN_FRAME BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define TARGET_BER_NOT_MET BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define FAILED_SERDES_INTERNAL_LOOPBACK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define FAILED_SERDES_INIT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define FAILED_LNI_POLLING BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define FAILED_LNI_DEBOUNCE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define FAILED_LNI_ESTBCOMM BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define FAILED_LNI_OPTEQ BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define FAILED_LNI_VERIFY_CAP1 BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define FAILED_LNI_VERIFY_CAP2 BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define FAILED_LNI_CONFIGLT BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define HOST_HANDSHAKE_TIMEOUT BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define EXTERNAL_DEVICE_REQ_TIMEOUT BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define FAILED_LNI (FAILED_LNI_POLLING | FAILED_LNI_DEBOUNCE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) | FAILED_LNI_ESTBCOMM | FAILED_LNI_OPTEQ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) | FAILED_LNI_VERIFY_CAP1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) | FAILED_LNI_VERIFY_CAP2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) | FAILED_LNI_CONFIGLT | HOST_HANDSHAKE_TIMEOUT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) | EXTERNAL_DEVICE_REQ_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* DC_DC8051_DBG_ERR_INFO_SET_BY_8051.HOST_MSG - host message flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define HOST_REQ_DONE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define BC_PWR_MGM_MSG BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define BC_SMA_MSG BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define BC_BCC_UNKNOWN_MSG BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define BC_IDLE_UNKNOWN_MSG BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define EXT_DEVICE_CFG_REQ BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define VERIFY_CAP_FRAME BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define LINKUP_ACHIEVED BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define LINK_GOING_DOWN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define LINK_WIDTH_DOWNGRADED BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* DC_DC8051_CFG_EXT_DEV_1.REQ_TYPE - 8051 host requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define HREQ_LOAD_CONFIG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define HREQ_SAVE_CONFIG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define HREQ_READ_CONFIG 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define HREQ_SET_TX_EQ_ABS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define HREQ_SET_TX_EQ_REL 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define HREQ_ENABLE 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define HREQ_LCB_RESET 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define HREQ_CONFIG_DONE 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define HREQ_INTERFACE_TEST 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* DC_DC8051_CFG_EXT_DEV_0.RETURN_CODE - 8051 host request return codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define HREQ_INVALID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define HREQ_SUCCESS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define HREQ_NOT_SUPPORTED 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define HREQ_FEATURE_NOT_SUPPORTED 0x04 /* request specific feature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define HREQ_REQUEST_REJECTED 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define HREQ_EXECUTION_ONGOING 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* MISC host command functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define HCMD_MISC_REQUEST_LCB_ACCESS 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define HCMD_MISC_GRANT_LCB_ACCESS 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* idle flit message types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define IDLE_PHYSICAL_LINK_MGMT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define IDLE_CRU 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define IDLE_SMA 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define IDLE_POWER_MGMT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* idle flit message send fields (both send and read) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define IDLE_PAYLOAD_MASK 0xffffffffffull /* 40 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define IDLE_PAYLOAD_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define IDLE_MSG_TYPE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define IDLE_MSG_TYPE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* idle flit message read fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define READ_IDLE_MSG_TYPE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define READ_IDLE_MSG_TYPE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* SMA idle flit payload commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define SMA_IDLE_ARM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define SMA_IDLE_ACTIVE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* DC_DC8051_CFG_MODE.GENERAL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define DISABLE_SELF_GUID_CHECK 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* Bad L2 frame error code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define BAD_L2_ERR 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * Eager buffer minimum and maximum sizes supported by the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * All power-of-two sizes in between are supported as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * MAX_EAGER_BUFFER_TOTAL is the maximum size of memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * allocatable for Eager buffer to a single context. All others
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * are limits for the RcvArray entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define MIN_EAGER_BUFFER (4 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define MAX_EAGER_BUFFER (256 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define MAX_EAGER_BUFFER_TOTAL (64 * (1 << 20)) /* max per ctxt 64MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define MAX_EXPECTED_BUFFER (2048 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define HFI1_MIN_HDRQ_EGRBUF_CNT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define HFI1_MAX_HDRQ_EGRBUF_CNT 16352
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * Receive expected base and count and eager base and count increment -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * the CSR fields hold multiples of this value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define RCV_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define RCV_INCREMENT BIT(RCV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * Receive header queue entry increment - the CSR holds multiples of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * this value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define HDRQ_SIZE_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define HDRQ_INCREMENT BIT(HDRQ_SIZE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * Freeze handling flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define FREEZE_ABORT 0x01 /* do not do recovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define FREEZE_SELF 0x02 /* initiate the freeze */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define FREEZE_LINK_DOWN 0x04 /* link is down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * Chip implementation codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define ICODE_RTL_SILICON 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define ICODE_RTL_VCS_SIMULATION 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define ICODE_FPGA_EMULATION 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define ICODE_FUNCTIONAL_SIMULATOR 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * 8051 data memory size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define DC8051_DATA_MEM_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * 8051 firmware registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define NUM_GENERAL_FIELDS 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define NUM_LANE_FIELDS 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* 8051 general register Field IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define LINK_OPTIMIZATION_SETTINGS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define LINK_TUNING_PARAMETERS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define DC_HOST_COMM_SETTINGS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define TX_SETTINGS 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define VERIFY_CAP_LOCAL_PHY 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define VERIFY_CAP_LOCAL_FABRIC 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define VERIFY_CAP_LOCAL_LINK_MODE 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define LOCAL_DEVICE_ID 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define RESERVED_REGISTERS 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define LOCAL_LNI_INFO 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define REMOTE_LNI_INFO 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define MISC_STATUS 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define VERIFY_CAP_REMOTE_PHY 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define VERIFY_CAP_REMOTE_FABRIC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define VERIFY_CAP_REMOTE_LINK_WIDTH 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define LAST_LOCAL_STATE_COMPLETE 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define LAST_REMOTE_STATE_COMPLETE 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define LINK_QUALITY_INFO 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define REMOTE_DEVICE_ID 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define LINK_DOWN_REASON 0x16 /* first byte of offset 0x16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define VERSION_PATCH 0x16 /* last byte of offset 0x16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* 8051 lane specific register field IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define TX_EQ_SETTINGS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define CHANNEL_LOSS_SETTINGS 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* Lane ID for general configuration registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define GENERAL_CONFIG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* LINK_TUNING_PARAMETERS fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define TUNING_METHOD_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* LINK_OPTIMIZATION_SETTINGS fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define ENABLE_EXT_DEV_CONFIG_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* LOAD_DATA 8051 command shifts and fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define LOAD_DATA_FIELD_ID_SHIFT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define LOAD_DATA_FIELD_ID_MASK 0xfull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define LOAD_DATA_LANE_ID_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define LOAD_DATA_LANE_ID_MASK 0xfull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define LOAD_DATA_DATA_SHIFT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define LOAD_DATA_DATA_MASK 0xffffffffull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* READ_DATA 8051 command shifts and fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define READ_DATA_FIELD_ID_SHIFT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define READ_DATA_FIELD_ID_MASK 0xffull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define READ_DATA_LANE_ID_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define READ_DATA_LANE_ID_MASK 0xffull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define READ_DATA_DATA_SHIFT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define READ_DATA_DATA_MASK 0xffffffffull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* TX settings fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define ENABLE_LANE_TX_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define ENABLE_LANE_TX_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define TX_POLARITY_INVERSION_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define TX_POLARITY_INVERSION_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define RX_POLARITY_INVERSION_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define RX_POLARITY_INVERSION_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define MAX_RATE_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define MAX_RATE_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* verify capability PHY fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define CONTINIOUS_REMOTE_UPDATE_SUPPORT_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define POWER_MANAGEMENT_SHIFT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define POWER_MANAGEMENT_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* 8051 lane register Field IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define SPICO_FW_VERSION 0x7 /* SPICO firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* SPICO firmware version fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define SPICO_ROM_VERSION_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define SPICO_ROM_VERSION_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define SPICO_ROM_PROD_ID_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define SPICO_ROM_PROD_ID_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* verify capability fabric fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define VAU_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define VAU_MASK 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define Z_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define Z_MASK 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define VCU_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define VCU_MASK 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define VL15BUF_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define VL15BUF_MASK 0x0fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define CRC_SIZES_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define CRC_SIZES_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* verify capability local link width fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define LINK_WIDTH_SHIFT 0 /* also for remote link width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define LINK_WIDTH_MASK 0xffff /* also for remote link width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define LOCAL_FLAG_BITS_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define LOCAL_FLAG_BITS_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define MISC_CONFIG_BITS_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define MISC_CONFIG_BITS_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* verify capability remote link width fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define REMOTE_TX_RATE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define REMOTE_TX_RATE_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* LOCAL_DEVICE_ID fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define LOCAL_DEVICE_REV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define LOCAL_DEVICE_REV_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define LOCAL_DEVICE_ID_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define LOCAL_DEVICE_ID_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* REMOTE_DEVICE_ID fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define REMOTE_DEVICE_REV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define REMOTE_DEVICE_REV_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define REMOTE_DEVICE_ID_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define REMOTE_DEVICE_ID_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* local LNI link width fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define ENABLE_LANE_RX_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define ENABLE_LANE_RX_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* mask, shift for reading 'mgmt_enabled' value from REMOTE_LNI_INFO field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define MGMT_ALLOWED_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define MGMT_ALLOWED_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* mask, shift for 'link_quality' within LINK_QUALITY_INFO field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define LINK_QUALITY_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define LINK_QUALITY_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * mask, shift for reading 'planned_down_remote_reason_code'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * from LINK_QUALITY_INFO field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define DOWN_REMOTE_REASON_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define DOWN_REMOTE_REASON_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define HOST_INTERFACE_VERSION 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define HOST_INTERFACE_VERSION_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define HOST_INTERFACE_VERSION_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* verify capability PHY power management bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define PWRM_BER_CONTROL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define PWRM_BANDWIDTH_CONTROL 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* 8051 link down reasons */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define LDR_LINK_TRANSFER_ACTIVE_LOW 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define LDR_RECEIVED_LINKDOWN_IDLE_MSG 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define LDR_RECEIVED_HOST_OFFLINE_REQ 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* verify capability fabric CRC size bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) CAP_CRC_14B = (1 << 0), /* 14b CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) CAP_CRC_48B = (1 << 1), /* 48b CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) CAP_CRC_12B_16B_PER_LANE = (1 << 2) /* 12b-16b per lane CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define SUPPORTED_CRCS (CAP_CRC_14B | CAP_CRC_48B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* misc status version fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define STS_FM_VERSION_MINOR_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define STS_FM_VERSION_MINOR_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define STS_FM_VERSION_MAJOR_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define STS_FM_VERSION_MAJOR_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define STS_FM_VERSION_PATCH_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define STS_FM_VERSION_PATCH_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* LCB_CFG_CRC_MODE TX_VAL and RX_VAL CRC mode values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define LCB_CRC_16B 0x0 /* 16b CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define LCB_CRC_14B 0x1 /* 14b CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define LCB_CRC_48B 0x2 /* 48b CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define LCB_CRC_12B_16B_PER_LANE 0x3 /* 12b-16b per lane CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * the following enum is (almost) a copy/paste of the definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * in the OPA spec, section 20.2.2.6.8 (PortInfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) PORT_LTP_CRC_MODE_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) PORT_LTP_CRC_MODE_14 = 1, /* 14-bit LTP CRC mode (optional) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) PORT_LTP_CRC_MODE_16 = 2, /* 16-bit LTP CRC mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) PORT_LTP_CRC_MODE_48 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* 48-bit overlapping LTP CRC mode (optional) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) PORT_LTP_CRC_MODE_PER_LANE = 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* 12 to 16 bit per lane LTP CRC mode (optional) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* timeouts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define LINK_RESTART_DELAY 1000 /* link restart delay, in ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define TIMEOUT_8051_START 5000 /* 8051 start timeout, in ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define DC8051_COMMAND_TIMEOUT 1000 /* DC8051 command timeout, in ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define FREEZE_STATUS_TIMEOUT 20 /* wait for freeze indicators, in ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define VL_STATUS_CLEAR_TIMEOUT 5000 /* per-VL status clear, in ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define CCE_STATUS_TIMEOUT 10 /* time to clear CCE Status, in ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* cclock tick time, in picoseconds per tick: 1/speed * 10^12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define ASIC_CCLOCK_PS 1242 /* 805 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define FPGA_CCLOCK_PS 30300 /* 33 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * Mask of enabled MISC errors. Do not enable the two RSA engine errors -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * see firmware.c:run_rsa() for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define DRIVER_MISC_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) (~(MISC_ERR_STATUS_MISC_FW_AUTH_FAILED_ERR_SMASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) | MISC_ERR_STATUS_MISC_KEY_MISMATCH_ERR_SMASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* valid values for the loopback module parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define LOOPBACK_NONE 0 /* no loopback - default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define LOOPBACK_SERDES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define LOOPBACK_LCB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define LOOPBACK_CABLE 3 /* external cable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* set up bits in MISC_CONFIG_BITS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define LOOPBACK_SERDES_CONFIG_BIT_MASK_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define EXT_CFG_LCB_RESET_SUPPORTED_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* read and write hardware registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) u64 read_csr(const struct hfi1_devdata *dd, u32 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * The *_kctxt_* flavor of the CSR read/write functions are for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * per-context or per-SDMA CSRs that are not mappable to user-space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * Their spacing is not a PAGE_SIZE multiple.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static inline u64 read_kctxt_csr(const struct hfi1_devdata *dd, int ctxt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) u32 offset0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* kernel per-context CSRs are separated by 0x100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return read_csr(dd, offset0 + (0x100 * ctxt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static inline void write_kctxt_csr(struct hfi1_devdata *dd, int ctxt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) u32 offset0, u64 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* kernel per-context CSRs are separated by 0x100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) write_csr(dd, offset0 + (0x100 * ctxt), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) int read_lcb_csr(struct hfi1_devdata *dd, u32 offset, u64 *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) int write_lcb_csr(struct hfi1_devdata *dd, u32 offset, u64 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) void __iomem *get_csr_addr(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) const struct hfi1_devdata *dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) u32 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static inline void __iomem *get_kctxt_csr_addr(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) const struct hfi1_devdata *dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) int ctxt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) u32 offset0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return get_csr_addr(dd, offset0 + (0x100 * ctxt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * The *_uctxt_* flavor of the CSR read/write functions are for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * per-context CSRs that are mappable to user space. All these CSRs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * are spaced by a PAGE_SIZE multiple in order to be mappable to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * different processes without exposing other contexts' CSRs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static inline u64 read_uctxt_csr(const struct hfi1_devdata *dd, int ctxt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) u32 offset0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* user per-context CSRs are separated by 0x1000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return read_csr(dd, offset0 + (0x1000 * ctxt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static inline void write_uctxt_csr(struct hfi1_devdata *dd, int ctxt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) u32 offset0, u64 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* user per-context CSRs are separated by 0x1000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) write_csr(dd, offset0 + (0x1000 * ctxt), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static inline u32 chip_rcv_contexts(struct hfi1_devdata *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return read_csr(dd, RCV_CONTEXTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static inline u32 chip_send_contexts(struct hfi1_devdata *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return read_csr(dd, SEND_CONTEXTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static inline u32 chip_sdma_engines(struct hfi1_devdata *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return read_csr(dd, SEND_DMA_ENGINES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static inline u32 chip_pio_mem_size(struct hfi1_devdata *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return read_csr(dd, SEND_PIO_MEM_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static inline u32 chip_sdma_mem_size(struct hfi1_devdata *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return read_csr(dd, SEND_DMA_MEM_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static inline u32 chip_rcv_array_count(struct hfi1_devdata *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return read_csr(dd, RCV_ARRAY_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) u8 encode_rcv_header_entry_size(u8 size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) int hfi1_validate_rcvhdrcnt(struct hfi1_devdata *dd, uint thecnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) void set_hdrq_regs(struct hfi1_devdata *dd, u8 ctxt, u8 entsize, u16 hdrcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u64 create_pbc(struct hfi1_pportdata *ppd, u64 flags, int srate_mbs, u32 vl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) u32 dw_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* firmware.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define SBUS_MASTER_BROADCAST 0xfd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define NUM_PCIE_SERDES 16 /* number of PCIe serdes on the SBus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) extern const u8 pcie_serdes_broadcast[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) extern const u8 pcie_pcs_addrs[2][NUM_PCIE_SERDES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /* SBus commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define RESET_SBUS_RECEIVER 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define WRITE_SBUS_RECEIVER 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define READ_SBUS_RECEIVER 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) void sbus_request(struct hfi1_devdata *dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) u8 receiver_addr, u8 data_addr, u8 command, u32 data_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) int sbus_request_slow(struct hfi1_devdata *dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) u8 receiver_addr, u8 data_addr, u8 command, u32 data_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) void set_sbus_fast_mode(struct hfi1_devdata *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) void clear_sbus_fast_mode(struct hfi1_devdata *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) int hfi1_firmware_init(struct hfi1_devdata *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) int load_pcie_firmware(struct hfi1_devdata *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) int load_firmware(struct hfi1_devdata *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) void dispose_firmware(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) int acquire_hw_mutex(struct hfi1_devdata *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) void release_hw_mutex(struct hfi1_devdata *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * Bitmask of dynamic access for ASIC block chip resources. Each HFI has its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * own range of bits for the resource so it can clear its own bits on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * starting and exiting. If either HFI has the resource bit set, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * resource is in use. The separate bit ranges are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * HFI0 bits 7:0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * HFI1 bits 15:8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define CR_SBUS 0x01 /* SBUS, THERM, and PCIE registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define CR_EPROM 0x02 /* EEP, GPIO registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define CR_I2C1 0x04 /* QSFP1_OE register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define CR_I2C2 0x08 /* QSFP2_OE register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define CR_DYN_SHIFT 8 /* dynamic flag shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define CR_DYN_MASK ((1ull << CR_DYN_SHIFT) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * Bitmask of static ASIC states these are outside of the dynamic ASIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * block chip resources above. These are to be set once and never cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * Must be holding the SBus dynamic flag when setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define CR_THERM_INIT 0x010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) int acquire_chip_resource(struct hfi1_devdata *dd, u32 resource, u32 mswait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) void release_chip_resource(struct hfi1_devdata *dd, u32 resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) bool check_chip_resource(struct hfi1_devdata *dd, u32 resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) const char *func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) void init_chip_resources(struct hfi1_devdata *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) void finish_chip_resources(struct hfi1_devdata *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* ms wait time for access to an SBus resoure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define SBUS_TIMEOUT 4000 /* long enough for a FW download and SBR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* ms wait time for a qsfp (i2c) chain to become available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define QSFP_WAIT 20000 /* long enough for FW update to the F4 uc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) void fabric_serdes_reset(struct hfi1_devdata *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) int read_8051_data(struct hfi1_devdata *dd, u32 addr, u32 len, u64 *result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* chip.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) void read_misc_status(struct hfi1_devdata *dd, u8 *ver_major, u8 *ver_minor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) u8 *ver_patch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) int write_host_interface_version(struct hfi1_devdata *dd, u8 version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) void read_guid(struct hfi1_devdata *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) int wait_fm_ready(struct hfi1_devdata *dd, u32 mstimeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) void set_link_down_reason(struct hfi1_pportdata *ppd, u8 lcl_reason,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) u8 neigh_reason, u8 rem_reason);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) int set_link_state(struct hfi1_pportdata *, u32 state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) int port_ltp_to_cap(int port_ltp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) void handle_verify_cap(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) void handle_freeze(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) void handle_link_up(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) void handle_link_down(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) void handle_link_downgrade(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) void handle_link_bounce(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) void handle_start_link(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) void handle_sma_message(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) int reset_qsfp(struct hfi1_pportdata *ppd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) void qsfp_event(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) void start_freeze_handling(struct hfi1_pportdata *ppd, int flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) int send_idle_sma(struct hfi1_devdata *dd, u64 message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) int load_8051_config(struct hfi1_devdata *, u8, u8, u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) int read_8051_config(struct hfi1_devdata *, u8, u8, u32 *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) int start_link(struct hfi1_pportdata *ppd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) int bringup_serdes(struct hfi1_pportdata *ppd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) void set_intr_state(struct hfi1_devdata *dd, u32 enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) bool apply_link_downgrade_policy(struct hfi1_pportdata *ppd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) bool refresh_widths);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) void update_usrhead(struct hfi1_ctxtdata *rcd, u32 hd, u32 updegr, u32 egrhd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) u32 intr_adjust, u32 npkts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) int stop_drain_data_vls(struct hfi1_devdata *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) int open_fill_data_vls(struct hfi1_devdata *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) u32 ns_to_cclock(struct hfi1_devdata *dd, u32 ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) u32 cclock_to_ns(struct hfi1_devdata *dd, u32 cclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) void get_linkup_link_widths(struct hfi1_pportdata *ppd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) void read_ltp_rtt(struct hfi1_devdata *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) void clear_linkup_counters(struct hfi1_devdata *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) u32 hdrqempty(struct hfi1_ctxtdata *rcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) int is_ax(struct hfi1_devdata *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) int is_bx(struct hfi1_devdata *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) bool is_urg_masked(struct hfi1_ctxtdata *rcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) u32 read_physical_state(struct hfi1_devdata *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) u32 chip_to_opa_pstate(struct hfi1_devdata *dd, u32 chip_pstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) const char *opa_lstate_name(u32 lstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) const char *opa_pstate_name(u32 pstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) u32 driver_pstate(struct hfi1_pportdata *ppd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) u32 driver_lstate(struct hfi1_pportdata *ppd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) int acquire_lcb_access(struct hfi1_devdata *dd, int sleep_ok);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) int release_lcb_access(struct hfi1_devdata *dd, int sleep_ok);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define LCB_START DC_LCB_CSRS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define LCB_END DC_8051_CSRS /* next block is 8051 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static inline int is_lcb_offset(u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return (offset >= LCB_START && offset < LCB_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) extern uint num_vls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) extern uint disable_integrity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) u64 read_dev_cntr(struct hfi1_devdata *dd, int index, int vl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) u64 write_dev_cntr(struct hfi1_devdata *dd, int index, int vl, u64 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) u64 read_port_cntr(struct hfi1_pportdata *ppd, int index, int vl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) u64 write_port_cntr(struct hfi1_pportdata *ppd, int index, int vl, u64 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) u32 read_logical_state(struct hfi1_devdata *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) void force_recv_intr(struct hfi1_ctxtdata *rcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /* Per VL indexes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) C_VL_0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) C_VL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) C_VL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) C_VL_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) C_VL_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) C_VL_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) C_VL_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) C_VL_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) C_VL_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) C_VL_COUNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static inline int vl_from_idx(int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return (idx == C_VL_15 ? 15 : idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static inline int idx_from_vl(int vl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return (vl == 15 ? C_VL_15 : vl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /* Per device counter indexes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) C_RCV_OVF = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) C_RX_LEN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) C_RX_SHORT_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) C_RX_ICRC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) C_RX_EBP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) C_RX_TID_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) C_RX_TID_INVALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) C_RX_TID_FLGMS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) C_RX_CTX_EGRS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) C_RCV_TID_FLSMS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) C_CCE_PCI_CR_ST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) C_CCE_PCI_TR_ST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) C_CCE_PIO_WR_ST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) C_CCE_ERR_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) C_CCE_SDMA_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) C_CCE_MISC_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) C_CCE_RCV_AV_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) C_CCE_RCV_URG_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) C_CCE_SEND_CR_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) C_DC_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) C_DC_RCV_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) C_DC_FM_CFG_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) C_DC_RMT_PHY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) C_DC_DROPPED_PKT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) C_DC_MC_XMIT_PKTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) C_DC_MC_RCV_PKTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) C_DC_XMIT_CERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) C_DC_RCV_CERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) C_DC_RCV_FCC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) C_DC_XMIT_FCC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) C_DC_XMIT_FLITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) C_DC_RCV_FLITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) C_DC_XMIT_PKTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) C_DC_RCV_PKTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) C_DC_RX_FLIT_VL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) C_DC_RX_PKT_VL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) C_DC_RCV_FCN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) C_DC_RCV_FCN_VL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) C_DC_RCV_BCN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) C_DC_RCV_BCN_VL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) C_DC_RCV_BBL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) C_DC_RCV_BBL_VL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) C_DC_MARK_FECN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) C_DC_MARK_FECN_VL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) C_DC_TOTAL_CRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) C_DC_CRC_LN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) C_DC_CRC_LN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) C_DC_CRC_LN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) C_DC_CRC_LN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) C_DC_CRC_MULT_LN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) C_DC_TX_REPLAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) C_DC_RX_REPLAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) C_DC_SEQ_CRC_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) C_DC_ESC0_ONLY_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) C_DC_ESC0_PLUS1_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) C_DC_ESC0_PLUS2_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) C_DC_REINIT_FROM_PEER_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) C_DC_SBE_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) C_DC_MISC_FLG_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) C_DC_PRF_GOOD_LTP_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) C_DC_PRF_ACCEPTED_LTP_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) C_DC_PRF_RX_FLIT_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) C_DC_PRF_TX_FLIT_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) C_DC_PRF_CLK_CNTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) C_DC_PG_DBG_FLIT_CRDTS_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) C_DC_PG_STS_PAUSE_COMPLETE_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) C_DC_PG_STS_TX_SBE_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) C_DC_PG_STS_TX_MBE_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) C_SW_CPU_INTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) C_SW_CPU_RCV_LIM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) C_SW_CTX0_SEQ_DROP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) C_SW_VTX_WAIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) C_SW_PIO_WAIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) C_SW_PIO_DRAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) C_SW_KMEM_WAIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) C_SW_TID_WAIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) C_SW_SEND_SCHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) C_SDMA_DESC_FETCHED_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) C_SDMA_INT_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) C_SDMA_ERR_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) C_SDMA_IDLE_INT_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) C_SDMA_PROGRESS_INT_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /* MISC_ERR_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) C_MISC_PLL_LOCK_FAIL_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) C_MISC_MBIST_FAIL_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) C_MISC_INVALID_EEP_CMD_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) C_MISC_EFUSE_DONE_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) C_MISC_EFUSE_WRITE_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) C_MISC_EFUSE_READ_BAD_ADDR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) C_MISC_EFUSE_CSR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) C_MISC_FW_AUTH_FAILED_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) C_MISC_KEY_MISMATCH_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) C_MISC_SBUS_WRITE_FAILED_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) C_MISC_CSR_WRITE_BAD_ADDR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) C_MISC_CSR_READ_BAD_ADDR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) C_MISC_CSR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /* CceErrStatus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) * A special counter that is the aggregate count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) * of all the cce_err_status errors. The remainder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * are actual bits in the CceErrStatus register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) C_CCE_ERR_STATUS_AGGREGATED_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) C_CCE_MSIX_CSR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) C_CCE_INT_MAP_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) C_CCE_INT_MAP_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) C_CCE_MSIX_TABLE_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) C_CCE_MSIX_TABLE_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) C_CCE_RXDMA_CONV_FIFO_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) C_CCE_RCPL_ASYNC_FIFO_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) C_CCE_SEG_WRITE_BAD_ADDR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) C_CCE_SEG_READ_BAD_ADDR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) C_LA_TRIGGERED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) C_CCE_TRGT_CPL_TIMEOUT_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) C_PCIC_RECEIVE_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) C_PCIC_TRANSMIT_BACK_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) C_PCIC_TRANSMIT_FRONT_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) C_PCIC_CPL_DAT_Q_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) C_PCIC_CPL_HD_Q_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) C_PCIC_POST_DAT_Q_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) C_PCIC_POST_HD_Q_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) C_PCIC_RETRY_SOT_MEM_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) C_PCIC_RETRY_MEM_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) C_PCIC_N_POST_DAT_Q_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) C_PCIC_N_POST_H_Q_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) C_PCIC_CPL_DAT_Q_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) C_PCIC_CPL_HD_Q_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) C_PCIC_POST_DAT_Q_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) C_PCIC_POST_HD_Q_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) C_PCIC_RETRY_SOT_MEM_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) C_PCIC_RETRY_MEM_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) C_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) C_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) C_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) C_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) C_CCE_CLI2_ASYNC_FIFO_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) C_CCE_CSR_CFG_BUS_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) C_CCE_CLI0_ASYNC_FIFO_PARTIY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) C_CCE_RSPD_DATA_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) C_CCE_TRGT_ACCESS_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) C_CCE_TRGT_ASYNC_FIFO_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) C_CCE_CSR_WRITE_BAD_ADDR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) C_CCE_CSR_READ_BAD_ADDR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) C_CCE_CSR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) /* RcvErrStatus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) C_RX_CSR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) C_RX_CSR_WRITE_BAD_ADDR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) C_RX_CSR_READ_BAD_ADDR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) C_RX_DMA_CSR_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) C_RX_DMA_DQ_FSM_ENCODING_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) C_RX_DMA_EQ_FSM_ENCODING_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) C_RX_DMA_CSR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) C_RX_RBUF_DATA_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) C_RX_RBUF_DATA_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) C_RX_DMA_DATA_FIFO_RD_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) C_RX_DMA_DATA_FIFO_RD_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) C_RX_DMA_HDR_FIFO_RD_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) C_RX_DMA_HDR_FIFO_RD_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) C_RX_RBUF_DESC_PART2_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) C_RX_RBUF_DESC_PART2_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) C_RX_RBUF_DESC_PART1_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) C_RX_RBUF_DESC_PART1_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) C_RX_HQ_INTR_FSM_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) C_RX_HQ_INTR_CSR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) C_RX_LOOKUP_CSR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) C_RX_LOOKUP_RCV_ARRAY_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) C_RX_LOOKUP_RCV_ARRAY_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) C_RX_LOOKUP_DES_PART2_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) C_RX_LOOKUP_DES_PART1_UNC_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) C_RX_LOOKUP_DES_PART1_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) C_RX_RBUF_NEXT_FREE_BUF_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) C_RX_RBUF_NEXT_FREE_BUF_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) C_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) C_RX_RBUF_FL_INITDONE_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) C_RX_RBUF_FL_WRITE_ADDR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) C_RX_RBUF_FL_RD_ADDR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) C_RX_RBUF_EMPTY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) C_RX_RBUF_FULL_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) C_RX_RBUF_BAD_LOOKUP_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) C_RX_RBUF_CTX_ID_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) C_RX_RBUF_CSR_QEOPDW_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) C_RX_RBUF_CSR_Q_NUM_OF_PKT_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) C_RX_RBUF_CSR_Q_T1_PTR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) C_RX_RBUF_CSR_Q_HD_PTR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) C_RX_RBUF_CSR_Q_VLD_BIT_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) C_RX_RBUF_CSR_Q_NEXT_BUF_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) C_RX_RBUF_CSR_Q_ENT_CNT_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) C_RX_RBUF_CSR_Q_HEAD_BUF_NUM_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) C_RX_RBUF_BLOCK_LIST_READ_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) C_RX_RBUF_BLOCK_LIST_READ_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) C_RX_RBUF_LOOKUP_DES_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) C_RX_RBUF_LOOKUP_DES_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) C_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) C_RX_RBUF_LOOKUP_DES_REG_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) C_RX_RBUF_FREE_LIST_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) C_RX_RBUF_FREE_LIST_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) C_RX_RCV_FSM_ENCODING_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) C_RX_DMA_FLAG_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) C_RX_DMA_FLAG_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) C_RX_DC_SOP_EOP_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) C_RX_RCV_CSR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) C_RX_RCV_QP_MAP_TABLE_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) C_RX_RCV_QP_MAP_TABLE_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) C_RX_RCV_DATA_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) C_RX_RCV_DATA_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) C_RX_RCV_HDR_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) C_RX_RCV_HDR_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) C_RX_DC_INTF_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) C_RX_DMA_CSR_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) /* SendPioErrStatus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) C_PIO_PEC_SOP_HEAD_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) C_PIO_PCC_SOP_HEAD_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) C_PIO_LAST_RETURNED_CNT_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) C_PIO_CURRENT_FREE_CNT_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) C_PIO_RSVD_31_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) C_PIO_RSVD_30_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) C_PIO_PPMC_SOP_LEN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) C_PIO_PPMC_BQC_MEM_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) C_PIO_VL_FIFO_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) C_PIO_VLF_SOP_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) C_PIO_VLF_V1_LEN_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) C_PIO_BLOCK_QW_COUNT_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) C_PIO_WRITE_QW_VALID_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) C_PIO_STATE_MACHINE_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) C_PIO_WRITE_DATA_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) C_PIO_HOST_ADDR_MEM_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) C_PIO_HOST_ADDR_MEM_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) C_PIO_PKT_EVICT_SM_OR_ARM_SM_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) C_PIO_INIT_SM_IN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) C_PIO_PPMC_PBL_FIFO_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) C_PIO_CREDIT_RET_FIFO_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) C_PIO_V1_LEN_MEM_BANK1_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) C_PIO_V1_LEN_MEM_BANK0_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) C_PIO_V1_LEN_MEM_BANK1_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) C_PIO_V1_LEN_MEM_BANK0_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) C_PIO_SM_PKT_RESET_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) C_PIO_PKT_EVICT_FIFO_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) C_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) C_PIO_SBRDCTL_CRREL_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) C_PIO_PEC_FIFO_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) C_PIO_PCC_FIFO_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) C_PIO_SB_MEM_FIFO1_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) C_PIO_SB_MEM_FIFO0_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) C_PIO_CSR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) C_PIO_WRITE_ADDR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) C_PIO_WRITE_BAD_CTXT_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) /* SendDmaErrStatus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) C_SDMA_PCIE_REQ_TRACKING_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) C_SDMA_PCIE_REQ_TRACKING_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) C_SDMA_CSR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) C_SDMA_RPY_TAG_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) /* SendEgressErrStatus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) C_TX_READ_PIO_MEMORY_CSR_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) C_TX_READ_SDMA_MEMORY_CSR_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) C_TX_EGRESS_FIFO_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) C_TX_READ_PIO_MEMORY_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) C_TX_READ_SDMA_MEMORY_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) C_TX_SB_HDR_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) C_TX_CREDIT_OVERRUN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) C_TX_LAUNCH_FIFO8_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) C_TX_LAUNCH_FIFO7_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) C_TX_LAUNCH_FIFO6_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) C_TX_LAUNCH_FIFO5_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) C_TX_LAUNCH_FIFO4_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) C_TX_LAUNCH_FIFO3_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) C_TX_LAUNCH_FIFO2_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) C_TX_LAUNCH_FIFO1_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) C_TX_LAUNCH_FIFO0_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) C_TX_CREDIT_RETURN_VL_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) C_TX_HCRC_INSERTION_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) C_TX_EGRESS_FIFI_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) C_TX_READ_PIO_MEMORY_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) C_TX_READ_SDMA_MEMORY_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) C_TX_SB_HDR_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) C_TX_CREDIT_RETURN_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) C_TX_LAUNCH_FIFO8_UNC_OR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) C_TX_LAUNCH_FIFO7_UNC_OR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) C_TX_LAUNCH_FIFO6_UNC_OR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) C_TX_LAUNCH_FIFO5_UNC_OR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) C_TX_LAUNCH_FIFO4_UNC_OR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) C_TX_LAUNCH_FIFO3_UNC_OR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) C_TX_LAUNCH_FIFO2_UNC_OR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) C_TX_LAUNCH_FIFO1_UNC_OR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) C_TX_LAUNCH_FIFO0_UNC_OR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) C_TX_SDMA15_DISALLOWED_PACKET_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) C_TX_SDMA14_DISALLOWED_PACKET_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) C_TX_SDMA13_DISALLOWED_PACKET_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) C_TX_SDMA12_DISALLOWED_PACKET_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) C_TX_SDMA11_DISALLOWED_PACKET_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) C_TX_SDMA10_DISALLOWED_PACKET_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) C_TX_SDMA9_DISALLOWED_PACKET_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) C_TX_SDMA8_DISALLOWED_PACKET_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) C_TX_SDMA7_DISALLOWED_PACKET_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) C_TX_SDMA6_DISALLOWED_PACKET_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) C_TX_SDMA5_DISALLOWED_PACKET_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) C_TX_SDMA4_DISALLOWED_PACKET_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) C_TX_SDMA3_DISALLOWED_PACKET_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) C_TX_SDMA2_DISALLOWED_PACKET_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) C_TX_SDMA1_DISALLOWED_PACKET_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) C_TX_SDMA0_DISALLOWED_PACKET_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) C_TX_CONFIG_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) C_TX_SBRD_CTL_CSR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) C_TX_LAUNCH_CSR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) C_TX_ILLEGAL_CL_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) C_TX_SBRD_CTL_STATE_MACHINE_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) C_TX_RESERVED_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) C_TX_RESERVED_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) C_TX_SDMA_LAUNCH_INTF_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) C_TX_PIO_LAUNCH_INTF_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) C_TX_RESERVED_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) C_TX_INCORRECT_LINK_STATE_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) C_TX_LINK_DOWN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) C_TX_EGRESS_FIFO_UNDERRUN_OR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) C_TX_RESERVED_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) C_TX_PKT_INTEGRITY_MEM_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) C_TX_PKT_INTEGRITY_MEM_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /* SendErrStatus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) C_SEND_CSR_WRITE_BAD_ADDR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) C_SEND_CSR_READ_BAD_ADD_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) C_SEND_CSR_PARITY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) /* SendCtxtErrStatus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) C_PIO_WRITE_OUT_OF_BOUNDS_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) C_PIO_WRITE_OVERFLOW_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) C_PIO_WRITE_CROSSES_BOUNDARY_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) C_PIO_DISALLOWED_PACKET_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) C_PIO_INCONSISTENT_SOP_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) /*SendDmaEngErrStatus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) C_SDMA_HEADER_REQUEST_FIFO_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) C_SDMA_HEADER_STORAGE_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) C_SDMA_PACKET_TRACKING_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) C_SDMA_ASSEMBLY_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) C_SDMA_DESC_TABLE_COR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) C_SDMA_HEADER_REQUEST_FIFO_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) C_SDMA_HEADER_STORAGE_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) C_SDMA_PACKET_TRACKING_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) C_SDMA_ASSEMBLY_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) C_SDMA_DESC_TABLE_UNC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) C_SDMA_TIMEOUT_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) C_SDMA_HEADER_LENGTH_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) C_SDMA_HEADER_ADDRESS_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) C_SDMA_HEADER_SELECT_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) C_SMDA_RESERVED_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) C_SDMA_PACKET_DESC_OVERFLOW_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) C_SDMA_LENGTH_MISMATCH_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) C_SDMA_HALT_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) C_SDMA_MEM_READ_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) C_SDMA_FIRST_DESC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) C_SDMA_TAIL_OUT_OF_BOUNDS_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) C_SDMA_TOO_LONG_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) C_SDMA_GEN_MISMATCH_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) C_SDMA_WRONG_DW_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) DEV_CNTR_LAST /* Must be kept last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) /* Per port counter indexes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) C_TX_UNSUP_VL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) C_TX_INVAL_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) C_TX_MM_LEN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) C_TX_UNDERRUN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) C_TX_FLOW_STALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) C_TX_DROPPED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) C_TX_HDR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) C_TX_PKT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) C_TX_WORDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) C_TX_WAIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) C_TX_FLIT_VL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) C_TX_PKT_VL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) C_TX_WAIT_VL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) C_RX_PKT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) C_RX_WORDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) C_SW_LINK_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) C_SW_LINK_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) C_SW_UNKNOWN_FRAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) C_SW_XMIT_DSCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) C_SW_XMIT_DSCD_VL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) C_SW_XMIT_CSTR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) C_SW_RCV_CSTR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) C_SW_IBP_LOOP_PKTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) C_SW_IBP_RC_RESENDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) C_SW_IBP_RNR_NAKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) C_SW_IBP_OTHER_NAKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) C_SW_IBP_RC_TIMEOUTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) C_SW_IBP_PKT_DROPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) C_SW_IBP_DMA_WAIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) C_SW_IBP_RC_SEQNAK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) C_SW_IBP_RC_DUPREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) C_SW_IBP_RDMA_SEQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) C_SW_IBP_UNALIGNED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) C_SW_IBP_SEQ_NAK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) C_SW_IBP_RC_CRWAITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) C_SW_CPU_RC_ACKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) C_SW_CPU_RC_QACKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) C_SW_CPU_RC_DELAYED_COMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) C_RCV_HDR_OVF_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) C_RCV_HDR_OVF_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) C_RCV_HDR_OVF_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) C_RCV_HDR_OVF_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) C_RCV_HDR_OVF_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) C_RCV_HDR_OVF_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) C_RCV_HDR_OVF_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) C_RCV_HDR_OVF_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) C_RCV_HDR_OVF_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) C_RCV_HDR_OVF_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) C_RCV_HDR_OVF_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) C_RCV_HDR_OVF_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) C_RCV_HDR_OVF_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) C_RCV_HDR_OVF_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) C_RCV_HDR_OVF_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) C_RCV_HDR_OVF_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) C_RCV_HDR_OVF_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) C_RCV_HDR_OVF_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) C_RCV_HDR_OVF_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) C_RCV_HDR_OVF_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) C_RCV_HDR_OVF_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) C_RCV_HDR_OVF_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) C_RCV_HDR_OVF_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) C_RCV_HDR_OVF_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) C_RCV_HDR_OVF_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) C_RCV_HDR_OVF_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) C_RCV_HDR_OVF_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) C_RCV_HDR_OVF_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) C_RCV_HDR_OVF_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) C_RCV_HDR_OVF_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) C_RCV_HDR_OVF_30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) C_RCV_HDR_OVF_31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) C_RCV_HDR_OVF_32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) C_RCV_HDR_OVF_33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) C_RCV_HDR_OVF_34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) C_RCV_HDR_OVF_35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) C_RCV_HDR_OVF_36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) C_RCV_HDR_OVF_37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) C_RCV_HDR_OVF_38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) C_RCV_HDR_OVF_39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) C_RCV_HDR_OVF_40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) C_RCV_HDR_OVF_41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) C_RCV_HDR_OVF_42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) C_RCV_HDR_OVF_43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) C_RCV_HDR_OVF_44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) C_RCV_HDR_OVF_45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) C_RCV_HDR_OVF_46,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) C_RCV_HDR_OVF_47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) C_RCV_HDR_OVF_48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) C_RCV_HDR_OVF_49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) C_RCV_HDR_OVF_50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) C_RCV_HDR_OVF_51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) C_RCV_HDR_OVF_52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) C_RCV_HDR_OVF_53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) C_RCV_HDR_OVF_54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) C_RCV_HDR_OVF_55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) C_RCV_HDR_OVF_56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) C_RCV_HDR_OVF_57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) C_RCV_HDR_OVF_58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) C_RCV_HDR_OVF_59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) C_RCV_HDR_OVF_60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) C_RCV_HDR_OVF_61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) C_RCV_HDR_OVF_62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) C_RCV_HDR_OVF_63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) C_RCV_HDR_OVF_64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) C_RCV_HDR_OVF_65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) C_RCV_HDR_OVF_66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) C_RCV_HDR_OVF_67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) C_RCV_HDR_OVF_68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) C_RCV_HDR_OVF_69,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) C_RCV_HDR_OVF_70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) C_RCV_HDR_OVF_71,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) C_RCV_HDR_OVF_72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) C_RCV_HDR_OVF_73,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) C_RCV_HDR_OVF_74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) C_RCV_HDR_OVF_75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) C_RCV_HDR_OVF_76,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) C_RCV_HDR_OVF_77,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) C_RCV_HDR_OVF_78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) C_RCV_HDR_OVF_79,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) C_RCV_HDR_OVF_80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) C_RCV_HDR_OVF_81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) C_RCV_HDR_OVF_82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) C_RCV_HDR_OVF_83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) C_RCV_HDR_OVF_84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) C_RCV_HDR_OVF_85,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) C_RCV_HDR_OVF_86,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) C_RCV_HDR_OVF_87,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) C_RCV_HDR_OVF_88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) C_RCV_HDR_OVF_89,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) C_RCV_HDR_OVF_90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) C_RCV_HDR_OVF_91,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) C_RCV_HDR_OVF_92,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) C_RCV_HDR_OVF_93,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) C_RCV_HDR_OVF_94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) C_RCV_HDR_OVF_95,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) C_RCV_HDR_OVF_96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) C_RCV_HDR_OVF_97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) C_RCV_HDR_OVF_98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) C_RCV_HDR_OVF_99,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) C_RCV_HDR_OVF_100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) C_RCV_HDR_OVF_101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) C_RCV_HDR_OVF_102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) C_RCV_HDR_OVF_103,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) C_RCV_HDR_OVF_104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) C_RCV_HDR_OVF_105,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) C_RCV_HDR_OVF_106,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) C_RCV_HDR_OVF_107,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) C_RCV_HDR_OVF_108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) C_RCV_HDR_OVF_109,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) C_RCV_HDR_OVF_110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) C_RCV_HDR_OVF_111,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) C_RCV_HDR_OVF_112,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) C_RCV_HDR_OVF_113,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) C_RCV_HDR_OVF_114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) C_RCV_HDR_OVF_115,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) C_RCV_HDR_OVF_116,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) C_RCV_HDR_OVF_117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) C_RCV_HDR_OVF_118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) C_RCV_HDR_OVF_119,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) C_RCV_HDR_OVF_120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) C_RCV_HDR_OVF_121,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) C_RCV_HDR_OVF_122,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) C_RCV_HDR_OVF_123,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) C_RCV_HDR_OVF_124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) C_RCV_HDR_OVF_125,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) C_RCV_HDR_OVF_126,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) C_RCV_HDR_OVF_127,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) C_RCV_HDR_OVF_128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) C_RCV_HDR_OVF_129,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) C_RCV_HDR_OVF_130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) C_RCV_HDR_OVF_131,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) C_RCV_HDR_OVF_132,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) C_RCV_HDR_OVF_133,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) C_RCV_HDR_OVF_134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) C_RCV_HDR_OVF_135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) C_RCV_HDR_OVF_136,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) C_RCV_HDR_OVF_137,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) C_RCV_HDR_OVF_138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) C_RCV_HDR_OVF_139,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) C_RCV_HDR_OVF_140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) C_RCV_HDR_OVF_141,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) C_RCV_HDR_OVF_142,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) C_RCV_HDR_OVF_143,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) C_RCV_HDR_OVF_144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) C_RCV_HDR_OVF_145,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) C_RCV_HDR_OVF_146,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) C_RCV_HDR_OVF_147,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) C_RCV_HDR_OVF_148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) C_RCV_HDR_OVF_149,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) C_RCV_HDR_OVF_150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) C_RCV_HDR_OVF_151,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) C_RCV_HDR_OVF_152,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) C_RCV_HDR_OVF_153,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) C_RCV_HDR_OVF_154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) C_RCV_HDR_OVF_155,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) C_RCV_HDR_OVF_156,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) C_RCV_HDR_OVF_157,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) C_RCV_HDR_OVF_158,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) C_RCV_HDR_OVF_159,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) PORT_CNTR_LAST /* Must be kept last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) u64 get_all_cpu_total(u64 __percpu *cntr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) void hfi1_start_cleanup(struct hfi1_devdata *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) void hfi1_clear_tids(struct hfi1_ctxtdata *rcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) void hfi1_init_ctxt(struct send_context *sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) void hfi1_put_tid(struct hfi1_devdata *dd, u32 index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) u32 type, unsigned long pa, u16 order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) void hfi1_quiet_serdes(struct hfi1_pportdata *ppd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) void hfi1_rcvctrl(struct hfi1_devdata *dd, unsigned int op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) struct hfi1_ctxtdata *rcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) u32 hfi1_read_cntrs(struct hfi1_devdata *dd, char **namep, u64 **cntrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) u32 hfi1_read_portcntrs(struct hfi1_pportdata *ppd, char **namep, u64 **cntrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) int hfi1_get_ib_cfg(struct hfi1_pportdata *ppd, int which);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) int hfi1_set_ib_cfg(struct hfi1_pportdata *ppd, int which, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) int hfi1_set_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) u16 jkey);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) int hfi1_clear_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *ctxt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) int hfi1_set_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *ctxt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) u16 pkey);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) int hfi1_clear_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *ctxt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) void hfi1_read_link_quality(struct hfi1_devdata *dd, u8 *link_quality);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) void hfi1_init_vnic_rsm(struct hfi1_devdata *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) void hfi1_deinit_vnic_rsm(struct hfi1_devdata *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) irqreturn_t general_interrupt(int irq, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) irqreturn_t sdma_interrupt(int irq, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) irqreturn_t receive_context_interrupt(int irq, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) irqreturn_t receive_context_thread(int irq, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) irqreturn_t receive_context_interrupt_napi(int irq, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) int set_intr_bits(struct hfi1_devdata *dd, u16 first, u16 last, bool set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) void init_qsfp_int(struct hfi1_devdata *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) void clear_all_interrupts(struct hfi1_devdata *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) void remap_intr(struct hfi1_devdata *dd, int isrc, int msix_intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) void remap_sdma_interrupts(struct hfi1_devdata *dd, int engine, int msix_intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) void reset_interrupts(struct hfi1_devdata *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) u8 hfi1_get_qp_map(struct hfi1_devdata *dd, u8 idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) void hfi1_init_aip_rsm(struct hfi1_devdata *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) void hfi1_deinit_aip_rsm(struct hfi1_devdata *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) * Interrupt source table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) * Each entry is an interrupt source "type". It is ordered by increasing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) * number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) struct is_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) int start; /* interrupt source type start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) int end; /* interrupt source type end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) /* routine that returns the name of the interrupt source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) char *(*is_name)(char *name, size_t size, unsigned int source);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) /* routine to call when receiving an interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) void (*is_int)(struct hfi1_devdata *dd, unsigned int source);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) #endif /* _CHIP_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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