^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This software is available to you under a choice of one of two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * licenses. You may choose to be licensed under the terms of the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * General Public License (GPL) Version 2, available from the file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * COPYING in the main directory of this source tree, or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * OpenIB.org BSD license below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Redistribution and use in source and binary forms, with or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * without modification, are permitted provided that the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * conditions are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * - Redistributions of source code must retain the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * copyright notice, this list of conditions and the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * - Redistributions in binary form must reproduce the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * copyright notice, this list of conditions and the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * disclaimer in the documentation and/or other materials
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * provided with the distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #ifndef __T4_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define __T4_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "t4_hw.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "t4_regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "t4_values.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "t4_msg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include "t4_tcb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "t4fw_ri_api.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define T4_MAX_NUM_PD 65536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define T4_MAX_MR_SIZE (~0ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define T4_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define T4_STAG_UNSET 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define T4_FW_MAJ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PCIE_MA_SYNC_A 0x30b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct t4_status_page {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) __be32 rsvd1; /* flit 0 - hw owns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) __be16 rsvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) __be16 qid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) __be16 cidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) __be16 pidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u8 qp_err; /* flit 1 - sw owns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u8 db_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u8 pad[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u16 host_wq_pidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u16 host_cidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u16 host_pidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u16 pad2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 srqidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define T4_RQT_ENTRY_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define T4_RQT_ENTRY_SIZE BIT(T4_RQT_ENTRY_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define T4_EQ_ENTRY_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define T4_SQ_NUM_SLOTS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) sizeof(struct fw_ri_immd)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) sizeof(struct fw_ri_rdma_write_wr) - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) sizeof(struct fw_ri_immd)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) sizeof(struct fw_ri_rdma_write_wr) - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) sizeof(struct fw_ri_immd)) & ~31UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define T4_MAX_FR_IMMD_DEPTH (T4_MAX_FR_IMMD / sizeof(u64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define T4_MAX_FR_DSGL 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define T4_MAX_FR_DSGL_DEPTH (T4_MAX_FR_DSGL / sizeof(u64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static inline int t4_max_fr_depth(int use_dsgl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return use_dsgl ? T4_MAX_FR_DSGL_DEPTH : T4_MAX_FR_IMMD_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define T4_RQ_NUM_SLOTS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define T4_MAX_RECV_SGE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define T4_WRITE_CMPL_MAX_SGL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define T4_WRITE_CMPL_MAX_CQE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) union t4_wr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct fw_ri_res_wr res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct fw_ri_wr ri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct fw_ri_rdma_write_wr write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct fw_ri_send_wr send;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct fw_ri_rdma_read_wr read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct fw_ri_bind_mw_wr bind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct fw_ri_fr_nsmr_wr fr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct fw_ri_fr_nsmr_tpte_wr fr_tpte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct fw_ri_inv_lstag_wr inv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct fw_ri_rdma_write_cmpl_wr write_cmpl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct t4_status_page status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) union t4_recv_wr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct fw_ri_recv_wr recv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct t4_status_page status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) enum fw_wr_opcodes opcode, u8 flags, u8 len16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) wqe->send.opcode = (u8)opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) wqe->send.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) wqe->send.wrid = wrid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) wqe->send.r1[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) wqe->send.r1[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) wqe->send.r1[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) wqe->send.len16 = len16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* CQE/AE status codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define T4_ERR_SUCCESS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define T4_ERR_STAG 0x1 /* STAG invalid: either the */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* STAG is offlimt, being 0, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* or STAG_key mismatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define T4_ERR_PDID 0x2 /* PDID mismatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define T4_ERR_QPID 0x3 /* QPID mismatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define T4_ERR_ACCESS 0x4 /* Invalid access right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define T4_ERR_WRAP 0x5 /* Wrap error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define T4_ERR_BOUND 0x6 /* base and bounds voilation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define T4_ERR_INVALIDATE_SHARED_MR 0x7 /* attempt to invalidate a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* shared memory region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8 /* attempt to invalidate a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* shared memory region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define T4_ERR_ECC 0x9 /* ECC error detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define T4_ERR_ECC_PSTAG 0xA /* ECC error detected when */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* reading PSTAG for a MW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Invalidate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define T4_ERR_PBL_ADDR_BOUND 0xB /* pbl addr out of bounds: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* software error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define T4_ERR_SWFLUSH 0xC /* SW FLUSHED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define T4_ERR_CRC 0x10 /* CRC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define T4_ERR_MARKER 0x11 /* Marker error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define T4_ERR_PDU_LEN_ERR 0x12 /* invalid PDU length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define T4_ERR_OUT_OF_RQE 0x13 /* out of RQE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define T4_ERR_DDP_VERSION 0x14 /* wrong DDP version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define T4_ERR_RDMA_VERSION 0x15 /* wrong RDMA version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define T4_ERR_OPCODE 0x16 /* invalid rdma opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define T4_ERR_DDP_QUEUE_NUM 0x17 /* invalid ddp queue number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define T4_ERR_MSN 0x18 /* MSN error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define T4_ERR_TBIT 0x19 /* tag bit not set correctly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define T4_ERR_MO 0x1A /* MO not 0 for TERMINATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* or READ_REQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define T4_ERR_MSN_GAP 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define T4_ERR_MSN_RANGE 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define T4_ERR_IRD_OVERFLOW 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define T4_ERR_RQE_ADDR_BOUND 0x1E /* RQE addr out of bounds: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* software error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define T4_ERR_INTERNAL_ERR 0x1F /* internal error (opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* mismatch) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * CQE defs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct t4_cqe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) __be32 header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) __be32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) __be32 stag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) __be32 msn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) } rcqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) __be32 stag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u16 nada2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u16 cidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) } scqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) __be32 wrid_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) __be32 wrid_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) } gen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) __be32 stag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) __be32 msn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) __be32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) __be32 abs_rqe_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) } srcqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) __be32 mo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) __be32 msn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * Use union for immediate data to be consistent with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * stack's 32 bit data and iWARP spec's 64 bit data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) __be32 imm_data32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) } ib_imm_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) __be64 imm_data64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) } iw_imm_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) } imm_data_rcqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u64 drain_cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) __be64 flits[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) __be64 reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) __be64 bits_type_ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* macros for flit 0 of the cqe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CQE_QPID_S 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CQE_QPID_M 0xFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CQE_QPID_G(x) ((((x) >> CQE_QPID_S)) & CQE_QPID_M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CQE_QPID_V(x) ((x)<<CQE_QPID_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CQE_SWCQE_S 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CQE_SWCQE_M 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CQE_SWCQE_G(x) ((((x) >> CQE_SWCQE_S)) & CQE_SWCQE_M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CQE_SWCQE_V(x) ((x)<<CQE_SWCQE_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CQE_DRAIN_S 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define CQE_DRAIN_M 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define CQE_DRAIN_G(x) ((((x) >> CQE_DRAIN_S)) & CQE_DRAIN_M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define CQE_DRAIN_V(x) ((x)<<CQE_DRAIN_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CQE_STATUS_S 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CQE_STATUS_M 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CQE_STATUS_G(x) ((((x) >> CQE_STATUS_S)) & CQE_STATUS_M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define CQE_STATUS_V(x) ((x)<<CQE_STATUS_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define CQE_TYPE_S 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define CQE_TYPE_M 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define CQE_TYPE_G(x) ((((x) >> CQE_TYPE_S)) & CQE_TYPE_M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define CQE_TYPE_V(x) ((x)<<CQE_TYPE_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define CQE_OPCODE_S 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define CQE_OPCODE_M 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define CQE_OPCODE_G(x) ((((x) >> CQE_OPCODE_S)) & CQE_OPCODE_M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define CQE_OPCODE_V(x) ((x)<<CQE_OPCODE_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SW_CQE(x) (CQE_SWCQE_G(be32_to_cpu((x)->header)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define DRAIN_CQE(x) (CQE_DRAIN_G(be32_to_cpu((x)->header)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define CQE_QPID(x) (CQE_QPID_G(be32_to_cpu((x)->header)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define CQE_TYPE(x) (CQE_TYPE_G(be32_to_cpu((x)->header)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SQ_TYPE(x) (CQE_TYPE((x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define RQ_TYPE(x) (!CQE_TYPE((x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define CQE_STATUS(x) (CQE_STATUS_G(be32_to_cpu((x)->header)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CQE_OPCODE(x) (CQE_OPCODE_G(be32_to_cpu((x)->header)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CQE_SEND_OPCODE(x)( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define CQE_LEN(x) (be32_to_cpu((x)->len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* used for RQ completion processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define CQE_ABS_RQE_IDX(x) (be32_to_cpu((x)->u.srcqe.abs_rqe_idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define CQE_IMM_DATA(x)( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) (x)->u.imm_data_rcqe.iw_imm_data.ib_imm_data.imm_data32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* used for SQ completion processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define CQE_WRID_FR_STAG(x) (be32_to_cpu((x)->u.scqe.stag))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* generic accessor macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define CQE_WRID_HI(x) (be32_to_cpu((x)->u.gen.wrid_hi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define CQE_WRID_LOW(x) (be32_to_cpu((x)->u.gen.wrid_low))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define CQE_DRAIN_COOKIE(x) ((x)->u.drain_cookie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* macros for flit 3 of the cqe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define CQE_GENBIT_S 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define CQE_GENBIT_M 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define CQE_GENBIT_G(x) (((x) >> CQE_GENBIT_S) & CQE_GENBIT_M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define CQE_GENBIT_V(x) ((x)<<CQE_GENBIT_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define CQE_OVFBIT_S 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define CQE_OVFBIT_M 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define CQE_OVFBIT_G(x) ((((x) >> CQE_OVFBIT_S)) & CQE_OVFBIT_M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define CQE_IQTYPE_S 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define CQE_IQTYPE_M 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define CQE_IQTYPE_G(x) ((((x) >> CQE_IQTYPE_S)) & CQE_IQTYPE_M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define CQE_TS_M 0x0fffffffffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define CQE_TS_G(x) ((x) & CQE_TS_M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define CQE_OVFBIT(x) ((unsigned)CQE_OVFBIT_G(be64_to_cpu((x)->bits_type_ts)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define CQE_GENBIT(x) ((unsigned)CQE_GENBIT_G(be64_to_cpu((x)->bits_type_ts)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define CQE_TS(x) (CQE_TS_G(be64_to_cpu((x)->bits_type_ts)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct t4_swsqe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u64 wr_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct t4_cqe cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int read_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int signaled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u16 idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int flushed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ktime_t host_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u64 sge_ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static inline pgprot_t t4_pgprot_wc(pgprot_t prot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return pgprot_writecombine(prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return pgprot_noncached(prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) T4_SQ_ONCHIP = (1<<0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct t4_sq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) union t4_wr *queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) DEFINE_DMA_UNMAP_ADDR(mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) unsigned long phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct t4_swsqe *sw_sq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct t4_swsqe *oldest_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) void __iomem *bar2_va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u64 bar2_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) size_t memsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u32 bar2_qid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u32 qid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u16 in_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u16 cidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u16 pidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u16 wq_pidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u16 wq_pidx_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) short flush_cidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct t4_swrqe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u64 wr_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ktime_t host_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u64 sge_ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct t4_rq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) union t4_recv_wr *queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) DEFINE_DMA_UNMAP_ADDR(mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct t4_swrqe *sw_rq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) void __iomem *bar2_va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u64 bar2_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) size_t memsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u32 bar2_qid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u32 qid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u32 msn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u32 rqt_hwaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u16 rqt_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u16 in_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u16 cidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u16 pidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u16 wq_pidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u16 wq_pidx_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct t4_wq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct t4_sq sq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct t4_rq rq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) void __iomem *db;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct c4iw_rdev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) int flushed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u8 *qp_errp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u32 *srqidxp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct t4_srq_pending_wr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u64 wr_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) union t4_recv_wr wqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u8 len16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct t4_srq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) union t4_recv_wr *queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) DEFINE_DMA_UNMAP_ADDR(mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct t4_swrqe *sw_rq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) void __iomem *bar2_va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u64 bar2_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) size_t memsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u32 bar2_qid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u32 qid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u32 msn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u32 rqt_hwaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 rqt_abs_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u16 rqt_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u16 cidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u16 pidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u16 wq_pidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) u16 wq_pidx_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u16 in_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct t4_srq_pending_wr *pending_wrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u16 pending_cidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u16 pending_pidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u16 pending_in_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u16 ooo_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static inline u32 t4_srq_avail(struct t4_srq *srq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return srq->size - 1 - srq->in_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static inline void t4_srq_produce(struct t4_srq *srq, u8 len16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) srq->in_use++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (++srq->pidx == srq->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) srq->pidx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) srq->wq_pidx += DIV_ROUND_UP(len16 * 16, T4_EQ_ENTRY_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (srq->wq_pidx >= srq->size * T4_RQ_NUM_SLOTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) srq->wq_pidx %= srq->size * T4_RQ_NUM_SLOTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) srq->queue[srq->size].status.host_pidx = srq->pidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static inline void t4_srq_produce_pending_wr(struct t4_srq *srq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) srq->pending_in_use++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) srq->in_use++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (++srq->pending_pidx == srq->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) srq->pending_pidx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static inline void t4_srq_consume_pending_wr(struct t4_srq *srq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) srq->pending_in_use--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) srq->in_use--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (++srq->pending_cidx == srq->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) srq->pending_cidx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static inline void t4_srq_produce_ooo(struct t4_srq *srq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) srq->in_use--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) srq->ooo_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static inline void t4_srq_consume_ooo(struct t4_srq *srq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) srq->cidx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (srq->cidx == srq->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) srq->cidx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) srq->queue[srq->size].status.host_cidx = srq->cidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) srq->ooo_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static inline void t4_srq_consume(struct t4_srq *srq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) srq->in_use--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (++srq->cidx == srq->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) srq->cidx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) srq->queue[srq->size].status.host_cidx = srq->cidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static inline int t4_rqes_posted(struct t4_wq *wq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return wq->rq.in_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static inline int t4_rq_empty(struct t4_wq *wq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return wq->rq.in_use == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static inline int t4_rq_full(struct t4_wq *wq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return wq->rq.in_use == (wq->rq.size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static inline u32 t4_rq_avail(struct t4_wq *wq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return wq->rq.size - 1 - wq->rq.in_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static inline void t4_rq_produce(struct t4_wq *wq, u8 len16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) wq->rq.in_use++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (++wq->rq.pidx == wq->rq.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) wq->rq.pidx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static inline void t4_rq_consume(struct t4_wq *wq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) wq->rq.in_use--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (++wq->rq.cidx == wq->rq.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) wq->rq.cidx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return wq->rq.queue[wq->rq.size].status.host_wq_pidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static inline u16 t4_rq_wq_size(struct t4_wq *wq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return wq->rq.size * T4_RQ_NUM_SLOTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static inline int t4_sq_onchip(struct t4_sq *sq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return sq->flags & T4_SQ_ONCHIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static inline int t4_sq_empty(struct t4_wq *wq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return wq->sq.in_use == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static inline int t4_sq_full(struct t4_wq *wq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return wq->sq.in_use == (wq->sq.size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static inline u32 t4_sq_avail(struct t4_wq *wq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return wq->sq.size - 1 - wq->sq.in_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static inline void t4_sq_produce(struct t4_wq *wq, u8 len16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) wq->sq.in_use++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (++wq->sq.pidx == wq->sq.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) wq->sq.pidx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static inline void t4_sq_consume(struct t4_wq *wq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (wq->sq.cidx == wq->sq.flush_cidx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) wq->sq.flush_cidx = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) wq->sq.in_use--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (++wq->sq.cidx == wq->sq.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) wq->sq.cidx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return wq->sq.queue[wq->sq.size].status.host_wq_pidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static inline u16 t4_sq_wq_size(struct t4_wq *wq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return wq->sq.size * T4_SQ_NUM_SLOTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* This function copies 64 byte coalesced work request to memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * mapped BAR2 space. For coalesced WRs, the SGE fetches data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * from the FIFO instead of from Host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static inline void pio_copy(u64 __iomem *dst, u64 *src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) int count = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) while (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) writeq(*src, dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) dst++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static inline void t4_ring_srq_db(struct t4_srq *srq, u16 inc, u8 len16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) union t4_recv_wr *wqe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* Flush host queue memory writes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (inc == 1 && srq->bar2_qid == 0 && wqe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) pr_debug("%s : WC srq->pidx = %d; len16=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) __func__, srq->pidx, len16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) pio_copy(srq->bar2_va + SGE_UDB_WCDOORBELL, (u64 *)wqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) pr_debug("%s: DB srq->pidx = %d; len16=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) __func__, srq->pidx, len16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) writel(PIDX_T5_V(inc) | QID_V(srq->bar2_qid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) srq->bar2_va + SGE_UDB_KDOORBELL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* Flush user doorbell area writes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, union t4_wr *wqe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* Flush host queue memory writes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (wq->sq.bar2_va) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (inc == 1 && wq->sq.bar2_qid == 0 && wqe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) pr_debug("WC wq->sq.pidx = %d\n", wq->sq.pidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) pio_copy((u64 __iomem *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) (wq->sq.bar2_va + SGE_UDB_WCDOORBELL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) (u64 *)wqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) pr_debug("DB wq->sq.pidx = %d\n", wq->sq.pidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) writel(PIDX_T5_V(inc) | QID_V(wq->sq.bar2_qid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) wq->sq.bar2_va + SGE_UDB_KDOORBELL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* Flush user doorbell area writes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) writel(QID_V(wq->sq.qid) | PIDX_V(inc), wq->db);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) union t4_recv_wr *wqe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* Flush host queue memory writes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (wq->rq.bar2_va) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (inc == 1 && wq->rq.bar2_qid == 0 && wqe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) pr_debug("WC wq->rq.pidx = %d\n", wq->rq.pidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) pio_copy((u64 __iomem *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) (wq->rq.bar2_va + SGE_UDB_WCDOORBELL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) (void *)wqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) pr_debug("DB wq->rq.pidx = %d\n", wq->rq.pidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) writel(PIDX_T5_V(inc) | QID_V(wq->rq.bar2_qid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) wq->rq.bar2_va + SGE_UDB_KDOORBELL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* Flush user doorbell area writes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) writel(QID_V(wq->rq.qid) | PIDX_V(inc), wq->db);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static inline int t4_wq_in_error(struct t4_wq *wq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return *wq->qp_errp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static inline void t4_set_wq_in_error(struct t4_wq *wq, u32 srqidx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (srqidx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) *wq->srqidxp = srqidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) *wq->qp_errp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static inline void t4_disable_wq_db(struct t4_wq *wq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) wq->rq.queue[wq->rq.size].status.db_off = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static inline void t4_enable_wq_db(struct t4_wq *wq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) wq->rq.queue[wq->rq.size].status.db_off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static inline int t4_wq_db_enabled(struct t4_wq *wq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return !wq->rq.queue[wq->rq.size].status.db_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) enum t4_cq_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) CQ_ARMED = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct t4_cq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct t4_cqe *queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) DEFINE_DMA_UNMAP_ADDR(mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct t4_cqe *sw_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) void __iomem *gts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) void __iomem *bar2_va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) u64 bar2_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) u32 bar2_qid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct c4iw_rdev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) size_t memsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) __be64 bits_type_ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) u32 cqid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) u32 qid_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) int vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) u16 size; /* including status page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) u16 cidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u16 sw_pidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) u16 sw_cidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) u16 sw_in_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) u16 cidx_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) u8 gen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) u8 error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) u8 *qp_errp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static inline void write_gts(struct t4_cq *cq, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (cq->bar2_va)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) writel(val | INGRESSQID_V(cq->bar2_qid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) cq->bar2_va + SGE_UDB_GTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) writel(val | INGRESSQID_V(cq->cqid), cq->gts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static inline int t4_clear_cq_armed(struct t4_cq *cq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return test_and_clear_bit(CQ_ARMED, &cq->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static inline int t4_arm_cq(struct t4_cq *cq, int se)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) set_bit(CQ_ARMED, &cq->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) while (cq->cidx_inc > CIDXINC_M) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) val = SEINTARM_V(0) | CIDXINC_V(CIDXINC_M) | TIMERREG_V(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) write_gts(cq, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) cq->cidx_inc -= CIDXINC_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) val = SEINTARM_V(se) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) write_gts(cq, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) cq->cidx_inc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static inline void t4_swcq_produce(struct t4_cq *cq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) cq->sw_in_use++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (cq->sw_in_use == cq->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) pr_warn("%s cxgb4 sw cq overflow cqid %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) __func__, cq->cqid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) cq->error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) cq->sw_in_use--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (++cq->sw_pidx == cq->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) cq->sw_pidx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static inline void t4_swcq_consume(struct t4_cq *cq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) cq->sw_in_use--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (++cq->sw_cidx == cq->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) cq->sw_cidx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static inline void t4_hwcq_consume(struct t4_cq *cq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == CIDXINC_M) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) val = SEINTARM_V(0) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) write_gts(cq, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) cq->cidx_inc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (++cq->cidx == cq->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) cq->cidx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) cq->gen ^= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return (CQE_GENBIT(cqe) == cq->gen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static inline int t4_cq_notempty(struct t4_cq *cq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return cq->sw_in_use || t4_valid_cqe(cq, &cq->queue[cq->cidx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) u16 prev_cidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (cq->cidx == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) prev_cidx = cq->size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) prev_cidx = cq->cidx - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ret = -EOVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) cq->error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) pr_err("cq overflow cqid %u\n", cq->cqid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) } else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* Ensure CQE is flushed to memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) *cqe = &cq->queue[cq->cidx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) ret = -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (cq->sw_in_use == cq->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) pr_warn("%s cxgb4 sw cq overflow cqid %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) __func__, cq->cqid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) cq->error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (cq->sw_in_use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return &cq->sw_queue[cq->sw_cidx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (cq->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) ret = -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) else if (cq->sw_in_use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) *cqe = &cq->sw_queue[cq->sw_cidx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) ret = t4_next_hw_cqe(cq, cqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static inline int t4_cq_in_error(struct t4_cq *cq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return *cq->qp_errp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static inline void t4_set_cq_in_error(struct t4_cq *cq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) *cq->qp_errp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) struct t4_dev_status_page {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) u8 db_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) u8 write_cmpl_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) u16 pad2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) u32 pad3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) u64 qp_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) u64 qp_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) u64 cq_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) u64 cq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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