^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This software is available to you under a choice of one of two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * licenses. You may choose to be licensed under the terms of the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * General Public License (GPL) Version 2, available from the file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * COPYING in the main directory of this source tree, or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * OpenIB.org BSD license below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Redistribution and use in source and binary forms, with or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * without modification, are permitted provided that the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * conditions are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * - Redistributions of source code must retain the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * copyright notice, this list of conditions and the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * - Redistributions in binary form must reproduce the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * copyright notice, this list of conditions and the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * disclaimer in the documentation and/or other materials
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * provided with the distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <rdma/ib_umem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <rdma/ib_user_verbs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "iw_cxgb4.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int use_dsgl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) module_param(use_dsgl, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MODULE_PARM_DESC(use_dsgl, "Use DSGL for PBL/FastReg (default=1) (DEPRECATED)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define T4_ULPTX_MIN_IO 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define C4IW_MAX_INLINE_SIZE 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define T4_ULPTX_MAX_DMA 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define C4IW_INLINE_THRESHOLD 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int inline_threshold = C4IW_INLINE_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) module_param(inline_threshold, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MODULE_PARM_DESC(inline_threshold, "inline vs dsgl threshold (default=128)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static int mr_exceeds_hw_limits(struct c4iw_dev *dev, u64 length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return (is_t4(dev->rdev.lldi.adapter_type) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) is_t5(dev->rdev.lldi.adapter_type)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) length >= 8*1024*1024*1024ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int _c4iw_write_mem_dma_aligned(struct c4iw_rdev *rdev, u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 len, dma_addr_t data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct c4iw_wr_wait *wr_waitp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct ulp_mem_io *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct ulptx_sgl *sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u8 wr_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) addr &= 0x7FFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (wr_waitp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) c4iw_init_wr_wait(wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) wr_len = roundup(sizeof(*req) + sizeof(*sgl), 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) skb = alloc_skb(wr_len, GFP_KERNEL | __GFP_NOFAIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (!skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) req = __skb_put_zero(skb, wr_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) INIT_ULPTX_WR(req, wr_len, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) (wr_waitp ? FW_WR_COMPL_F : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) req->wr.wr_lo = wr_waitp ? (__force __be64)(unsigned long)wr_waitp : 0L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) req->wr.wr_mid = cpu_to_be32(FW_WR_LEN16_V(DIV_ROUND_UP(wr_len, 16)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) req->cmd = cpu_to_be32(ULPTX_CMD_V(ULP_TX_MEM_WRITE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) T5_ULP_MEMIO_ORDER_V(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) T5_ULP_MEMIO_FID_V(rdev->lldi.rxq_ids[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN_V(len>>5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) req->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(req->wr), 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) req->lock_addr = cpu_to_be32(ULP_MEMIO_ADDR_V(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) sgl = (struct ulptx_sgl *)(req + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) sgl->cmd_nsge = cpu_to_be32(ULPTX_CMD_V(ULP_TX_SC_DSGL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ULPTX_NSGE_V(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) sgl->len0 = cpu_to_be32(len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) sgl->addr0 = cpu_to_be64(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (wr_waitp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ret = c4iw_ref_send_wait(rdev, skb, wr_waitp, 0, 0, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ret = c4iw_ofld_send(rdev, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int _c4iw_write_mem_inline(struct c4iw_rdev *rdev, u32 addr, u32 len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) void *data, struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct c4iw_wr_wait *wr_waitp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct ulp_mem_io *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct ulptx_idata *sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u8 wr_len, *to_dp, *from_dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int copy_len, num_wqe, i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) __be32 cmd = cpu_to_be32(ULPTX_CMD_V(ULP_TX_MEM_WRITE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (is_t4(rdev->lldi.adapter_type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) cmd |= cpu_to_be32(ULP_MEMIO_ORDER_F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) cmd |= cpu_to_be32(T5_ULP_MEMIO_IMM_F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) addr &= 0x7FFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) pr_debug("addr 0x%x len %u\n", addr, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) num_wqe = DIV_ROUND_UP(len, C4IW_MAX_INLINE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) c4iw_init_wr_wait(wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) for (i = 0; i < num_wqe; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) copy_len = len > C4IW_MAX_INLINE_SIZE ? C4IW_MAX_INLINE_SIZE :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) wr_len = roundup(sizeof(*req) + sizeof(*sc) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) roundup(copy_len, T4_ULPTX_MIN_IO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) skb = alloc_skb(wr_len, GFP_KERNEL | __GFP_NOFAIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (!skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) req = __skb_put_zero(skb, wr_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) INIT_ULPTX_WR(req, wr_len, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (i == (num_wqe-1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) FW_WR_COMPL_F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) req->wr.wr_lo = (__force __be64)(unsigned long)wr_waitp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) req->wr.wr_mid = cpu_to_be32(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) FW_WR_LEN16_V(DIV_ROUND_UP(wr_len, 16)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) req->cmd = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN_V(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) DIV_ROUND_UP(copy_len, T4_ULPTX_MIN_IO)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) req->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(req->wr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) req->lock_addr = cpu_to_be32(ULP_MEMIO_ADDR_V(addr + i * 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) sc = (struct ulptx_idata *)(req + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) sc->cmd_more = cpu_to_be32(ULPTX_CMD_V(ULP_TX_SC_IMM));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) sc->len = cpu_to_be32(roundup(copy_len, T4_ULPTX_MIN_IO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) to_dp = (u8 *)(sc + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) from_dp = (u8 *)data + i * C4IW_MAX_INLINE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) memcpy(to_dp, from_dp, copy_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) memset(to_dp, 0, copy_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (copy_len % T4_ULPTX_MIN_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) memset(to_dp + copy_len, 0, T4_ULPTX_MIN_IO -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) (copy_len % T4_ULPTX_MIN_IO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (i == (num_wqe-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ret = c4iw_ref_send_wait(rdev, skb, wr_waitp, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ret = c4iw_ofld_send(rdev, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) len -= C4IW_MAX_INLINE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int _c4iw_write_mem_dma(struct c4iw_rdev *rdev, u32 addr, u32 len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) void *data, struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct c4iw_wr_wait *wr_waitp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 remain = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 dmalen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dma_addr_t daddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dma_addr_t save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) daddr = dma_map_single(&rdev->lldi.pdev->dev, data, len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (dma_mapping_error(&rdev->lldi.pdev->dev, daddr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) save = daddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) while (remain > inline_threshold) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (remain < T4_ULPTX_MAX_DMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (remain & ~T4_ULPTX_MIN_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dmalen = remain & ~(T4_ULPTX_MIN_IO-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dmalen = remain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dmalen = T4_ULPTX_MAX_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) remain -= dmalen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ret = _c4iw_write_mem_dma_aligned(rdev, addr, dmalen, daddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) skb, remain ? NULL : wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) addr += dmalen >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) data += dmalen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) daddr += dmalen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (remain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ret = _c4iw_write_mem_inline(rdev, addr, remain, data, skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dma_unmap_single(&rdev->lldi.pdev->dev, save, len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * write len bytes of data into addr (32B aligned address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * If data is NULL, clear len byte of memory to zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int write_adapter_mem(struct c4iw_rdev *rdev, u32 addr, u32 len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) void *data, struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct c4iw_wr_wait *wr_waitp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (!rdev->lldi.ulptx_memwrite_dsgl || !use_dsgl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ret = _c4iw_write_mem_inline(rdev, addr, len, data, skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (len <= inline_threshold) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ret = _c4iw_write_mem_inline(rdev, addr, len, data, skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret = _c4iw_write_mem_dma(rdev, addr, len, data, skb, wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) pr_warn_ratelimited("%s: dma map failure (non fatal)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pci_name(rdev->lldi.pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ret = _c4iw_write_mem_inline(rdev, addr, len, data, skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * Build and write a TPT entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * IN: stag key, pdid, perm, bind_enabled, zbva, to, len, page_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * pbl_size and pbl_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * OUT: stag index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int write_tpt_entry(struct c4iw_rdev *rdev, u32 reset_tpt_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u32 *stag, u8 stag_state, u32 pdid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) enum fw_ri_stag_type type, enum fw_ri_mem_perms perm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int bind_enabled, u32 zbva, u64 to,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u64 len, u8 page_size, u32 pbl_size, u32 pbl_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct sk_buff *skb, struct c4iw_wr_wait *wr_waitp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct fw_ri_tpte *tpt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u32 stag_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static atomic_t key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (c4iw_fatal_error(rdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) tpt = kmalloc(sizeof(*tpt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (!tpt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) stag_state = stag_state > 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) stag_idx = (*stag) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if ((!reset_tpt_entry) && (*stag == T4_STAG_UNSET)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) stag_idx = c4iw_get_resource(&rdev->resource.tpt_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (!stag_idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) mutex_lock(&rdev->stats.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) rdev->stats.stag.fail++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) mutex_unlock(&rdev->stats.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) kfree(tpt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) mutex_lock(&rdev->stats.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) rdev->stats.stag.cur += 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (rdev->stats.stag.cur > rdev->stats.stag.max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) rdev->stats.stag.max = rdev->stats.stag.cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) mutex_unlock(&rdev->stats.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) *stag = (stag_idx << 8) | (atomic_inc_return(&key) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) pr_debug("stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) stag_state, type, pdid, stag_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* write TPT entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (reset_tpt_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) memset(tpt, 0, sizeof(*tpt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) tpt->valid_to_pdid = cpu_to_be32(FW_RI_TPTE_VALID_F |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) FW_RI_TPTE_STAGKEY_V((*stag & FW_RI_TPTE_STAGKEY_M)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) FW_RI_TPTE_STAGSTATE_V(stag_state) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) FW_RI_TPTE_STAGTYPE_V(type) | FW_RI_TPTE_PDID_V(pdid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) tpt->locread_to_qpid = cpu_to_be32(FW_RI_TPTE_PERM_V(perm) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) (bind_enabled ? FW_RI_TPTE_MWBINDEN_F : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) FW_RI_TPTE_ADDRTYPE_V((zbva ? FW_RI_ZERO_BASED_TO :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) FW_RI_VA_BASED_TO))|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) FW_RI_TPTE_PS_V(page_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) tpt->nosnoop_pbladdr = !pbl_size ? 0 : cpu_to_be32(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) FW_RI_TPTE_PBLADDR_V(PBL_OFF(rdev, pbl_addr)>>3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) tpt->len_lo = cpu_to_be32((u32)(len & 0xffffffffUL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) tpt->va_hi = cpu_to_be32((u32)(to >> 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) tpt->va_lo_fbo = cpu_to_be32((u32)(to & 0xffffffffUL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) tpt->dca_mwbcnt_pstag = cpu_to_be32(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) tpt->len_hi = cpu_to_be32((u32)(len >> 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) err = write_adapter_mem(rdev, stag_idx +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) (rdev->lldi.vr->stag.start >> 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) sizeof(*tpt), tpt, skb, wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (reset_tpt_entry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) c4iw_put_resource(&rdev->resource.tpt_table, stag_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) mutex_lock(&rdev->stats.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) rdev->stats.stag.cur -= 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) mutex_unlock(&rdev->stats.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) kfree(tpt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int write_pbl(struct c4iw_rdev *rdev, __be64 *pbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u32 pbl_addr, u32 pbl_size, struct c4iw_wr_wait *wr_waitp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) pr_debug("*pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pbl_addr, rdev->lldi.vr->pbl.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) pbl_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) err = write_adapter_mem(rdev, pbl_addr >> 5, pbl_size << 3, pbl, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int dereg_mem(struct c4iw_rdev *rdev, u32 stag, u32 pbl_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 pbl_addr, struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct c4iw_wr_wait *wr_waitp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) pbl_size, pbl_addr, skb, wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static int allocate_window(struct c4iw_rdev *rdev, u32 *stag, u32 pdid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct c4iw_wr_wait *wr_waitp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) *stag = T4_STAG_UNSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_MW, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 0UL, 0, 0, 0, 0, NULL, wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static int deallocate_window(struct c4iw_rdev *rdev, u32 stag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct c4iw_wr_wait *wr_waitp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 0, skb, wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int allocate_stag(struct c4iw_rdev *rdev, u32 *stag, u32 pdid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u32 pbl_size, u32 pbl_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct c4iw_wr_wait *wr_waitp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) *stag = T4_STAG_UNSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_NSMR, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 0UL, 0, 0, pbl_size, pbl_addr, NULL, wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static int finish_mem_reg(struct c4iw_mr *mhp, u32 stag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u32 mmid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) mhp->attr.state = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) mhp->attr.stag = stag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) mmid = stag >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) mhp->ibmr.rkey = mhp->ibmr.lkey = stag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) mhp->ibmr.length = mhp->attr.len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) mhp->ibmr.page_size = 1U << (mhp->attr.page_size + 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) pr_debug("mmid 0x%x mhp %p\n", mmid, mhp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return xa_insert_irq(&mhp->rhp->mrs, mmid, mhp, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int register_mem(struct c4iw_dev *rhp, struct c4iw_pd *php,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct c4iw_mr *mhp, int shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 stag = T4_STAG_UNSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, mhp->attr.pdid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) FW_RI_STAG_NSMR, mhp->attr.len ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) mhp->attr.perms : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) mhp->attr.mw_bind_enable, mhp->attr.zbva,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) mhp->attr.va_fbo, mhp->attr.len ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) mhp->attr.len : -1, shift - 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) mhp->attr.pbl_size, mhp->attr.pbl_addr, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) mhp->wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ret = finish_mem_reg(mhp, stag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) mhp->attr.pbl_addr, mhp->dereg_skb, mhp->wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) mhp->dereg_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static int alloc_pbl(struct c4iw_mr *mhp, int npages)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) mhp->attr.pbl_addr = c4iw_pblpool_alloc(&mhp->rhp->rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) npages << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (!mhp->attr.pbl_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) mhp->attr.pbl_size = npages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct c4iw_dev *rhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct c4iw_pd *php;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct c4iw_mr *mhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) u32 stag = T4_STAG_UNSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) pr_debug("ib_pd %p\n", pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) php = to_c4iw_pd(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) rhp = php->rhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (!mhp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) mhp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (!mhp->wr_waitp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) goto err_free_mhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) c4iw_init_wr_wait(mhp->wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (!mhp->dereg_skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) goto err_free_wr_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) mhp->rhp = rhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) mhp->attr.pdid = php->pdid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) mhp->attr.perms = c4iw_ib_to_tpt_access(acc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) mhp->attr.mw_bind_enable = (acc&IB_ACCESS_MW_BIND) == IB_ACCESS_MW_BIND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) mhp->attr.zbva = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) mhp->attr.va_fbo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) mhp->attr.page_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) mhp->attr.len = ~0ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) mhp->attr.pbl_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, php->pdid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) FW_RI_STAG_NSMR, mhp->attr.perms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) mhp->attr.mw_bind_enable, 0, 0, ~0ULL, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) NULL, mhp->wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) goto err_free_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ret = finish_mem_reg(mhp, stag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) goto err_dereg_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return &mhp->ibmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) err_dereg_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) mhp->attr.pbl_addr, mhp->dereg_skb, mhp->wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) err_free_skb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) kfree_skb(mhp->dereg_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) err_free_wr_wait:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) c4iw_put_wr_wait(mhp->wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) err_free_mhp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) kfree(mhp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) u64 virt, int acc, struct ib_udata *udata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) __be64 *pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) int shift, n, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) int err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct ib_block_iter biter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct c4iw_dev *rhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct c4iw_pd *php;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct c4iw_mr *mhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) pr_debug("ib_pd %p\n", pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (length == ~0ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if ((length + start) < start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) php = to_c4iw_pd(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) rhp = php->rhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (mr_exceeds_hw_limits(rhp, length))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (!mhp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) mhp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (!mhp->wr_waitp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) goto err_free_mhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (!mhp->dereg_skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) goto err_free_wr_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) mhp->rhp = rhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) mhp->umem = ib_umem_get(pd->device, start, length, acc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (IS_ERR(mhp->umem))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) goto err_free_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) shift = PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) n = ib_umem_num_dma_blocks(mhp->umem, 1 << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) err = alloc_pbl(mhp, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) goto err_umem_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) pages = (__be64 *) __get_free_page(GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (!pages) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) goto err_pbl_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) i = n = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) rdma_umem_for_each_dma_block(mhp->umem, &biter, 1 << shift) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) pages[i++] = cpu_to_be64(rdma_block_iter_dma_address(&biter));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (i == PAGE_SIZE / sizeof(*pages)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) err = write_pbl(&mhp->rhp->rdev, pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) mhp->attr.pbl_addr + (n << 3), i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) mhp->wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) goto pbl_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) n += i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) err = write_pbl(&mhp->rhp->rdev, pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) mhp->attr.pbl_addr + (n << 3), i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) mhp->wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) pbl_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) free_page((unsigned long) pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) goto err_pbl_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) mhp->attr.pdid = php->pdid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) mhp->attr.zbva = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) mhp->attr.perms = c4iw_ib_to_tpt_access(acc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) mhp->attr.va_fbo = virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) mhp->attr.page_size = shift - 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) mhp->attr.len = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) err = register_mem(rhp, php, mhp, shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) goto err_pbl_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return &mhp->ibmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) err_pbl_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) mhp->attr.pbl_size << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) err_umem_release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ib_umem_release(mhp->umem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) err_free_skb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) kfree_skb(mhp->dereg_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) err_free_wr_wait:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) c4iw_put_wr_wait(mhp->wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) err_free_mhp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) kfree(mhp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) int c4iw_alloc_mw(struct ib_mw *ibmw, struct ib_udata *udata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct c4iw_mw *mhp = to_c4iw_mw(ibmw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct c4iw_dev *rhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct c4iw_pd *php;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) u32 mmid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) u32 stag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (ibmw->type != IB_MW_TYPE_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) php = to_c4iw_pd(ibmw->pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) rhp = php->rhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) mhp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (!mhp->wr_waitp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (!mhp->dereg_skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) goto free_wr_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ret = allocate_window(&rhp->rdev, &stag, php->pdid, mhp->wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) goto free_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) mhp->rhp = rhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) mhp->attr.pdid = php->pdid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) mhp->attr.type = FW_RI_STAG_MW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) mhp->attr.stag = stag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) mmid = (stag) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ibmw->rkey = stag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (xa_insert_irq(&rhp->mrs, mmid, mhp, GFP_KERNEL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) goto dealloc_win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) pr_debug("mmid 0x%x mhp %p stag 0x%x\n", mmid, mhp, stag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) dealloc_win:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) deallocate_window(&rhp->rdev, mhp->attr.stag, mhp->dereg_skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) mhp->wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) free_skb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) kfree_skb(mhp->dereg_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) free_wr_wait:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) c4iw_put_wr_wait(mhp->wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) int c4iw_dealloc_mw(struct ib_mw *mw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct c4iw_dev *rhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct c4iw_mw *mhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) u32 mmid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) mhp = to_c4iw_mw(mw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) rhp = mhp->rhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) mmid = (mw->rkey) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) xa_erase_irq(&rhp->mrs, mmid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) deallocate_window(&rhp->rdev, mhp->attr.stag, mhp->dereg_skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) mhp->wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) kfree_skb(mhp->dereg_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) c4iw_put_wr_wait(mhp->wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) u32 max_num_sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct c4iw_dev *rhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct c4iw_pd *php;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) struct c4iw_mr *mhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) u32 mmid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) u32 stag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) int length = roundup(max_num_sg * sizeof(u64), 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) php = to_c4iw_pd(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) rhp = php->rhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (mr_type != IB_MR_TYPE_MEM_REG ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) max_num_sg > t4_max_fr_depth(rhp->rdev.lldi.ulptx_memwrite_dsgl &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) use_dsgl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (!mhp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) mhp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (!mhp->wr_waitp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) goto err_free_mhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) c4iw_init_wr_wait(mhp->wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) mhp->mpl = dma_alloc_coherent(&rhp->rdev.lldi.pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) length, &mhp->mpl_addr, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (!mhp->mpl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) goto err_free_wr_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) mhp->max_mpl_len = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) mhp->rhp = rhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) ret = alloc_pbl(mhp, max_num_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) goto err_free_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) mhp->attr.pbl_size = max_num_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ret = allocate_stag(&rhp->rdev, &stag, php->pdid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) mhp->attr.pbl_size, mhp->attr.pbl_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) mhp->wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) goto err_free_pbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) mhp->attr.pdid = php->pdid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) mhp->attr.type = FW_RI_STAG_NSMR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) mhp->attr.stag = stag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) mhp->attr.state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) mmid = (stag) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) mhp->ibmr.rkey = mhp->ibmr.lkey = stag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (xa_insert_irq(&rhp->mrs, mmid, mhp, GFP_KERNEL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) goto err_dereg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) pr_debug("mmid 0x%x mhp %p stag 0x%x\n", mmid, mhp, stag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return &(mhp->ibmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) err_dereg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) dereg_mem(&rhp->rdev, stag, mhp->attr.pbl_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) mhp->attr.pbl_addr, mhp->dereg_skb, mhp->wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) err_free_pbl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) mhp->attr.pbl_size << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) err_free_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) dma_free_coherent(&mhp->rhp->rdev.lldi.pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) mhp->max_mpl_len, mhp->mpl, mhp->mpl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) err_free_wr_wait:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) c4iw_put_wr_wait(mhp->wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) err_free_mhp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) kfree(mhp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static int c4iw_set_page(struct ib_mr *ibmr, u64 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct c4iw_mr *mhp = to_c4iw_mr(ibmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (unlikely(mhp->mpl_len == mhp->attr.pbl_size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) mhp->mpl[mhp->mpl_len++] = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) int c4iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) unsigned int *sg_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct c4iw_mr *mhp = to_c4iw_mr(ibmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) mhp->mpl_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, c4iw_set_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) int c4iw_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct c4iw_dev *rhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct c4iw_mr *mhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) u32 mmid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) pr_debug("ib_mr %p\n", ib_mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) mhp = to_c4iw_mr(ib_mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) rhp = mhp->rhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) mmid = mhp->attr.stag >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) xa_erase_irq(&rhp->mrs, mmid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (mhp->mpl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) dma_free_coherent(&mhp->rhp->rdev.lldi.pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) mhp->max_mpl_len, mhp->mpl, mhp->mpl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) mhp->attr.pbl_addr, mhp->dereg_skb, mhp->wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (mhp->attr.pbl_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) mhp->attr.pbl_size << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (mhp->kva)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) kfree((void *) (unsigned long) mhp->kva);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ib_umem_release(mhp->umem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) pr_debug("mmid 0x%x ptr %p\n", mmid, mhp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) c4iw_put_wr_wait(mhp->wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) kfree(mhp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) void c4iw_invalidate_mr(struct c4iw_dev *rhp, u32 rkey)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct c4iw_mr *mhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) xa_lock_irqsave(&rhp->mrs, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) mhp = xa_load(&rhp->mrs, rkey >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (mhp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) mhp->attr.state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) xa_unlock_irqrestore(&rhp->mrs, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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