^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This software is available to you under a choice of one of two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * licenses. You may choose to be licensed under the terms of the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * General Public License (GPL) Version 2, available from the file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * COPYING in the main directory of this source tree, or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * OpenIB.org BSD license below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Redistribution and use in source and binary forms, with or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * without modification, are permitted provided that the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * conditions are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * - Redistributions of source code must retain the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * copyright notice, this list of conditions and the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * - Redistributions in binary form must reproduce the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * copyright notice, this list of conditions and the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * disclaimer in the documentation and/or other materials
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * provided with the distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <rdma/uverbs_ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "iw_cxgb4.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static void destroy_cq(struct c4iw_rdev *rdev, struct t4_cq *cq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct c4iw_dev_ucontext *uctx, struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct c4iw_wr_wait *wr_waitp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct fw_ri_res_wr *res_wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct fw_ri_res *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int wr_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) wr_len = sizeof(*res_wr) + sizeof(*res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) res_wr = __skb_put_zero(skb, wr_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) res_wr->op_nres = cpu_to_be32(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) FW_WR_OP_V(FW_RI_RES_WR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) FW_RI_RES_WR_NRES_V(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) FW_WR_COMPL_F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) res_wr->cookie = (uintptr_t)wr_waitp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) res = res_wr->res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) res->u.cq.restype = FW_RI_RES_TYPE_CQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) res->u.cq.op = FW_RI_RES_OP_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) res->u.cq.iqid = cpu_to_be32(cq->cqid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) c4iw_init_wr_wait(wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) c4iw_ref_send_wait(rdev, skb, wr_waitp, 0, 0, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) kfree(cq->sw_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) dma_free_coherent(&(rdev->lldi.pdev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) cq->memsize, cq->queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) dma_unmap_addr(cq, mapping));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) c4iw_put_cqid(rdev, cq->cqid, uctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int create_cq(struct c4iw_rdev *rdev, struct t4_cq *cq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct c4iw_dev_ucontext *uctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct c4iw_wr_wait *wr_waitp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct fw_ri_res_wr *res_wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct fw_ri_res *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int wr_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int user = (uctx != &rdev->uctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct c4iw_ucontext *ucontext = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (user)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ucontext = container_of(uctx, struct c4iw_ucontext, uctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) cq->cqid = c4iw_get_cqid(rdev, uctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (!cq->cqid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (!user) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) cq->sw_queue = kzalloc(cq->memsize, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (!cq->sw_queue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) cq->queue = dma_alloc_coherent(&rdev->lldi.pdev->dev, cq->memsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) &cq->dma_addr, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (!cq->queue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) goto err3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) dma_unmap_addr_set(cq, mapping, cq->dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (user && ucontext->is_32b_cqe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) cq->qp_errp = &((struct t4_status_page *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ((u8 *)cq->queue + (cq->size - 1) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) (sizeof(*cq->queue) / 2)))->qp_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) cq->qp_errp = &((struct t4_status_page *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ((u8 *)cq->queue + (cq->size - 1) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) sizeof(*cq->queue)))->qp_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* build fw_ri_res_wr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) wr_len = sizeof(*res_wr) + sizeof(*res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) skb = alloc_skb(wr_len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) goto err4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) res_wr = __skb_put_zero(skb, wr_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) res_wr->op_nres = cpu_to_be32(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) FW_WR_OP_V(FW_RI_RES_WR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) FW_RI_RES_WR_NRES_V(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) FW_WR_COMPL_F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) res_wr->cookie = (uintptr_t)wr_waitp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) res = res_wr->res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) res->u.cq.restype = FW_RI_RES_TYPE_CQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) res->u.cq.op = FW_RI_RES_OP_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) res->u.cq.iqid = cpu_to_be32(cq->cqid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) res->u.cq.iqandst_to_iqandstindex = cpu_to_be32(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) FW_RI_RES_WR_IQANUS_V(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) FW_RI_RES_WR_IQANUD_V(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) FW_RI_RES_WR_IQANDST_F |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) FW_RI_RES_WR_IQANDSTINDEX_V(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) rdev->lldi.ciq_ids[cq->vector]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) res->u.cq.iqdroprss_to_iqesize = cpu_to_be16(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) FW_RI_RES_WR_IQDROPRSS_F |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) FW_RI_RES_WR_IQPCIECH_V(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) FW_RI_RES_WR_IQINTCNTTHRESH_V(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) FW_RI_RES_WR_IQO_F |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ((user && ucontext->is_32b_cqe) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) FW_RI_RES_WR_IQESIZE_V(1) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) FW_RI_RES_WR_IQESIZE_V(2)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) res->u.cq.iqsize = cpu_to_be16(cq->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) res->u.cq.iqaddr = cpu_to_be64(cq->dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) c4iw_init_wr_wait(wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ret = c4iw_ref_send_wait(rdev, skb, wr_waitp, 0, 0, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) goto err4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) cq->gen = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) cq->gts = rdev->lldi.gts_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) cq->rdev = rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) cq->bar2_va = c4iw_bar2_addrs(rdev, cq->cqid, CXGB4_BAR2_QTYPE_INGRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) &cq->bar2_qid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) user ? &cq->bar2_pa : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (user && !cq->bar2_pa) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) pr_warn("%s: cqid %u not in BAR2 range\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) pci_name(rdev->lldi.pdev), cq->cqid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) goto err4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) err4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dma_free_coherent(&rdev->lldi.pdev->dev, cq->memsize, cq->queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dma_unmap_addr(cq, mapping));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) err3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) kfree(cq->sw_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) c4iw_put_cqid(rdev, cq->cqid, uctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static void insert_recv_cqe(struct t4_wq *wq, struct t4_cq *cq, u32 srqidx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct t4_cqe cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) pr_debug("wq %p cq %p sw_cidx %u sw_pidx %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) wq, cq, cq->sw_cidx, cq->sw_pidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) memset(&cqe, 0, sizeof(cqe));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) cqe.header = cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) CQE_OPCODE_V(FW_RI_SEND) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) CQE_TYPE_V(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) CQE_SWCQE_V(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) CQE_QPID_V(wq->sq.qid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) cqe.bits_type_ts = cpu_to_be64(CQE_GENBIT_V((u64)cq->gen));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (srqidx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) cqe.u.srcqe.abs_rqe_idx = cpu_to_be32(srqidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) cq->sw_queue[cq->sw_pidx] = cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) t4_swcq_produce(cq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int flushed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int in_use = wq->rq.in_use - count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pr_debug("wq %p cq %p rq.in_use %u skip count %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) wq, cq, wq->rq.in_use, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) while (in_use--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) insert_recv_cqe(wq, cq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) flushed++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return flushed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static void insert_sq_cqe(struct t4_wq *wq, struct t4_cq *cq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct t4_swsqe *swcqe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct t4_cqe cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) pr_debug("wq %p cq %p sw_cidx %u sw_pidx %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) wq, cq, cq->sw_cidx, cq->sw_pidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) memset(&cqe, 0, sizeof(cqe));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) cqe.header = cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) CQE_OPCODE_V(swcqe->opcode) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) CQE_TYPE_V(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) CQE_SWCQE_V(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) CQE_QPID_V(wq->sq.qid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) CQE_WRID_SQ_IDX(&cqe) = swcqe->idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) cqe.bits_type_ts = cpu_to_be64(CQE_GENBIT_V((u64)cq->gen));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) cq->sw_queue[cq->sw_pidx] = cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) t4_swcq_produce(cq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static void advance_oldest_read(struct t4_wq *wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int c4iw_flush_sq(struct c4iw_qp *qhp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int flushed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct t4_wq *wq = &qhp->wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct c4iw_cq *chp = to_c4iw_cq(qhp->ibqp.send_cq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct t4_cq *cq = &chp->cq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct t4_swsqe *swsqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (wq->sq.flush_cidx == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) wq->sq.flush_cidx = wq->sq.cidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) idx = wq->sq.flush_cidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) while (idx != wq->sq.pidx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) swsqe = &wq->sq.sw_sq[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) swsqe->flushed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) insert_sq_cqe(wq, cq, swsqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (wq->sq.oldest_read == swsqe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) advance_oldest_read(wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) flushed++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (++idx == wq->sq.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) wq->sq.flush_cidx += flushed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (wq->sq.flush_cidx >= wq->sq.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) wq->sq.flush_cidx -= wq->sq.size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return flushed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static void flush_completed_wrs(struct t4_wq *wq, struct t4_cq *cq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct t4_swsqe *swsqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int cidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (wq->sq.flush_cidx == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) wq->sq.flush_cidx = wq->sq.cidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) cidx = wq->sq.flush_cidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) while (cidx != wq->sq.pidx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) swsqe = &wq->sq.sw_sq[cidx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (!swsqe->signaled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (++cidx == wq->sq.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) cidx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) } else if (swsqe->complete) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * Insert this completed cqe into the swcq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) pr_debug("moving cqe into swcq sq idx %u cq idx %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) cidx, cq->sw_pidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) swsqe->cqe.header |= htonl(CQE_SWCQE_V(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) cq->sw_queue[cq->sw_pidx] = swsqe->cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) t4_swcq_produce(cq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) swsqe->flushed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (++cidx == wq->sq.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) cidx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) wq->sq.flush_cidx = cidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static void create_read_req_cqe(struct t4_wq *wq, struct t4_cqe *hw_cqe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct t4_cqe *read_cqe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) read_cqe->u.scqe.cidx = wq->sq.oldest_read->idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) read_cqe->len = htonl(wq->sq.oldest_read->read_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) read_cqe->header = htonl(CQE_QPID_V(CQE_QPID(hw_cqe)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) CQE_SWCQE_V(SW_CQE(hw_cqe)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) CQE_OPCODE_V(FW_RI_READ_REQ) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) CQE_TYPE_V(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) read_cqe->bits_type_ts = hw_cqe->bits_type_ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static void advance_oldest_read(struct t4_wq *wq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u32 rptr = wq->sq.oldest_read - wq->sq.sw_sq + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (rptr == wq->sq.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) rptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) while (rptr != wq->sq.pidx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) wq->sq.oldest_read = &wq->sq.sw_sq[rptr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (wq->sq.oldest_read->opcode == FW_RI_READ_REQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (++rptr == wq->sq.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) rptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) wq->sq.oldest_read = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * Move all CQEs from the HWCQ into the SWCQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * Deal with out-of-order and/or completions that complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * prior unsignalled WRs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) void c4iw_flush_hw_cq(struct c4iw_cq *chp, struct c4iw_qp *flush_qhp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct t4_cqe *hw_cqe, *swcqe, read_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct c4iw_qp *qhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct t4_swsqe *swsqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) pr_debug("cqid 0x%x\n", chp->cq.cqid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ret = t4_next_hw_cqe(&chp->cq, &hw_cqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * This logic is similar to poll_cq(), but not quite the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * unfortunately. Need to move pertinent HW CQEs to the SW CQ but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * also do any translation magic that poll_cq() normally does.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) while (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) qhp = get_qhp(chp->rhp, CQE_QPID(hw_cqe));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * drop CQEs with no associated QP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (qhp == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) goto next_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (flush_qhp != qhp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) spin_lock(&qhp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (qhp->wq.flushed == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) goto next_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (CQE_OPCODE(hw_cqe) == FW_RI_TERMINATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) goto next_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (CQE_OPCODE(hw_cqe) == FW_RI_READ_RESP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* If we have reached here because of async
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * event or other error, and have egress error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * then drop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (CQE_TYPE(hw_cqe) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) goto next_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* drop peer2peer RTR reads.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (CQE_WRID_STAG(hw_cqe) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) goto next_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * Eat completions for unsignaled read WRs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (!qhp->wq.sq.oldest_read->signaled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) advance_oldest_read(&qhp->wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) goto next_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * Don't write to the HWCQ, create a new read req CQE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * in local memory and move it into the swcq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) create_read_req_cqe(&qhp->wq, hw_cqe, &read_cqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) hw_cqe = &read_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) advance_oldest_read(&qhp->wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* if its a SQ completion, then do the magic to move all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * unsignaled and now in-order completions into the swcq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (SQ_TYPE(hw_cqe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) swsqe = &qhp->wq.sq.sw_sq[CQE_WRID_SQ_IDX(hw_cqe)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) swsqe->cqe = *hw_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) swsqe->complete = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) flush_completed_wrs(&qhp->wq, &chp->cq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) swcqe = &chp->cq.sw_queue[chp->cq.sw_pidx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) *swcqe = *hw_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) swcqe->header |= cpu_to_be32(CQE_SWCQE_V(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) t4_swcq_produce(&chp->cq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) next_cqe:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) t4_hwcq_consume(&chp->cq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ret = t4_next_hw_cqe(&chp->cq, &hw_cqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (qhp && flush_qhp != qhp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) spin_unlock(&qhp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static int cqe_completes_wr(struct t4_cqe *cqe, struct t4_wq *wq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (DRAIN_CQE(cqe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) WARN_ONCE(1, "Unexpected DRAIN CQE qp id %u!\n", wq->sq.qid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (CQE_OPCODE(cqe) == FW_RI_TERMINATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if ((CQE_OPCODE(cqe) == FW_RI_RDMA_WRITE) && RQ_TYPE(cqe))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if ((CQE_OPCODE(cqe) == FW_RI_READ_RESP) && SQ_TYPE(cqe))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (CQE_SEND_OPCODE(cqe) && RQ_TYPE(cqe) && t4_rq_empty(wq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct t4_cqe *cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u32 ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) *count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) pr_debug("count zero %d\n", *count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ptr = cq->sw_cidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) while (ptr != cq->sw_pidx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) cqe = &cq->sw_queue[ptr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (RQ_TYPE(cqe) && (CQE_OPCODE(cqe) != FW_RI_READ_RESP) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) (CQE_QPID(cqe) == wq->sq.qid) && cqe_completes_wr(cqe, wq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) (*count)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (++ptr == cq->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) pr_debug("cq %p count %d\n", cq, *count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static void post_pending_srq_wrs(struct t4_srq *srq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct t4_srq_pending_wr *pwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) u16 idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) while (srq->pending_in_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) pwr = &srq->pending_wrs[srq->pending_cidx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) srq->sw_rq[srq->pidx].wr_id = pwr->wr_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) srq->sw_rq[srq->pidx].valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) pr_debug("%s posting pending cidx %u pidx %u wq_pidx %u in_use %u rq_size %u wr_id %llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) srq->cidx, srq->pidx, srq->wq_pidx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) srq->in_use, srq->size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) (unsigned long long)pwr->wr_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) c4iw_copy_wr_to_srq(srq, &pwr->wqe, pwr->len16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) t4_srq_consume_pending_wr(srq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) t4_srq_produce(srq, pwr->len16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) idx += DIV_ROUND_UP(pwr->len16 * 16, T4_EQ_ENTRY_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) t4_ring_srq_db(srq, idx, pwr->len16, &pwr->wqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) srq->queue[srq->size].status.host_wq_pidx =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) srq->wq_pidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static u64 reap_srq_cqe(struct t4_cqe *hw_cqe, struct t4_srq *srq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int rel_idx = CQE_ABS_RQE_IDX(hw_cqe) - srq->rqt_abs_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u64 wr_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) srq->sw_rq[rel_idx].valid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) wr_id = srq->sw_rq[rel_idx].wr_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (rel_idx == srq->cidx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pr_debug("%s in order cqe rel_idx %u cidx %u pidx %u wq_pidx %u in_use %u rq_size %u wr_id %llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) __func__, rel_idx, srq->cidx, srq->pidx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) srq->wq_pidx, srq->in_use, srq->size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) (unsigned long long)srq->sw_rq[rel_idx].wr_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) t4_srq_consume(srq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) while (srq->ooo_count && !srq->sw_rq[srq->cidx].valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) pr_debug("%s eat ooo cidx %u pidx %u wq_pidx %u in_use %u rq_size %u ooo_count %u wr_id %llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) __func__, srq->cidx, srq->pidx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) srq->wq_pidx, srq->in_use,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) srq->size, srq->ooo_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) (unsigned long long)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) srq->sw_rq[srq->cidx].wr_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) t4_srq_consume_ooo(srq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (srq->ooo_count == 0 && srq->pending_in_use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) post_pending_srq_wrs(srq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) pr_debug("%s ooo cqe rel_idx %u cidx %u pidx %u wq_pidx %u in_use %u rq_size %u ooo_count %u wr_id %llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) __func__, rel_idx, srq->cidx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) srq->pidx, srq->wq_pidx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) srq->in_use, srq->size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) srq->ooo_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) (unsigned long long)srq->sw_rq[rel_idx].wr_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) t4_srq_produce_ooo(srq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return wr_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * poll_cq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * Caller must:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * check the validity of the first CQE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * supply the wq assicated with the qpid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * credit: cq credit to return to sge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * cqe_flushed: 1 iff the CQE is flushed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * cqe: copy of the polled CQE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * return value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * 0 CQE returned ok.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * -EAGAIN CQE skipped, try again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * -EOVERFLOW CQ overflow detected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static int poll_cq(struct t4_wq *wq, struct t4_cq *cq, struct t4_cqe *cqe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u8 *cqe_flushed, u64 *cookie, u32 *credit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct t4_srq *srq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct t4_cqe *hw_cqe, read_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) *cqe_flushed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) *credit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ret = t4_next_cqe(cq, &hw_cqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) pr_debug("CQE OVF %u qpid 0x%0x genbit %u type %u status 0x%0x opcode 0x%0x len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) CQE_OVFBIT(hw_cqe), CQE_QPID(hw_cqe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) CQE_GENBIT(hw_cqe), CQE_TYPE(hw_cqe), CQE_STATUS(hw_cqe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) CQE_OPCODE(hw_cqe), CQE_LEN(hw_cqe), CQE_WRID_HI(hw_cqe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) CQE_WRID_LOW(hw_cqe));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * skip cqe's not affiliated with a QP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (wq == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) goto skip_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * skip hw cqe's if the wq is flushed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (wq->flushed && !SW_CQE(hw_cqe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) goto skip_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * skip TERMINATE cqes...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (CQE_OPCODE(hw_cqe) == FW_RI_TERMINATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) goto skip_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * Special cqe for drain WR completions...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (DRAIN_CQE(hw_cqe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) *cookie = CQE_DRAIN_COOKIE(hw_cqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) *cqe = *hw_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) goto skip_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * Gotta tweak READ completions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * 1) the cqe doesn't contain the sq_wptr from the wr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * 2) opcode not reflected from the wr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * 3) read_len not reflected from the wr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * 4) cq_type is RQ_TYPE not SQ_TYPE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (RQ_TYPE(hw_cqe) && (CQE_OPCODE(hw_cqe) == FW_RI_READ_RESP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* If we have reached here because of async
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * event or other error, and have egress error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * then drop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (CQE_TYPE(hw_cqe) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (CQE_STATUS(hw_cqe))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) t4_set_wq_in_error(wq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) goto skip_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* If this is an unsolicited read response, then the read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * was generated by the kernel driver as part of peer-2-peer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * connection setup. So ignore the completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (CQE_WRID_STAG(hw_cqe) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (CQE_STATUS(hw_cqe))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) t4_set_wq_in_error(wq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) goto skip_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * Eat completions for unsignaled read WRs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (!wq->sq.oldest_read->signaled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) advance_oldest_read(wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) goto skip_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * Don't write to the HWCQ, so create a new read req CQE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * in local memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) create_read_req_cqe(wq, hw_cqe, &read_cqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) hw_cqe = &read_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) advance_oldest_read(wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (CQE_STATUS(hw_cqe) || t4_wq_in_error(wq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) *cqe_flushed = (CQE_STATUS(hw_cqe) == T4_ERR_SWFLUSH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) t4_set_wq_in_error(wq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * RECV completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (RQ_TYPE(hw_cqe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * HW only validates 4 bits of MSN. So we must validate that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * the MSN in the SEND is the next expected MSN. If its not,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * then we complete this with T4_ERR_MSN and mark the wq in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (unlikely(!CQE_STATUS(hw_cqe) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) CQE_WRID_MSN(hw_cqe) != wq->rq.msn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) t4_set_wq_in_error(wq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) hw_cqe->header |= cpu_to_be32(CQE_STATUS_V(T4_ERR_MSN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) goto proc_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * If we get here its a send completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * Handle out of order completion. These get stuffed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * in the SW SQ. Then the SW SQ is walked to move any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * now in-order completions into the SW CQ. This handles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * 2 cases:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * 1) reaping unsignaled WRs when the first subsequent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * signaled WR is completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * 2) out of order read completions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (!SW_CQE(hw_cqe) && (CQE_WRID_SQ_IDX(hw_cqe) != wq->sq.cidx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct t4_swsqe *swsqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) pr_debug("out of order completion going in sw_sq at idx %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) CQE_WRID_SQ_IDX(hw_cqe));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) swsqe = &wq->sq.sw_sq[CQE_WRID_SQ_IDX(hw_cqe)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) swsqe->cqe = *hw_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) swsqe->complete = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) goto flush_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) proc_cqe:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) *cqe = *hw_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * Reap the associated WR(s) that are freed up with this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (SQ_TYPE(hw_cqe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) int idx = CQE_WRID_SQ_IDX(hw_cqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * Account for any unsignaled completions completed by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * this signaled completion. In this case, cidx points
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * to the first unsignaled one, and idx points to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * signaled one. So adjust in_use based on this delta.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * if this is not completing any unsigned wrs, then the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * delta will be 0. Handle wrapping also!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (idx < wq->sq.cidx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) wq->sq.in_use -= wq->sq.size + idx - wq->sq.cidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) wq->sq.in_use -= idx - wq->sq.cidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) wq->sq.cidx = (uint16_t)idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) pr_debug("completing sq idx %u\n", wq->sq.cidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) *cookie = wq->sq.sw_sq[wq->sq.cidx].wr_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (c4iw_wr_log)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) c4iw_log_wr_stats(wq, hw_cqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) t4_sq_consume(wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (!srq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) pr_debug("completing rq idx %u\n", wq->rq.cidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) *cookie = wq->rq.sw_rq[wq->rq.cidx].wr_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (c4iw_wr_log)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) c4iw_log_wr_stats(wq, hw_cqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) t4_rq_consume(wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) *cookie = reap_srq_cqe(hw_cqe, srq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) wq->rq.msn++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) goto skip_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) flush_wq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * Flush any completed cqes that are now in-order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) flush_completed_wrs(wq, cq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) skip_cqe:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (SW_CQE(hw_cqe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) pr_debug("cq %p cqid 0x%x skip sw cqe cidx %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) cq, cq->cqid, cq->sw_cidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) t4_swcq_consume(cq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) pr_debug("cq %p cqid 0x%x skip hw cqe cidx %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) cq, cq->cqid, cq->cidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) t4_hwcq_consume(cq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static int __c4iw_poll_cq_one(struct c4iw_cq *chp, struct c4iw_qp *qhp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct ib_wc *wc, struct c4iw_srq *srq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct t4_cqe cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct t4_wq *wq = qhp ? &qhp->wq : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) u32 credit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) u8 cqe_flushed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) u64 cookie = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) ret = poll_cq(wq, &(chp->cq), &cqe, &cqe_flushed, &cookie, &credit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) srq ? &srq->wq : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) wc->wr_id = cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) wc->qp = qhp ? &qhp->ibqp : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) wc->vendor_err = CQE_STATUS(&cqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) wc->wc_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * Simulate a SRQ_LIMIT_REACHED HW notification if required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (srq && !(srq->flags & T4_SRQ_LIMIT_SUPPORT) && srq->armed &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) srq->wq.in_use < srq->srq_limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) c4iw_dispatch_srq_limit_reached_event(srq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) pr_debug("qpid 0x%x type %d opcode %d status 0x%x len %u wrid hi 0x%x lo 0x%x cookie 0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) CQE_QPID(&cqe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) CQE_TYPE(&cqe), CQE_OPCODE(&cqe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) CQE_STATUS(&cqe), CQE_LEN(&cqe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) CQE_WRID_HI(&cqe), CQE_WRID_LOW(&cqe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) (unsigned long long)cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (CQE_TYPE(&cqe) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (!CQE_STATUS(&cqe))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) wc->byte_len = CQE_LEN(&cqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) wc->byte_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) switch (CQE_OPCODE(&cqe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) case FW_RI_SEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) wc->opcode = IB_WC_RECV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) case FW_RI_SEND_WITH_INV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) case FW_RI_SEND_WITH_SE_INV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) wc->opcode = IB_WC_RECV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) wc->ex.invalidate_rkey = CQE_WRID_STAG(&cqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) wc->wc_flags |= IB_WC_WITH_INVALIDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) c4iw_invalidate_mr(qhp->rhp, wc->ex.invalidate_rkey);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) case FW_RI_WRITE_IMMEDIATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) wc->ex.imm_data = CQE_IMM_DATA(&cqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) wc->wc_flags |= IB_WC_WITH_IMM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) pr_err("Unexpected opcode %d in the CQE received for QPID=0x%0x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) CQE_OPCODE(&cqe), CQE_QPID(&cqe));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) switch (CQE_OPCODE(&cqe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) case FW_RI_WRITE_IMMEDIATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) case FW_RI_RDMA_WRITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) wc->opcode = IB_WC_RDMA_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) case FW_RI_READ_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) wc->opcode = IB_WC_RDMA_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) wc->byte_len = CQE_LEN(&cqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) case FW_RI_SEND_WITH_INV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) case FW_RI_SEND_WITH_SE_INV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) wc->opcode = IB_WC_SEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) wc->wc_flags |= IB_WC_WITH_INVALIDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) case FW_RI_SEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) case FW_RI_SEND_WITH_SE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) wc->opcode = IB_WC_SEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) case FW_RI_LOCAL_INV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) wc->opcode = IB_WC_LOCAL_INV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) case FW_RI_FAST_REGISTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) wc->opcode = IB_WC_REG_MR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /* Invalidate the MR if the fastreg failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (CQE_STATUS(&cqe) != T4_ERR_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) c4iw_invalidate_mr(qhp->rhp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) CQE_WRID_FR_STAG(&cqe));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) pr_err("Unexpected opcode %d in the CQE received for QPID=0x%0x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) CQE_OPCODE(&cqe), CQE_QPID(&cqe));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (cqe_flushed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) wc->status = IB_WC_WR_FLUSH_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) switch (CQE_STATUS(&cqe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) case T4_ERR_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) wc->status = IB_WC_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) case T4_ERR_STAG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) wc->status = IB_WC_LOC_ACCESS_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) case T4_ERR_PDID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) wc->status = IB_WC_LOC_PROT_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) case T4_ERR_QPID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) case T4_ERR_ACCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) wc->status = IB_WC_LOC_ACCESS_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) case T4_ERR_WRAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) wc->status = IB_WC_GENERAL_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) case T4_ERR_BOUND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) wc->status = IB_WC_LOC_LEN_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) case T4_ERR_INVALIDATE_SHARED_MR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) wc->status = IB_WC_MW_BIND_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) case T4_ERR_CRC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) case T4_ERR_MARKER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) case T4_ERR_PDU_LEN_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) case T4_ERR_OUT_OF_RQE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) case T4_ERR_DDP_VERSION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) case T4_ERR_RDMA_VERSION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) case T4_ERR_DDP_QUEUE_NUM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) case T4_ERR_MSN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) case T4_ERR_TBIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) case T4_ERR_MO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) case T4_ERR_MSN_RANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) case T4_ERR_IRD_OVERFLOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) case T4_ERR_OPCODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) case T4_ERR_INTERNAL_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) wc->status = IB_WC_FATAL_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) case T4_ERR_SWFLUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) wc->status = IB_WC_WR_FLUSH_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) pr_err("Unexpected cqe_status 0x%x for QPID=0x%0x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) CQE_STATUS(&cqe), CQE_QPID(&cqe));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) wc->status = IB_WC_FATAL_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * Get one cq entry from c4iw and map it to openib.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) * 0 cqe returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * -ENODATA EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) * -EAGAIN caller must try again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * any other -errno fatal error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static int c4iw_poll_cq_one(struct c4iw_cq *chp, struct ib_wc *wc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) struct c4iw_srq *srq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct c4iw_qp *qhp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct t4_cqe *rd_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) ret = t4_next_cqe(&chp->cq, &rd_cqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) qhp = get_qhp(chp->rhp, CQE_QPID(rd_cqe));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (qhp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) spin_lock(&qhp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) srq = qhp->srq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (srq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) spin_lock(&srq->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) ret = __c4iw_poll_cq_one(chp, qhp, wc, srq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) spin_unlock(&qhp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (srq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) spin_unlock(&srq->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) ret = __c4iw_poll_cq_one(chp, NULL, wc, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct c4iw_cq *chp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) int npolled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) chp = to_c4iw_cq(ibcq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) spin_lock_irqsave(&chp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) for (npolled = 0; npolled < num_entries; ++npolled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) err = c4iw_poll_cq_one(chp, wc + npolled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) } while (err == -EAGAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) spin_unlock_irqrestore(&chp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return !err || err == -ENODATA ? npolled : err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) int c4iw_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) struct c4iw_cq *chp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct c4iw_ucontext *ucontext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) pr_debug("ib_cq %p\n", ib_cq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) chp = to_c4iw_cq(ib_cq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) xa_erase_irq(&chp->rhp->cqs, chp->cq.cqid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) atomic_dec(&chp->refcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) wait_event(chp->wait, !atomic_read(&chp->refcnt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) ucontext = rdma_udata_to_drv_context(udata, struct c4iw_ucontext,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) ibucontext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) destroy_cq(&chp->rhp->rdev, &chp->cq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) ucontext ? &ucontext->uctx : &chp->cq.rdev->uctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) chp->destroy_skb, chp->wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) c4iw_put_wr_wait(chp->wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) int c4iw_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) struct ib_udata *udata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) struct ib_device *ibdev = ibcq->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) int entries = attr->cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) int vector = attr->comp_vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct c4iw_dev *rhp = to_c4iw_dev(ibcq->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct c4iw_cq *chp = to_c4iw_cq(ibcq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct c4iw_create_cq ucmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct c4iw_create_cq_resp uresp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) int ret, wr_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) size_t memsize, hwentries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) struct c4iw_mm_entry *mm, *mm2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct c4iw_ucontext *ucontext = rdma_udata_to_drv_context(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) udata, struct c4iw_ucontext, ibucontext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) pr_debug("ib_dev %p entries %d\n", ibdev, entries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (attr->flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (entries < 1 || entries > ibdev->attrs.max_cqe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (vector >= rhp->rdev.lldi.nciq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (udata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (udata->inlen < sizeof(ucmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) ucontext->is_32b_cqe = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) chp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (!chp->wr_waitp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) goto err_free_chp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) c4iw_init_wr_wait(chp->wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) wr_len = sizeof(struct fw_ri_res_wr) + sizeof(struct fw_ri_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) chp->destroy_skb = alloc_skb(wr_len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (!chp->destroy_skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) goto err_free_wr_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* account for the status page. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) entries++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) /* IQ needs one extra entry to differentiate full vs empty. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) entries++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * entries must be multiple of 16 for HW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) entries = roundup(entries, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) * Make actual HW queue 2x to avoid cdix_inc overflows.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) hwentries = min(entries * 2, rhp->rdev.hw_queue.t4_max_iq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) * Make HW queue at least 64 entries so GTS updates aren't too
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) * frequent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (hwentries < 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) hwentries = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) memsize = hwentries * ((ucontext && ucontext->is_32b_cqe) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) (sizeof(*chp->cq.queue) / 2) : sizeof(*chp->cq.queue));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * memsize must be a multiple of the page size if its a user cq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (udata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) memsize = roundup(memsize, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) chp->cq.size = hwentries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) chp->cq.memsize = memsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) chp->cq.vector = vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) ret = create_cq(&rhp->rdev, &chp->cq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) ucontext ? &ucontext->uctx : &rhp->rdev.uctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) chp->wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) goto err_free_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) chp->rhp = rhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) chp->cq.size--; /* status page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) chp->ibcq.cqe = entries - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) spin_lock_init(&chp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) spin_lock_init(&chp->comp_handler_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) atomic_set(&chp->refcnt, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) init_waitqueue_head(&chp->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ret = xa_insert_irq(&rhp->cqs, chp->cq.cqid, chp, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) goto err_destroy_cq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (ucontext) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) mm = kmalloc(sizeof(*mm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (!mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) goto err_remove_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) mm2 = kmalloc(sizeof(*mm2), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (!mm2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) goto err_free_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) memset(&uresp, 0, sizeof(uresp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) uresp.qid_mask = rhp->rdev.cqmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) uresp.cqid = chp->cq.cqid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) uresp.size = chp->cq.size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) uresp.memsize = chp->cq.memsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) spin_lock(&ucontext->mmap_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) uresp.key = ucontext->key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) ucontext->key += PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) uresp.gts_key = ucontext->key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) ucontext->key += PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /* communicate to the userspace that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * kernel driver supports 64B CQE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) uresp.flags |= C4IW_64B_CQE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) spin_unlock(&ucontext->mmap_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) ret = ib_copy_to_udata(udata, &uresp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) ucontext->is_32b_cqe ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) sizeof(uresp) - sizeof(uresp.flags) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) sizeof(uresp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) goto err_free_mm2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) mm->key = uresp.key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) mm->addr = virt_to_phys(chp->cq.queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) mm->len = chp->cq.memsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) insert_mmap(ucontext, mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) mm2->key = uresp.gts_key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) mm2->addr = chp->cq.bar2_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) mm2->len = PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) insert_mmap(ucontext, mm2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) pr_debug("cqid 0x%0x chp %p size %u memsize %zu, dma_addr %pad\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) chp->cq.cqid, chp, chp->cq.size, chp->cq.memsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) &chp->cq.dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) err_free_mm2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) kfree(mm2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) err_free_mm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) kfree(mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) err_remove_handle:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) xa_erase_irq(&rhp->cqs, chp->cq.cqid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) err_destroy_cq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) destroy_cq(&chp->rhp->rdev, &chp->cq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) ucontext ? &ucontext->uctx : &rhp->rdev.uctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) chp->destroy_skb, chp->wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) err_free_skb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) kfree_skb(chp->destroy_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) err_free_wr_wait:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) c4iw_put_wr_wait(chp->wr_waitp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) err_free_chp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) struct c4iw_cq *chp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) unsigned long flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) chp = to_c4iw_cq(ibcq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) spin_lock_irqsave(&chp->lock, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) t4_arm_cq(&chp->cq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (flags & IB_CQ_REPORT_MISSED_EVENTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) ret = t4_cq_notempty(&chp->cq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) spin_unlock_irqrestore(&chp->lock, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) void c4iw_flush_srqidx(struct c4iw_qp *qhp, u32 srqidx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) struct c4iw_cq *rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) unsigned long flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) /* locking heirarchy: cq lock first, then qp lock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) spin_lock_irqsave(&rchp->lock, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) spin_lock(&qhp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) /* create a SRQ RECV CQE for srqidx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) insert_recv_cqe(&qhp->wq, &rchp->cq, srqidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) spin_unlock(&qhp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) spin_unlock_irqrestore(&rchp->lock, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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