^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) STMicroelectronics 2016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iio/timer/stm32-timer-trigger.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/iio/trigger.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mfd/stm32-timers.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MAX_TRIGGERS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MAX_VALIDS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* List the triggers created by each timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static const void *triggers_table[][MAX_TRIGGERS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) { TIM1_TRGO, TIM1_TRGO2, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) { TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) { TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) { TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { TIM6_TRGO,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { TIM7_TRGO,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { TIM8_TRGO, TIM8_TRGO2, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { TIM9_TRGO, TIM9_CH1, TIM9_CH2,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) { TIM10_OC1,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) { TIM11_OC1,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { TIM12_TRGO, TIM12_CH1, TIM12_CH2,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { TIM13_OC1,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { TIM14_OC1,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { TIM15_TRGO,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { TIM16_OC1,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { TIM17_OC1,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* List the triggers accepted by each timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static const void *valids_table[][MAX_VALIDS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { TIM5_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { TIM1_TRGO, TIM2_TRGO, TIM5_TRGO, TIM4_TRGO,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { TIM2_TRGO, TIM3_TRGO, TIM4_TRGO, TIM8_TRGO,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { }, /* timer 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { }, /* timer 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { TIM2_TRGO, TIM3_TRGO, TIM10_OC1, TIM11_OC1,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { }, /* timer 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { }, /* timer 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static const void *stm32h7_valids_table[][MAX_VALIDS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { TIM15_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { TIM1_TRGO, TIM2_TRGO, TIM15_TRGO, TIM4_TRGO,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { }, /* timer 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { }, /* timer 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { }, /* timer 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { }, /* timer 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { }, /* timer 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { }, /* timer 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { }, /* timer 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { TIM1_TRGO, TIM3_TRGO, TIM16_OC1, TIM17_OC1,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { }, /* timer 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { }, /* timer 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct stm32_timer_trigger_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 cr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 cr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 psc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 arr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 smcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct stm32_timer_trigger {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 max_arr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) const void *triggers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) const void *valids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) bool has_trgo2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct mutex lock; /* concurrent sysfs configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct list_head tr_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct stm32_timer_trigger_regs bak;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct stm32_timer_trigger_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) const void *(*valids_table)[MAX_VALIDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) const unsigned int num_valids_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static bool stm32_timer_is_trgo2_name(const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return !!strstr(name, "trgo2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static bool stm32_timer_is_trgo_name(const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return (!!strstr(name, "trgo") && !strstr(name, "trgo2"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int stm32_timer_start(struct stm32_timer_trigger *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct iio_trigger *trig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned long long prd, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int prescaler = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 ccer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Period and prescaler values depends of clock rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) div = (unsigned long long)clk_get_rate(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) do_div(div, frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) prd = div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * Increase prescaler value until we get a result that fit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * with auto reload register maximum value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) while (div > priv->max_arr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) prescaler++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) div = prd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) do_div(div, (prescaler + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) prd = div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (prescaler > MAX_TIM_PSC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dev_err(priv->dev, "prescaler exceeds the maximum value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Check if nobody else use the timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) regmap_read(priv->regmap, TIM_CCER, &ccer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (ccer & TIM_CCER_CCXE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (!priv->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) priv->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) clk_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) regmap_write(priv->regmap, TIM_PSC, prescaler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) regmap_write(priv->regmap, TIM_ARR, prd - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Force master mode to update mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (stm32_timer_is_trgo2_name(trig->name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 0x2 << TIM_CR2_MMS2_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 0x2 << TIM_CR2_MMS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Make sure that registers are updated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Enable controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static void stm32_timer_stop(struct stm32_timer_trigger *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct iio_trigger *trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u32 ccer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) regmap_read(priv->regmap, TIM_CCER, &ccer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (ccer & TIM_CCER_CCXE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Stop timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) regmap_write(priv->regmap, TIM_PSC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) regmap_write(priv->regmap, TIM_ARR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Force disable master mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (stm32_timer_is_trgo2_name(trig->name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Make sure that registers are updated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (priv->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) priv->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) clk_disable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static ssize_t stm32_tt_store_frequency(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) const char *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct iio_trigger *trig = to_iio_trigger(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned int freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = kstrtouint(buf, 10, &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (freq == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) stm32_timer_stop(priv, trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ret = stm32_timer_start(priv, trig, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static ssize_t stm32_tt_read_frequency(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct iio_trigger *trig = to_iio_trigger(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u32 psc, arr, cr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned long long freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) regmap_read(priv->regmap, TIM_CR1, &cr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) regmap_read(priv->regmap, TIM_PSC, &psc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) regmap_read(priv->regmap, TIM_ARR, &arr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (cr1 & TIM_CR1_CEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) freq = (unsigned long long)clk_get_rate(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) do_div(freq, psc + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) do_div(freq, arr + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return sprintf(buf, "%d\n", (unsigned int)freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static IIO_DEV_ATTR_SAMP_FREQ(0660,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) stm32_tt_read_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) stm32_tt_store_frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define MASTER_MODE_MAX 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define MASTER_MODE2_MAX 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static char *master_mode_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) "reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) "enable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) "update",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) "compare_pulse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "OC1REF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "OC2REF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) "OC3REF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) "OC4REF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Master mode selection 2 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "OC5REF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) "OC6REF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) "compare_pulse_OC4REF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) "compare_pulse_OC6REF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) "compare_pulse_OC4REF_r_or_OC6REF_r",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) "compare_pulse_OC4REF_r_or_OC6REF_f",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) "compare_pulse_OC5REF_r_or_OC6REF_r",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) "compare_pulse_OC5REF_r_or_OC6REF_f",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static ssize_t stm32_tt_show_master_mode(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct iio_trigger *trig = to_iio_trigger(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u32 cr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) regmap_read(priv->regmap, TIM_CR2, &cr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (stm32_timer_is_trgo2_name(trig->name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) cr2 = (cr2 & TIM_CR2_MMS2) >> TIM_CR2_MMS2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return snprintf(buf, PAGE_SIZE, "%s\n", master_mode_table[cr2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static ssize_t stm32_tt_store_master_mode(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) const char *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct iio_trigger *trig = to_iio_trigger(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 mask, shift, master_mode_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (stm32_timer_is_trgo2_name(trig->name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) mask = TIM_CR2_MMS2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) shift = TIM_CR2_MMS2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) master_mode_max = MASTER_MODE2_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) mask = TIM_CR2_MMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) shift = TIM_CR2_MMS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) master_mode_max = MASTER_MODE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) for (i = 0; i <= master_mode_max; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (!strncmp(master_mode_table[i], buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) strlen(master_mode_table[i]))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (!priv->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Clock should be enabled first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) priv->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) clk_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) regmap_update_bits(priv->regmap, TIM_CR2, mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) i << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static ssize_t stm32_tt_show_master_mode_avail(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct iio_trigger *trig = to_iio_trigger(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned int i, master_mode_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) size_t len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (stm32_timer_is_trgo2_name(trig->name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) master_mode_max = MASTER_MODE2_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) master_mode_max = MASTER_MODE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) for (i = 0; i <= master_mode_max; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) len += scnprintf(buf + len, PAGE_SIZE - len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) "%s ", master_mode_table[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* replace trailing space by newline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) buf[len - 1] = '\n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static IIO_DEVICE_ATTR(master_mode_available, 0444,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) stm32_tt_show_master_mode_avail, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static IIO_DEVICE_ATTR(master_mode, 0660,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) stm32_tt_show_master_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) stm32_tt_store_master_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static struct attribute *stm32_trigger_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) &iio_dev_attr_sampling_frequency.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) &iio_dev_attr_master_mode.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) &iio_dev_attr_master_mode_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static const struct attribute_group stm32_trigger_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .attrs = stm32_trigger_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static const struct attribute_group *stm32_trigger_attr_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) &stm32_trigger_attr_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const struct iio_trigger_ops timer_trigger_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static void stm32_unregister_iio_triggers(struct stm32_timer_trigger *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct iio_trigger *tr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) list_for_each_entry(tr, &priv->tr_list, alloc_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) iio_trigger_unregister(tr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int stm32_register_iio_triggers(struct stm32_timer_trigger *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) const char * const *cur = priv->triggers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) INIT_LIST_HEAD(&priv->tr_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) while (cur && *cur) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct iio_trigger *trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) bool cur_is_trgo = stm32_timer_is_trgo_name(*cur);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) bool cur_is_trgo2 = stm32_timer_is_trgo2_name(*cur);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (cur_is_trgo2 && !priv->has_trgo2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) cur++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (!trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) trig->dev.parent = priv->dev->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) trig->ops = &timer_trigger_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * sampling frequency and master mode attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * should only be available on trgo/trgo2 triggers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (cur_is_trgo || cur_is_trgo2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) trig->dev.groups = stm32_trigger_attr_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) iio_trigger_set_drvdata(trig, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ret = iio_trigger_register(trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) stm32_unregister_iio_triggers(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) list_add_tail(&trig->alloc_list, &priv->tr_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) cur++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static int stm32_counter_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct stm32_timer_trigger *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u32 dat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) regmap_read(priv->regmap, TIM_CNT, &dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) *val = dat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) case IIO_CHAN_INFO_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) regmap_read(priv->regmap, TIM_CR1, &dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) *val = (dat & TIM_CR1_CEN) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) regmap_read(priv->regmap, TIM_SMCR, &dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dat &= TIM_SMCR_SMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) *val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) *val2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* in quadrature case scale = 0.25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (dat == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) *val2 = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static int stm32_counter_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct stm32_timer_trigger *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return regmap_write(priv->regmap, TIM_CNT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* fixed scale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) case IIO_CHAN_INFO_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (!priv->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) priv->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) clk_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) TIM_CR1_CEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (priv->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) priv->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) clk_disable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static int stm32_counter_validate_trigger(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct iio_trigger *trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct stm32_timer_trigger *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) const char * const *cur = priv->valids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) unsigned int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (!is_stm32_timer_trigger(trig))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) while (cur && *cur) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (!strncmp(trig->name, *cur, strlen(trig->name))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) regmap_update_bits(priv->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) TIM_SMCR, TIM_SMCR_TS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) i << TIM_SMCR_TS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) cur++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static const struct iio_info stm32_trigger_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .validate_trigger = stm32_counter_validate_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .read_raw = stm32_counter_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .write_raw = stm32_counter_write_raw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static const char *const stm32_trigger_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) "trigger",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static int stm32_set_trigger_mode(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct stm32_timer_trigger *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, TIM_SMCR_SMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static int stm32_get_trigger_mode(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) const struct iio_chan_spec *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct stm32_timer_trigger *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) u32 smcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) regmap_read(priv->regmap, TIM_SMCR, &smcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return (smcr & TIM_SMCR_SMS) == TIM_SMCR_SMS ? 0 : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static const struct iio_enum stm32_trigger_mode_enum = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .items = stm32_trigger_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .num_items = ARRAY_SIZE(stm32_trigger_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .set = stm32_set_trigger_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .get = stm32_get_trigger_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static const char *const stm32_enable_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) "always",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) "gated",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) "triggered",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static int stm32_enable_mode2sms(int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static int stm32_set_enable_mode(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct stm32_timer_trigger *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) int sms = stm32_enable_mode2sms(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (sms < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return sms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * Triggered mode sets CEN bit automatically by hardware. So, first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * enable counter clock, so it can use it. Keeps it in sync with CEN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (sms == 6 && !priv->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) clk_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) priv->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static int stm32_sms2enable_mode(int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static int stm32_get_enable_mode(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) const struct iio_chan_spec *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct stm32_timer_trigger *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) u32 smcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) regmap_read(priv->regmap, TIM_SMCR, &smcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) smcr &= TIM_SMCR_SMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return stm32_sms2enable_mode(smcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static const struct iio_enum stm32_enable_mode_enum = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .items = stm32_enable_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .num_items = ARRAY_SIZE(stm32_enable_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .set = stm32_set_enable_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .get = stm32_get_enable_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static ssize_t stm32_count_get_preset(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) uintptr_t private,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct stm32_timer_trigger *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) u32 arr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) regmap_read(priv->regmap, TIM_ARR, &arr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return snprintf(buf, PAGE_SIZE, "%u\n", arr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static ssize_t stm32_count_set_preset(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) uintptr_t private,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) const char *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct stm32_timer_trigger *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) unsigned int preset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ret = kstrtouint(buf, 0, &preset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* TIMx_ARR register shouldn't be buffered (ARPE=0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) regmap_write(priv->regmap, TIM_ARR, preset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static const struct iio_chan_spec_ext_info stm32_trigger_count_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .name = "preset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .shared = IIO_SEPARATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .read = stm32_count_get_preset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .write = stm32_count_set_preset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) IIO_ENUM("enable_mode", IIO_SEPARATE, &stm32_enable_mode_enum),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) IIO_ENUM_AVAILABLE("enable_mode", &stm32_enable_mode_enum),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) IIO_ENUM("trigger_mode", IIO_SEPARATE, &stm32_trigger_mode_enum),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) IIO_ENUM_AVAILABLE("trigger_mode", &stm32_trigger_mode_enum),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static const struct iio_chan_spec stm32_trigger_channel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .type = IIO_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) BIT(IIO_CHAN_INFO_ENABLE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .ext_info = stm32_trigger_count_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .indexed = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static struct stm32_timer_trigger *stm32_setup_counter_device(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) indio_dev = devm_iio_device_alloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) sizeof(struct stm32_timer_trigger));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) indio_dev->name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) indio_dev->info = &stm32_trigger_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) indio_dev->modes = INDIO_HARDWARE_TRIGGERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) indio_dev->num_channels = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) indio_dev->channels = &stm32_trigger_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) ret = devm_iio_device_register(dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * is_stm32_timer_trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * @trig: trigger to be checked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * return true if the trigger is a valid stm32 iio timer trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * either return false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) bool is_stm32_timer_trigger(struct iio_trigger *trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return (trig->ops == &timer_trigger_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) EXPORT_SYMBOL(is_stm32_timer_trigger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static void stm32_timer_detect_trgo2(struct stm32_timer_trigger *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * Master mode selection 2 bits can only be written and read back when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * timer supports it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, TIM_CR2_MMS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) regmap_read(priv->regmap, TIM_CR2, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) priv->has_trgo2 = !!val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static int stm32_timer_trigger_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct stm32_timer_trigger *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) const struct stm32_timer_trigger_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (of_property_read_u32(dev->of_node, "reg", &index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) cfg = (const struct stm32_timer_trigger_cfg *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) of_match_device(dev->driver->of_match_table, dev)->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (index >= ARRAY_SIZE(triggers_table) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) index >= cfg->num_valids_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* Create an IIO device only if we have triggers to be validated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (*cfg->valids_table[index])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) priv = stm32_setup_counter_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) priv->regmap = ddata->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) priv->clk = ddata->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) priv->max_arr = ddata->max_arr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) priv->triggers = triggers_table[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) priv->valids = cfg->valids_table[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) stm32_timer_detect_trgo2(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) mutex_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) ret = stm32_register_iio_triggers(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static int stm32_timer_trigger_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) struct stm32_timer_trigger *priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* Unregister triggers before everything can be safely turned off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) stm32_unregister_iio_triggers(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* Check if nobody else use the timer, then disable it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) regmap_read(priv->regmap, TIM_CCER, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (!(val & TIM_CCER_CCXE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (priv->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) clk_disable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static int __maybe_unused stm32_timer_trigger_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* Only take care of enabled timer: don't disturb other MFD child */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (priv->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /* Backup registers that may get lost in low power mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) regmap_read(priv->regmap, TIM_CR2, &priv->bak.cr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) regmap_read(priv->regmap, TIM_PSC, &priv->bak.psc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* Disable the timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) clk_disable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static int __maybe_unused stm32_timer_trigger_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (priv->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) ret = clk_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /* restore master/slave modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) regmap_write(priv->regmap, TIM_CR2, priv->bak.cr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /* restore sampling_frequency (trgo / trgo2 triggers) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) regmap_write(priv->regmap, TIM_PSC, priv->bak.psc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) regmap_write(priv->regmap, TIM_ARR, priv->bak.arr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* Also re-enables the timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static SIMPLE_DEV_PM_OPS(stm32_timer_trigger_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) stm32_timer_trigger_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) stm32_timer_trigger_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static const struct stm32_timer_trigger_cfg stm32_timer_trg_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .valids_table = valids_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .num_valids_table = ARRAY_SIZE(valids_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static const struct stm32_timer_trigger_cfg stm32h7_timer_trg_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .valids_table = stm32h7_valids_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .num_valids_table = ARRAY_SIZE(stm32h7_valids_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static const struct of_device_id stm32_trig_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .compatible = "st,stm32-timer-trigger",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .data = (void *)&stm32_timer_trg_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .compatible = "st,stm32h7-timer-trigger",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .data = (void *)&stm32h7_timer_trg_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) { /* end node */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) MODULE_DEVICE_TABLE(of, stm32_trig_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) static struct platform_driver stm32_timer_trigger_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .probe = stm32_timer_trigger_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .remove = stm32_timer_trigger_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .name = "stm32-timer-trigger",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .of_match_table = stm32_trig_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .pm = &stm32_timer_trigger_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) module_platform_driver(stm32_timer_trigger_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) MODULE_ALIAS("platform:stm32-timer-trigger");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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