^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ad2s90.c simple support for the ADI Resolver to Digital Converters: AD2S90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2010-2010 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Although chip's max frequency is 2Mhz, it needs 600ns between CS and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * first falling edge of SCLK, so frequency should be at most 1 / (2 * 6e-7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AD2S90_MAX_SPI_FREQ_HZ 830000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct ad2s90_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct mutex lock; /* lock to protect rx buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct spi_device *sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u8 rx[2] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int ad2s90_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct ad2s90_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (chan->type != IIO_ANGL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* 2 * Pi / 2^12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *val = 6283; /* mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *val2 = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ret = spi_read(st->sdev, st->rx, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *val = (((u16)(st->rx[0])) << 4) | ((st->rx[1] & 0xF0) >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static const struct iio_info ad2s90_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .read_raw = ad2s90_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static const struct iio_chan_spec ad2s90_chan = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .type = IIO_ANGL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int ad2s90_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct ad2s90_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (spi->max_speed_hz > AD2S90_MAX_SPI_FREQ_HZ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) dev_err(&spi->dev, "SPI CLK, %d Hz exceeds %d Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) spi->max_speed_hz, AD2S90_MAX_SPI_FREQ_HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) mutex_init(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) st->sdev = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) indio_dev->info = &ad2s90_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) indio_dev->channels = &ad2s90_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) indio_dev->num_channels = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return devm_iio_device_register(indio_dev->dev.parent, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static const struct of_device_id ad2s90_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { .compatible = "adi,ad2s90", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MODULE_DEVICE_TABLE(of, ad2s90_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const struct spi_device_id ad2s90_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { "ad2s90" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MODULE_DEVICE_TABLE(spi, ad2s90_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static struct spi_driver ad2s90_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .name = "ad2s90",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .of_match_table = ad2s90_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .probe = ad2s90_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .id_table = ad2s90_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) module_spi_driver(ad2s90_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MODULE_AUTHOR("Graff Yang <graff.yang@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MODULE_DESCRIPTION("Analog Devices AD2S90 Resolver to Digital SPI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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