Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * mpl3115.c - Support for Freescale MPL3115A2 pressure/temperature sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2013 Peter Meerwald <pmeerw@pmeerw.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * (7-bit I2C slave address 0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * TODO: FIFO buffer, altimeter mode, oversampling, continuous mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * interrupts, user offset correction, raw mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MPL3115_STATUS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MPL3115_OUT_PRESS 0x01 /* MSB first, 20 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MPL3115_OUT_TEMP 0x04 /* MSB first, 12 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MPL3115_WHO_AM_I 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MPL3115_CTRL_REG1 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MPL3115_DEVICE_ID 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MPL3115_STATUS_PRESS_RDY BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MPL3115_STATUS_TEMP_RDY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MPL3115_CTRL_RESET BIT(2) /* software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define MPL3115_CTRL_OST BIT(1) /* initiate measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MPL3115_CTRL_ACTIVE BIT(0) /* continuous measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MPL3115_CTRL_OS_258MS (BIT(5) | BIT(4)) /* 64x oversampling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) struct mpl3115_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u8 ctrl_reg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static int mpl3115_request(struct mpl3115_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	int ret, tries = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	/* trigger measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	ret = i2c_smbus_write_byte_data(data->client, MPL3115_CTRL_REG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		data->ctrl_reg1 | MPL3115_CTRL_OST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	while (tries-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		ret = i2c_smbus_read_byte_data(data->client, MPL3115_CTRL_REG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		/* wait for data ready, i.e. OST cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		if (!(ret & MPL3115_CTRL_OST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	if (tries < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		dev_err(&data->client->dev, "data not ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static int mpl3115_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 			    struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			    int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	struct mpl3115_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	__be32 tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		ret = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		case IIO_PRESSURE: /* in 0.25 pascal / LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			ret = mpl3115_request(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 				mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 			ret = i2c_smbus_read_i2c_block_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 				MPL3115_OUT_PRESS, 3, (u8 *) &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 			if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			*val = be32_to_cpu(tmp) >> 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		case IIO_TEMP: /* in 0.0625 celsius / LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 			mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			ret = mpl3115_request(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 				mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			ret = i2c_smbus_read_i2c_block_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 				MPL3115_OUT_TEMP, 2, (u8 *) &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 			*val = sign_extend32(be32_to_cpu(tmp) >> 20, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		case IIO_PRESSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			*val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			*val2 = 250; /* want kilopascal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			*val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			*val2 = 62500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static irqreturn_t mpl3115_trigger_handler(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	struct mpl3115_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	 * 32-bit channel + 16-bit channel + padding + ts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	 * Note that it is possible for only one of the first 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	 * channels to be enabled. If that happens, the first element
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	 * of the buffer may be either 16 or 32-bits.  As such we cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	 * use a simple structure definition to express this data layout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	u8 buffer[16] __aligned(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	int ret, pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	ret = mpl3115_request(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	memset(buffer, 0, sizeof(buffer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (test_bit(0, indio_dev->active_scan_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		ret = i2c_smbus_read_i2c_block_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			MPL3115_OUT_PRESS, 3, &buffer[pos]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		pos += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (test_bit(1, indio_dev->active_scan_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		ret = i2c_smbus_read_i2c_block_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			MPL3115_OUT_TEMP, 2, &buffer[pos]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	iio_push_to_buffers_with_timestamp(indio_dev, buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static const struct iio_chan_spec mpl3115_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		.type = IIO_PRESSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		.scan_index = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		.scan_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			.sign = 'u',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			.realbits = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			.storagebits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			.shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			.endianness = IIO_BE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		.type = IIO_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		.scan_index = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		.scan_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			.sign = 's',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			.realbits = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			.storagebits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			.shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			.endianness = IIO_BE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	IIO_CHAN_SOFT_TIMESTAMP(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const struct iio_info mpl3115_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	.read_raw = &mpl3115_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int mpl3115_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			 const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	struct mpl3115_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	ret = i2c_smbus_read_byte_data(client, MPL3115_WHO_AM_I);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	if (ret != MPL3115_DEVICE_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	mutex_init(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	indio_dev->info = &mpl3115_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	indio_dev->name = id->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	indio_dev->channels = mpl3115_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	indio_dev->num_channels = ARRAY_SIZE(mpl3115_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	/* software reset, I2C transfer is aborted (fails) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	i2c_smbus_write_byte_data(client, MPL3115_CTRL_REG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		MPL3115_CTRL_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	data->ctrl_reg1 = MPL3115_CTRL_OS_258MS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	ret = i2c_smbus_write_byte_data(client, MPL3115_CTRL_REG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		data->ctrl_reg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	ret = iio_triggered_buffer_setup(indio_dev, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		mpl3115_trigger_handler, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		goto buffer_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) buffer_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int mpl3115_standby(struct mpl3115_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	return i2c_smbus_write_byte_data(data->client, MPL3115_CTRL_REG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		data->ctrl_reg1 & ~MPL3115_CTRL_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int mpl3115_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	struct iio_dev *indio_dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	mpl3115_standby(iio_priv(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static int mpl3115_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	return mpl3115_standby(iio_priv(i2c_get_clientdata(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		to_i2c_client(dev))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int mpl3115_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	struct mpl3115_data *data = iio_priv(i2c_get_clientdata(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		to_i2c_client(dev)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	return i2c_smbus_write_byte_data(data->client, MPL3115_CTRL_REG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		data->ctrl_reg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static SIMPLE_DEV_PM_OPS(mpl3115_pm_ops, mpl3115_suspend, mpl3115_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define MPL3115_PM_OPS (&mpl3115_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define MPL3115_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const struct i2c_device_id mpl3115_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	{ "mpl3115", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) MODULE_DEVICE_TABLE(i2c, mpl3115_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const struct of_device_id mpl3115_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	{ .compatible = "fsl,mpl3115" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) MODULE_DEVICE_TABLE(of, mpl3115_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static struct i2c_driver mpl3115_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		.name	= "mpl3115",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		.of_match_table = mpl3115_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		.pm	= MPL3115_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	.probe = mpl3115_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	.remove = mpl3115_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	.id_table = mpl3115_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) module_i2c_driver(mpl3115_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) MODULE_DESCRIPTION("Freescale MPL3115 pressure/temperature driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) MODULE_LICENSE("GPL");