^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * mpl115.c - Support for Freescale MPL115A pressure/temperature sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014 Peter Meerwald <pmeerw@pmeerw.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * TODO: shutdown pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "mpl115.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MPL115_PADC 0x00 /* pressure ADC output value, MSB first, 10 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MPL115_TADC 0x02 /* temperature ADC output value, MSB first, 10 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MPL115_A0 0x04 /* 12 bit integer, 3 bit fraction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MPL115_B1 0x06 /* 2 bit integer, 13 bit fraction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MPL115_B2 0x08 /* 1 bit integer, 14 bit fraction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MPL115_C12 0x0a /* 0 bit integer, 13 bit fraction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MPL115_CONVERT 0x12 /* convert temperature and pressure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct mpl115_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) s16 a0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) s16 b1, b2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) s16 c12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) const struct mpl115_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int mpl115_request(struct mpl115_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) int ret = data->ops->write(data->dev, MPL115_CONVERT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) usleep_range(3000, 4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static int mpl115_comp_pressure(struct mpl115_data *data, int *val, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u16 padc, tadc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int a1, y1, pcomp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned kpa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ret = mpl115_request(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ret = data->ops->read(data->dev, MPL115_PADC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) padc = ret >> 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ret = data->ops->read(data->dev, MPL115_TADC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) tadc = ret >> 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* see Freescale AN3785 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) a1 = data->b1 + ((data->c12 * tadc) >> 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) y1 = (data->a0 << 10) + a1 * padc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* compensated pressure with 4 fractional bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) pcomp = (y1 + ((data->b2 * (int) tadc) >> 1)) >> 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) kpa = pcomp * (115 - 50) / 1023 + (50 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) *val = kpa >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) *val2 = (kpa & 15) * (1000000 >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int mpl115_read_temp(struct mpl115_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ret = mpl115_request(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ret = data->ops->read(data->dev, MPL115_TADC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int mpl115_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct mpl115_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) case IIO_CHAN_INFO_PROCESSED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ret = mpl115_comp_pressure(data, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* temperature -5.35 C / LSB, 472 LSB is 25 C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ret = mpl115_read_temp(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) *val = ret >> 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) *val = -605;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) *val2 = 750000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) *val = -186;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) *val2 = 915888;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const struct iio_chan_spec mpl115_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .type = IIO_PRESSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .type = IIO_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .info_mask_shared_by_type =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) BIT(IIO_CHAN_INFO_OFFSET) | BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const struct iio_info mpl115_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .read_raw = &mpl115_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int mpl115_probe(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) const struct mpl115_ops *ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct mpl115_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) data->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) data->ops = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) mutex_init(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) indio_dev->info = &mpl115_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) indio_dev->name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) indio_dev->channels = mpl115_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) indio_dev->num_channels = ARRAY_SIZE(mpl115_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ret = data->ops->init(data->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ret = data->ops->read(data->dev, MPL115_A0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) data->a0 = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = data->ops->read(data->dev, MPL115_B1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) data->b1 = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ret = data->ops->read(data->dev, MPL115_B2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) data->b2 = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ret = data->ops->read(data->dev, MPL115_C12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) data->c12 = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return devm_iio_device_register(dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) EXPORT_SYMBOL_GPL(mpl115_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MODULE_DESCRIPTION("Freescale MPL115 pressure/temperature driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags