^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright IBM Corp 2019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * The DPS310 is a barometric pressure and temperature sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Currently only reading a single temperature is supported by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * https://www.infineon.com/dgdl/?fileId=5546d462576f34750157750826c42242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Temperature calculation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * c0 * 0.5 + c1 * T_raw / kT °C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * TODO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * - Optionally support the FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/limits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DPS310_DEV_NAME "dps310"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DPS310_PRS_B0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DPS310_PRS_B1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DPS310_PRS_B2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DPS310_TMP_B0 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DPS310_TMP_B1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DPS310_TMP_B2 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DPS310_PRS_CFG 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DPS310_PRS_RATE_BITS GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DPS310_PRS_PRC_BITS GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DPS310_TMP_CFG 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DPS310_TMP_RATE_BITS GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DPS310_TMP_PRC_BITS GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DPS310_TMP_EXT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DPS310_MEAS_CFG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DPS310_MEAS_CTRL_BITS GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DPS310_PRS_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DPS310_TEMP_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DPS310_BACKGROUND BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DPS310_PRS_RDY BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DPS310_TMP_RDY BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DPS310_SENSOR_RDY BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DPS310_COEF_RDY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DPS310_CFG_REG 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DPS310_INT_HL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DPS310_TMP_SHIFT_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DPS310_PRS_SHIFT_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DPS310_FIFO_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DPS310_SPI_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DPS310_RESET 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DPS310_RESET_MAGIC 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DPS310_COEF_BASE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Make sure sleep time is <= 20ms for usleep_range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DPS310_POLL_SLEEP_US(t) min(20000, (t) / 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Silently handle error in rate value here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DPS310_POLL_TIMEOUT_US(rc) ((rc) <= 0 ? 1000000 : 1000000 / (rc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DPS310_PRS_BASE DPS310_PRS_B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DPS310_TMP_BASE DPS310_TMP_B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * These values (defined in the spec) indicate how to scale the raw register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * values for each level of precision available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const int scale_factors[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 524288,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 1572864,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 3670016,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 7864320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 253952,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 516096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 1040384,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 2088960,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct dps310_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct mutex lock; /* Lock for sequential HW access functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) s32 c0, c1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) s32 c00, c10, c20, c30, c01, c11, c21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) s32 pressure_raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) s32 temp_raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static const struct iio_chan_spec dps310_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .type = IIO_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .info_mask_separate = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) BIT(IIO_CHAN_INFO_SAMP_FREQ) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) BIT(IIO_CHAN_INFO_PROCESSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .type = IIO_PRESSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .info_mask_separate = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) BIT(IIO_CHAN_INFO_SAMP_FREQ) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) BIT(IIO_CHAN_INFO_PROCESSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* To be called after checking the COEF_RDY bit in MEAS_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int dps310_get_coefs(struct dps310_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u8 coef[18];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 c0, c1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 c00, c10, c20, c30, c01, c11, c21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Read all sensor calibration coefficients from the COEF registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) rc = regmap_bulk_read(data->regmap, DPS310_COEF_BASE, coef,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) sizeof(coef));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Calculate temperature calibration coefficients c0 and c1. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * numbers are 12-bit 2's complement numbers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) c0 = (coef[0] << 4) | (coef[1] >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) data->c0 = sign_extend32(c0, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) c1 = ((coef[1] & GENMASK(3, 0)) << 8) | coef[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) data->c1 = sign_extend32(c1, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Calculate pressure calibration coefficients. c00 and c10 are 20 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * 2's complement numbers, while the rest are 16 bit 2's complement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * numbers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) c00 = (coef[3] << 12) | (coef[4] << 4) | (coef[5] >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) data->c00 = sign_extend32(c00, 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) c10 = ((coef[5] & GENMASK(3, 0)) << 16) | (coef[6] << 8) | coef[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) data->c10 = sign_extend32(c10, 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) c01 = (coef[8] << 8) | coef[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) data->c01 = sign_extend32(c01, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) c11 = (coef[10] << 8) | coef[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) data->c11 = sign_extend32(c11, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) c20 = (coef[12] << 8) | coef[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) data->c20 = sign_extend32(c20, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) c21 = (coef[14] << 8) | coef[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) data->c21 = sign_extend32(c21, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) c30 = (coef[16] << 8) | coef[17];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) data->c30 = sign_extend32(c30, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int dps310_get_pres_precision(struct dps310_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) rc = regmap_read(data->regmap, DPS310_PRS_CFG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return BIT(val & GENMASK(2, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int dps310_get_temp_precision(struct dps310_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) rc = regmap_read(data->regmap, DPS310_TMP_CFG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * Scale factor is bottom 4 bits of the register, but 1111 is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * reserved so just grab bottom three
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return BIT(val & GENMASK(2, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Called with lock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static int dps310_set_pres_precision(struct dps310_data *data, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u8 shift_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (val < 0 || val > 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) shift_en = val >= 16 ? DPS310_PRS_SHIFT_EN : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) rc = regmap_write_bits(data->regmap, DPS310_CFG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) DPS310_PRS_SHIFT_EN, shift_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return regmap_update_bits(data->regmap, DPS310_PRS_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) DPS310_PRS_PRC_BITS, ilog2(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Called with lock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int dps310_set_temp_precision(struct dps310_data *data, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u8 shift_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (val < 0 || val > 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) shift_en = val >= 16 ? DPS310_TMP_SHIFT_EN : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) rc = regmap_write_bits(data->regmap, DPS310_CFG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) DPS310_TMP_SHIFT_EN, shift_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return regmap_update_bits(data->regmap, DPS310_TMP_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) DPS310_TMP_PRC_BITS, ilog2(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Called with lock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int dps310_set_pres_samp_freq(struct dps310_data *data, int freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (freq < 0 || freq > 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) val = ilog2(freq) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return regmap_update_bits(data->regmap, DPS310_PRS_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) DPS310_PRS_RATE_BITS, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Called with lock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int dps310_set_temp_samp_freq(struct dps310_data *data, int freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (freq < 0 || freq > 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) val = ilog2(freq) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return regmap_update_bits(data->regmap, DPS310_TMP_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) DPS310_TMP_RATE_BITS, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int dps310_get_pres_samp_freq(struct dps310_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) rc = regmap_read(data->regmap, DPS310_PRS_CFG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return BIT((val & DPS310_PRS_RATE_BITS) >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int dps310_get_temp_samp_freq(struct dps310_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) rc = regmap_read(data->regmap, DPS310_TMP_CFG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return BIT((val & DPS310_TMP_RATE_BITS) >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int dps310_get_pres_k(struct dps310_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int rc = dps310_get_pres_precision(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return scale_factors[ilog2(rc)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int dps310_get_temp_k(struct dps310_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int rc = dps310_get_temp_precision(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return scale_factors[ilog2(rc)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int dps310_read_pres_raw(struct dps310_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) s32 raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u8 val[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (mutex_lock_interruptible(&data->lock))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return -EINTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) rate = dps310_get_pres_samp_freq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) timeout = DPS310_POLL_TIMEOUT_US(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Poll for sensor readiness; base the timeout upon the sample rate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) rc = regmap_read_poll_timeout(data->regmap, DPS310_MEAS_CFG, ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ready & DPS310_PRS_RDY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) DPS310_POLL_SLEEP_US(timeout), timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) rc = regmap_bulk_read(data->regmap, DPS310_PRS_BASE, val, sizeof(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) raw = (val[0] << 16) | (val[1] << 8) | val[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) data->pressure_raw = sign_extend32(raw, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Called with lock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int dps310_read_temp_ready(struct dps310_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u8 val[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) s32 raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) rc = regmap_bulk_read(data->regmap, DPS310_TMP_BASE, val, sizeof(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) raw = (val[0] << 16) | (val[1] << 8) | val[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) data->temp_raw = sign_extend32(raw, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static int dps310_read_temp_raw(struct dps310_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (mutex_lock_interruptible(&data->lock))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return -EINTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) rate = dps310_get_temp_samp_freq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) timeout = DPS310_POLL_TIMEOUT_US(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* Poll for sensor readiness; base the timeout upon the sample rate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) rc = regmap_read_poll_timeout(data->regmap, DPS310_MEAS_CFG, ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ready & DPS310_TMP_RDY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) DPS310_POLL_SLEEP_US(timeout), timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) rc = dps310_read_temp_ready(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static bool dps310_is_writeable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) case DPS310_PRS_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) case DPS310_TMP_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) case DPS310_MEAS_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) case DPS310_CFG_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) case DPS310_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* No documentation available on the registers below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) case 0x0e:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) case 0x0f:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) case 0x62:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static bool dps310_is_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) case DPS310_PRS_B0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) case DPS310_PRS_B1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) case DPS310_PRS_B2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) case DPS310_TMP_B0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) case DPS310_TMP_B1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) case DPS310_TMP_B2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) case DPS310_MEAS_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) case 0x32: /* No documentation available on this register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static int dps310_write_raw(struct iio_dev *iio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct iio_chan_spec const *chan, int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct dps310_data *data = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (mutex_lock_interruptible(&data->lock))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return -EINTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) case IIO_PRESSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) rc = dps310_set_pres_samp_freq(data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) rc = dps310_set_temp_samp_freq(data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case IIO_PRESSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) rc = dps310_set_pres_precision(data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) rc = dps310_set_temp_precision(data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static int dps310_calculate_pressure(struct dps310_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) int t_ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int kpi = dps310_get_pres_k(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) int kti = dps310_get_temp_k(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) s64 rem = 0ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) s64 pressure = 0ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) s64 p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) s64 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) s64 denoms[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) s64 nums[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) s64 rems[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) s64 kp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) s64 kt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (kpi < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return kpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (kti < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return kti;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) kp = (s64)kpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) kt = (s64)kti;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* Refresh temp if it's ready, otherwise just use the latest value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (mutex_trylock(&data->lock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) rc = regmap_read(data->regmap, DPS310_MEAS_CFG, &t_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (rc >= 0 && t_ready & DPS310_TMP_RDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) dps310_read_temp_ready(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) p = (s64)data->pressure_raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) t = (s64)data->temp_raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* Section 4.9.1 of the DPS310 spec; algebra'd to avoid underflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) nums[0] = (s64)data->c00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) denoms[0] = 1LL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) nums[1] = p * (s64)data->c10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) denoms[1] = kp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) nums[2] = p * p * (s64)data->c20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) denoms[2] = kp * kp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) nums[3] = p * p * p * (s64)data->c30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) denoms[3] = kp * kp * kp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) nums[4] = t * (s64)data->c01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) denoms[4] = kt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) nums[5] = t * p * (s64)data->c11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) denoms[5] = kp * kt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) nums[6] = t * p * p * (s64)data->c21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) denoms[6] = kp * kp * kt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* Kernel lacks a div64_s64_rem function; denoms are all positive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) for (i = 0; i < 7; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u64 irem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (nums[i] < 0LL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) pressure -= div64_u64_rem(-nums[i], denoms[i], &irem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) rems[i] = -irem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) pressure += div64_u64_rem(nums[i], denoms[i], &irem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) rems[i] = (s64)irem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* Increase precision and calculate the remainder sum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) for (i = 0; i < 7; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) rem += div64_s64((s64)rems[i] * 1000000000LL, denoms[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) pressure += div_s64(rem, 1000000000LL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (pressure < 0LL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return (int)min_t(s64, pressure, INT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static int dps310_read_pressure(struct dps310_data *data, int *val, int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) rc = dps310_get_pres_samp_freq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) *val = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) case IIO_CHAN_INFO_PROCESSED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) rc = dps310_read_pres_raw(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) rc = dps310_calculate_pressure(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) *val = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) *val2 = 1000; /* Convert Pa to KPa per IIO ABI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return IIO_VAL_FRACTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) rc = dps310_get_pres_precision(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) *val = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static int dps310_calculate_temp(struct dps310_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) s64 c0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) s64 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) int kt = dps310_get_temp_k(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (kt < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return kt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* Obtain inverse-scaled offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) c0 = div_s64((s64)kt * (s64)data->c0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* Add the offset to the unscaled temperature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) t = c0 + ((s64)data->temp_raw * (s64)data->c1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* Convert to milliCelsius and scale the temperature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return (int)div_s64(t * 1000LL, kt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static int dps310_read_temp(struct dps310_data *data, int *val, int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) rc = dps310_get_temp_samp_freq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) *val = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) case IIO_CHAN_INFO_PROCESSED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) rc = dps310_read_temp_raw(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) rc = dps310_calculate_temp(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) *val = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) rc = dps310_get_temp_precision(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) *val = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static int dps310_read_raw(struct iio_dev *iio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct dps310_data *data = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) case IIO_PRESSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return dps310_read_pressure(data, val, val2, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return dps310_read_temp(data, val, val2, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static void dps310_reset(void *action_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct dps310_data *data = action_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) regmap_write(data->regmap, DPS310_RESET, DPS310_RESET_MAGIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static const struct regmap_config dps310_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .writeable_reg = dps310_is_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .volatile_reg = dps310_is_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .max_register = 0x62, /* No documentation available on this register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static const struct iio_info dps310_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .read_raw = dps310_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .write_raw = dps310_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * Some verions of chip will read temperatures in the ~60C range when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * its actually ~20C. This is the manufacturer recommended workaround
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * to correct the issue. The registers used below are undocumented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static int dps310_temp_workaround(struct dps310_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) rc = regmap_read(data->regmap, 0x32, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * If bit 1 is set then the device is okay, and the workaround does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * need to be applied
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (reg & BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) rc = regmap_write(data->regmap, 0x0e, 0xA5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) rc = regmap_write(data->regmap, 0x0f, 0x96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) rc = regmap_write(data->regmap, 0x62, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) rc = regmap_write(data->regmap, 0x0e, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return regmap_write(data->regmap, 0x0f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static int dps310_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct dps310_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct iio_dev *iio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) int rc, ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) iio = devm_iio_device_alloc(&client->dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (!iio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) data = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) mutex_init(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) iio->name = id->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) iio->channels = dps310_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) iio->num_channels = ARRAY_SIZE(dps310_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) iio->info = &dps310_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) iio->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) data->regmap = devm_regmap_init_i2c(client, &dps310_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (IS_ERR(data->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return PTR_ERR(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* Register to run the device reset when the device is removed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) rc = devm_add_action_or_reset(&client->dev, dps310_reset, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * Set up pressure sensor in single sample, one measurement per second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) rc = regmap_write(data->regmap, DPS310_PRS_CFG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * Set up external (MEMS) temperature sensor in single sample, one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * measurement per second mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) rc = regmap_write(data->regmap, DPS310_TMP_CFG, DPS310_TMP_EXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* Temp and pressure shifts are disabled when PRC <= 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) rc = regmap_write_bits(data->regmap, DPS310_CFG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) DPS310_PRS_SHIFT_EN | DPS310_TMP_SHIFT_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /* MEAS_CFG doesn't update correctly unless first written with 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) rc = regmap_write_bits(data->regmap, DPS310_MEAS_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) DPS310_MEAS_CTRL_BITS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* Turn on temperature and pressure measurement in the background */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) rc = regmap_write_bits(data->regmap, DPS310_MEAS_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) DPS310_MEAS_CTRL_BITS, DPS310_PRS_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) DPS310_TEMP_EN | DPS310_BACKGROUND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * Calibration coefficients required for reporting temperature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * They are available 40ms after the device has started
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) rc = regmap_read_poll_timeout(data->regmap, DPS310_MEAS_CFG, ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) ready & DPS310_COEF_RDY, 10000, 40000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) rc = dps310_get_coefs(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) rc = dps310_temp_workaround(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) rc = devm_iio_device_register(&client->dev, iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) i2c_set_clientdata(client, iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static const struct i2c_device_id dps310_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) { DPS310_DEV_NAME, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) MODULE_DEVICE_TABLE(i2c, dps310_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static struct i2c_driver dps310_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .name = DPS310_DEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .probe = dps310_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .id_table = dps310_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) module_i2c_driver(dps310_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) MODULE_AUTHOR("Joel Stanley <joel@jms.id.au>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) MODULE_DESCRIPTION("Infineon DPS310 pressure and temperature sensor");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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