^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /* BMP280 specific registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define BMP280_REG_HUMIDITY_LSB 0xFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define BMP280_REG_HUMIDITY_MSB 0xFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define BMP280_REG_TEMP_XLSB 0xFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define BMP280_REG_TEMP_LSB 0xFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define BMP280_REG_TEMP_MSB 0xFA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define BMP280_REG_PRESS_XLSB 0xF9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define BMP280_REG_PRESS_LSB 0xF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define BMP280_REG_PRESS_MSB 0xF7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define BMP280_REG_CONFIG 0xF5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define BMP280_REG_CTRL_MEAS 0xF4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define BMP280_REG_STATUS 0xF3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define BMP280_REG_CTRL_HUMIDITY 0xF2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Due to non linear mapping, and data sizes we can't do a bulk read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define BMP280_REG_COMP_H1 0xA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BMP280_REG_COMP_H2 0xE1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BMP280_REG_COMP_H3 0xE3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define BMP280_REG_COMP_H4 0xE4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BMP280_REG_COMP_H5 0xE5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BMP280_REG_COMP_H6 0xE7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BMP280_REG_COMP_TEMP_START 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BMP280_COMP_TEMP_REG_COUNT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BMP280_REG_COMP_PRESS_START 0x8E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BMP280_COMP_PRESS_REG_COUNT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BMP280_FILTER_MASK (BIT(4) | BIT(3) | BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BMP280_FILTER_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BMP280_FILTER_2X BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BMP280_FILTER_4X BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BMP280_FILTER_8X (BIT(3) | BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BMP280_FILTER_16X BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BMP280_OSRS_HUMIDITY_MASK (BIT(2) | BIT(1) | BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BMP280_OSRS_HUMIDITIY_X(osrs_h) ((osrs_h) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BMP280_OSRS_HUMIDITY_SKIP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BMP280_OSRS_HUMIDITY_1X BMP280_OSRS_HUMIDITIY_X(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BMP280_OSRS_HUMIDITY_2X BMP280_OSRS_HUMIDITIY_X(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BMP280_OSRS_HUMIDITY_4X BMP280_OSRS_HUMIDITIY_X(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BMP280_OSRS_HUMIDITY_8X BMP280_OSRS_HUMIDITIY_X(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BMP280_OSRS_HUMIDITY_16X BMP280_OSRS_HUMIDITIY_X(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BMP280_OSRS_TEMP_MASK (BIT(7) | BIT(6) | BIT(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BMP280_OSRS_TEMP_SKIP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define BMP280_OSRS_TEMP_X(osrs_t) ((osrs_t) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define BMP280_OSRS_TEMP_1X BMP280_OSRS_TEMP_X(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define BMP280_OSRS_TEMP_2X BMP280_OSRS_TEMP_X(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define BMP280_OSRS_TEMP_4X BMP280_OSRS_TEMP_X(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define BMP280_OSRS_TEMP_8X BMP280_OSRS_TEMP_X(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define BMP280_OSRS_TEMP_16X BMP280_OSRS_TEMP_X(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BMP280_OSRS_PRESS_MASK (BIT(4) | BIT(3) | BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define BMP280_OSRS_PRESS_SKIP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define BMP280_OSRS_PRESS_X(osrs_p) ((osrs_p) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define BMP280_OSRS_PRESS_1X BMP280_OSRS_PRESS_X(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define BMP280_OSRS_PRESS_2X BMP280_OSRS_PRESS_X(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define BMP280_OSRS_PRESS_4X BMP280_OSRS_PRESS_X(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define BMP280_OSRS_PRESS_8X BMP280_OSRS_PRESS_X(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define BMP280_OSRS_PRESS_16X BMP280_OSRS_PRESS_X(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define BMP280_MODE_MASK (BIT(1) | BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define BMP280_MODE_SLEEP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define BMP280_MODE_FORCED BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define BMP280_MODE_NORMAL (BIT(1) | BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* BMP180 specific registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define BMP180_REG_OUT_XLSB 0xF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define BMP180_REG_OUT_LSB 0xF7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define BMP180_REG_OUT_MSB 0xF6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define BMP180_REG_CALIB_START 0xAA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define BMP180_REG_CALIB_COUNT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define BMP180_MEAS_SCO BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define BMP180_MEAS_TEMP (0x0E | BMP180_MEAS_SCO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define BMP180_MEAS_PRESS_X(oss) ((oss) << 6 | 0x14 | BMP180_MEAS_SCO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define BMP180_MEAS_PRESS_1X BMP180_MEAS_PRESS_X(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define BMP180_MEAS_PRESS_2X BMP180_MEAS_PRESS_X(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define BMP180_MEAS_PRESS_4X BMP180_MEAS_PRESS_X(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define BMP180_MEAS_PRESS_8X BMP180_MEAS_PRESS_X(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* BMP180 and BMP280 common registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define BMP280_REG_CTRL_MEAS 0xF4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define BMP280_REG_RESET 0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define BMP280_REG_ID 0xD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define BMP180_CHIP_ID 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define BMP280_CHIP_ID 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define BME280_CHIP_ID 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define BMP280_SOFT_RESET_VAL 0xB6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* BMP280 register skipped special values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define BMP280_TEMP_SKIPPED 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define BMP280_PRESS_SKIPPED 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define BMP280_HUMIDITY_SKIPPED 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Regmap configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) extern const struct regmap_config bmp180_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) extern const struct regmap_config bmp280_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Probe called from different transports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int bmp280_common_probe(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned int chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* PM ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) extern const struct dev_pm_ops bmp280_dev_pm_ops;
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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