Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Industrial I/O driver for Microchip digital potentiometers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2016 Slawomir Stepien
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Based on: Peter Rosin's code from mcp4531.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/22060b.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * DEVID	#Wipers	#Positions	Resistor Opts (kOhm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * mcp4131	1	129		5, 10, 50, 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * mcp4132	1	129		5, 10, 50, 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * mcp4141	1	129		5, 10, 50, 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * mcp4142	1	129		5, 10, 50, 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * mcp4151	1	257		5, 10, 50, 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * mcp4152	1	257		5, 10, 50, 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * mcp4161	1	257		5, 10, 50, 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * mcp4162	1	257		5, 10, 50, 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * mcp4231	2	129		5, 10, 50, 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * mcp4232	2	129		5, 10, 50, 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * mcp4241	2	129		5, 10, 50, 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * mcp4242	2	129		5, 10, 50, 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * mcp4251	2	257		5, 10, 50, 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * mcp4252	2	257		5, 10, 50, 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * mcp4261	2	257		5, 10, 50, 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * mcp4262	2	257		5, 10, 50, 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * TODO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * 1. Write wiper setting to EEPROM for EEPROM capable models.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <linux/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include <linux/iio/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define MCP4131_WRITE		(0x00 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define MCP4131_READ		(0x03 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MCP4131_WIPER_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define MCP4131_CMDERR(r)	((r[0]) & 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define MCP4131_RAW(r)		((r[0]) == 0xff ? 0x100 : (r[1]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) struct mcp4131_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	int wipers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	int max_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	int kohms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) enum mcp4131_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	MCP413x_502 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	MCP413x_103,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	MCP413x_503,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	MCP413x_104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	MCP414x_502,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	MCP414x_103,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	MCP414x_503,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	MCP414x_104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	MCP415x_502,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	MCP415x_103,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	MCP415x_503,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	MCP415x_104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	MCP416x_502,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	MCP416x_103,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	MCP416x_503,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	MCP416x_104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	MCP423x_502,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	MCP423x_103,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	MCP423x_503,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	MCP423x_104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	MCP424x_502,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	MCP424x_103,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	MCP424x_503,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	MCP424x_104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	MCP425x_502,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	MCP425x_103,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	MCP425x_503,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	MCP425x_104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	MCP426x_502,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	MCP426x_103,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	MCP426x_503,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	MCP426x_104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static const struct mcp4131_cfg mcp4131_cfg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	[MCP413x_502] = { .wipers = 1, .max_pos = 128, .kohms =   5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	[MCP413x_103] = { .wipers = 1, .max_pos = 128, .kohms =  10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	[MCP413x_503] = { .wipers = 1, .max_pos = 128, .kohms =  50, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	[MCP413x_104] = { .wipers = 1, .max_pos = 128, .kohms = 100, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	[MCP414x_502] = { .wipers = 1, .max_pos = 128, .kohms =   5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	[MCP414x_103] = { .wipers = 1, .max_pos = 128, .kohms =  10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	[MCP414x_503] = { .wipers = 1, .max_pos = 128, .kohms =  50, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	[MCP414x_104] = { .wipers = 1, .max_pos = 128, .kohms = 100, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	[MCP415x_502] = { .wipers = 1, .max_pos = 256, .kohms =   5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	[MCP415x_103] = { .wipers = 1, .max_pos = 256, .kohms =  10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	[MCP415x_503] = { .wipers = 1, .max_pos = 256, .kohms =  50, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	[MCP415x_104] = { .wipers = 1, .max_pos = 256, .kohms = 100, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	[MCP416x_502] = { .wipers = 1, .max_pos = 256, .kohms =   5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	[MCP416x_103] = { .wipers = 1, .max_pos = 256, .kohms =  10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	[MCP416x_503] = { .wipers = 1, .max_pos = 256, .kohms =  50, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	[MCP416x_104] = { .wipers = 1, .max_pos = 256, .kohms = 100, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	[MCP423x_502] = { .wipers = 2, .max_pos = 128, .kohms =   5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	[MCP423x_103] = { .wipers = 2, .max_pos = 128, .kohms =  10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	[MCP423x_503] = { .wipers = 2, .max_pos = 128, .kohms =  50, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	[MCP423x_104] = { .wipers = 2, .max_pos = 128, .kohms = 100, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	[MCP424x_502] = { .wipers = 2, .max_pos = 128, .kohms =   5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	[MCP424x_103] = { .wipers = 2, .max_pos = 128, .kohms =  10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	[MCP424x_503] = { .wipers = 2, .max_pos = 128, .kohms =  50, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	[MCP424x_104] = { .wipers = 2, .max_pos = 128, .kohms = 100, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	[MCP425x_502] = { .wipers = 2, .max_pos = 256, .kohms =   5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	[MCP425x_103] = { .wipers = 2, .max_pos = 256, .kohms =  10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	[MCP425x_503] = { .wipers = 2, .max_pos = 256, .kohms =  50, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	[MCP425x_104] = { .wipers = 2, .max_pos = 256, .kohms = 100, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	[MCP426x_502] = { .wipers = 2, .max_pos = 256, .kohms =   5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	[MCP426x_103] = { .wipers = 2, .max_pos = 256, .kohms =  10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	[MCP426x_503] = { .wipers = 2, .max_pos = 256, .kohms =  50, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	[MCP426x_104] = { .wipers = 2, .max_pos = 256, .kohms = 100, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct mcp4131_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	const struct mcp4131_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	u8 buf[2] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MCP4131_CHANNEL(ch) {					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.type = IIO_RESISTANCE,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.indexed = 1,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.output = 1,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.channel = (ch),					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const struct iio_chan_spec mcp4131_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	MCP4131_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	MCP4131_CHANNEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int mcp4131_read(struct spi_device *spi, void *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	struct spi_transfer t = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		.tx_buf = buf, /* We need to send addr, cmd and 12 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		.rx_buf	= buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		.len = len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	struct spi_message m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	spi_message_init(&m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	spi_message_add_tail(&t, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	return spi_sync(spi, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int mcp4131_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			    struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			    int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	struct mcp4131_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	int address = chan->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		data->buf[0] = (address << MCP4131_WIPER_SHIFT) | MCP4131_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		data->buf[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		err = mcp4131_read(data->spi, data->buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		/* Error, bad address/command combination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		if (!MCP4131_CMDERR(data->buf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		*val = MCP4131_RAW(data->buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		*val = 1000 * data->cfg->kohms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		*val2 = data->cfg->max_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		return IIO_VAL_FRACTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int mcp4131_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			     struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			     int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct mcp4131_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	int address = chan->channel << MCP4131_WIPER_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		if (val > data->cfg->max_pos || val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	data->buf[0] = address << MCP4131_WIPER_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	data->buf[0] |= MCP4131_WRITE | (val >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	data->buf[1] = val & 0xFF; /* 8 bits here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	err = spi_write(data->spi, data->buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const struct iio_info mcp4131_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	.read_raw = mcp4131_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	.write_raw = mcp4131_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int mcp4131_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	struct device *dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	unsigned long devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	struct mcp4131_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	data->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	data->cfg = device_get_match_data(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	if (!data->cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		devid = spi_get_device_id(spi)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		data->cfg = &mcp4131_cfg[devid];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	mutex_init(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	indio_dev->info = &mcp4131_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	indio_dev->channels = mcp4131_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	indio_dev->num_channels = data->cfg->wipers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	err = devm_iio_device_register(dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		dev_info(&spi->dev, "Unable to register %s\n", indio_dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const struct of_device_id mcp4131_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	{ .compatible = "microchip,mcp4131-502",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		.data = &mcp4131_cfg[MCP413x_502] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	{ .compatible = "microchip,mcp4131-103",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		.data = &mcp4131_cfg[MCP413x_103] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	{ .compatible = "microchip,mcp4131-503",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		.data = &mcp4131_cfg[MCP413x_503] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	{ .compatible = "microchip,mcp4131-104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		.data = &mcp4131_cfg[MCP413x_104] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	{ .compatible = "microchip,mcp4132-502",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		.data = &mcp4131_cfg[MCP413x_502] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	{ .compatible = "microchip,mcp4132-103",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		.data = &mcp4131_cfg[MCP413x_103] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	{ .compatible = "microchip,mcp4132-503",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		.data = &mcp4131_cfg[MCP413x_503] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	{ .compatible = "microchip,mcp4132-104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		.data = &mcp4131_cfg[MCP413x_104] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	{ .compatible = "microchip,mcp4141-502",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		.data = &mcp4131_cfg[MCP414x_502] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	{ .compatible = "microchip,mcp4141-103",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		.data = &mcp4131_cfg[MCP414x_103] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	{ .compatible = "microchip,mcp4141-503",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		.data = &mcp4131_cfg[MCP414x_503] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	{ .compatible = "microchip,mcp4141-104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		.data = &mcp4131_cfg[MCP414x_104] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	{ .compatible = "microchip,mcp4142-502",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		.data = &mcp4131_cfg[MCP414x_502] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	{ .compatible = "microchip,mcp4142-103",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		.data = &mcp4131_cfg[MCP414x_103] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	{ .compatible = "microchip,mcp4142-503",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		.data = &mcp4131_cfg[MCP414x_503] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	{ .compatible = "microchip,mcp4142-104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		.data = &mcp4131_cfg[MCP414x_104] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	{ .compatible = "microchip,mcp4151-502",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		.data = &mcp4131_cfg[MCP415x_502] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	{ .compatible = "microchip,mcp4151-103",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		.data = &mcp4131_cfg[MCP415x_103] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	{ .compatible = "microchip,mcp4151-503",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		.data = &mcp4131_cfg[MCP415x_503] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	{ .compatible = "microchip,mcp4151-104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		.data = &mcp4131_cfg[MCP415x_104] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	{ .compatible = "microchip,mcp4152-502",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		.data = &mcp4131_cfg[MCP415x_502] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	{ .compatible = "microchip,mcp4152-103",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		.data = &mcp4131_cfg[MCP415x_103] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	{ .compatible = "microchip,mcp4152-503",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		.data = &mcp4131_cfg[MCP415x_503] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	{ .compatible = "microchip,mcp4152-104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		.data = &mcp4131_cfg[MCP415x_104] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	{ .compatible = "microchip,mcp4161-502",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		.data = &mcp4131_cfg[MCP416x_502] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	{ .compatible = "microchip,mcp4161-103",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		.data = &mcp4131_cfg[MCP416x_103] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	{ .compatible = "microchip,mcp4161-503",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		.data = &mcp4131_cfg[MCP416x_503] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	{ .compatible = "microchip,mcp4161-104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		.data = &mcp4131_cfg[MCP416x_104] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	{ .compatible = "microchip,mcp4162-502",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		.data = &mcp4131_cfg[MCP416x_502] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	{ .compatible = "microchip,mcp4162-103",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		.data = &mcp4131_cfg[MCP416x_103] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	{ .compatible = "microchip,mcp4162-503",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		.data = &mcp4131_cfg[MCP416x_503] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	{ .compatible = "microchip,mcp4162-104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		.data = &mcp4131_cfg[MCP416x_104] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	{ .compatible = "microchip,mcp4231-502",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		.data = &mcp4131_cfg[MCP423x_502] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	{ .compatible = "microchip,mcp4231-103",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		.data = &mcp4131_cfg[MCP423x_103] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	{ .compatible = "microchip,mcp4231-503",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		.data = &mcp4131_cfg[MCP423x_503] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	{ .compatible = "microchip,mcp4231-104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		.data = &mcp4131_cfg[MCP423x_104] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	{ .compatible = "microchip,mcp4232-502",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		.data = &mcp4131_cfg[MCP423x_502] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	{ .compatible = "microchip,mcp4232-103",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		.data = &mcp4131_cfg[MCP423x_103] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	{ .compatible = "microchip,mcp4232-503",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		.data = &mcp4131_cfg[MCP423x_503] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	{ .compatible = "microchip,mcp4232-104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		.data = &mcp4131_cfg[MCP423x_104] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	{ .compatible = "microchip,mcp4241-502",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		.data = &mcp4131_cfg[MCP424x_502] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	{ .compatible = "microchip,mcp4241-103",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		.data = &mcp4131_cfg[MCP424x_103] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	{ .compatible = "microchip,mcp4241-503",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		.data = &mcp4131_cfg[MCP424x_503] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	{ .compatible = "microchip,mcp4241-104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		.data = &mcp4131_cfg[MCP424x_104] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	{ .compatible = "microchip,mcp4242-502",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		.data = &mcp4131_cfg[MCP424x_502] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	{ .compatible = "microchip,mcp4242-103",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		.data = &mcp4131_cfg[MCP424x_103] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	{ .compatible = "microchip,mcp4242-503",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		.data = &mcp4131_cfg[MCP424x_503] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	{ .compatible = "microchip,mcp4242-104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		.data = &mcp4131_cfg[MCP424x_104] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	{ .compatible = "microchip,mcp4251-502",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		.data = &mcp4131_cfg[MCP425x_502] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	{ .compatible = "microchip,mcp4251-103",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		.data = &mcp4131_cfg[MCP425x_103] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	{ .compatible = "microchip,mcp4251-503",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		.data = &mcp4131_cfg[MCP425x_503] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	{ .compatible = "microchip,mcp4251-104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		.data = &mcp4131_cfg[MCP425x_104] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	{ .compatible = "microchip,mcp4252-502",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		.data = &mcp4131_cfg[MCP425x_502] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	{ .compatible = "microchip,mcp4252-103",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		.data = &mcp4131_cfg[MCP425x_103] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	{ .compatible = "microchip,mcp4252-503",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		.data = &mcp4131_cfg[MCP425x_503] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	{ .compatible = "microchip,mcp4252-104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		.data = &mcp4131_cfg[MCP425x_104] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	{ .compatible = "microchip,mcp4261-502",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		.data = &mcp4131_cfg[MCP426x_502] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	{ .compatible = "microchip,mcp4261-103",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		.data = &mcp4131_cfg[MCP426x_103] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	{ .compatible = "microchip,mcp4261-503",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		.data = &mcp4131_cfg[MCP426x_503] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	{ .compatible = "microchip,mcp4261-104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		.data = &mcp4131_cfg[MCP426x_104] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	{ .compatible = "microchip,mcp4262-502",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		.data = &mcp4131_cfg[MCP426x_502] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	{ .compatible = "microchip,mcp4262-103",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		.data = &mcp4131_cfg[MCP426x_103] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	{ .compatible = "microchip,mcp4262-503",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		.data = &mcp4131_cfg[MCP426x_503] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	{ .compatible = "microchip,mcp4262-104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		.data = &mcp4131_cfg[MCP426x_104] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) MODULE_DEVICE_TABLE(of, mcp4131_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static const struct spi_device_id mcp4131_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	{ "mcp4131-502", MCP413x_502 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	{ "mcp4131-103", MCP413x_103 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	{ "mcp4131-503", MCP413x_503 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	{ "mcp4131-104", MCP413x_104 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	{ "mcp4132-502", MCP413x_502 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	{ "mcp4132-103", MCP413x_103 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	{ "mcp4132-503", MCP413x_503 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	{ "mcp4132-104", MCP413x_104 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	{ "mcp4141-502", MCP414x_502 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	{ "mcp4141-103", MCP414x_103 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	{ "mcp4141-503", MCP414x_503 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	{ "mcp4141-104", MCP414x_104 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	{ "mcp4142-502", MCP414x_502 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	{ "mcp4142-103", MCP414x_103 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	{ "mcp4142-503", MCP414x_503 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	{ "mcp4142-104", MCP414x_104 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	{ "mcp4151-502", MCP415x_502 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	{ "mcp4151-103", MCP415x_103 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	{ "mcp4151-503", MCP415x_503 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	{ "mcp4151-104", MCP415x_104 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	{ "mcp4152-502", MCP415x_502 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	{ "mcp4152-103", MCP415x_103 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	{ "mcp4152-503", MCP415x_503 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	{ "mcp4152-104", MCP415x_104 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	{ "mcp4161-502", MCP416x_502 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	{ "mcp4161-103", MCP416x_103 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	{ "mcp4161-503", MCP416x_503 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	{ "mcp4161-104", MCP416x_104 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	{ "mcp4162-502", MCP416x_502 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	{ "mcp4162-103", MCP416x_103 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	{ "mcp4162-503", MCP416x_503 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	{ "mcp4162-104", MCP416x_104 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	{ "mcp4231-502", MCP423x_502 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	{ "mcp4231-103", MCP423x_103 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	{ "mcp4231-503", MCP423x_503 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	{ "mcp4231-104", MCP423x_104 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	{ "mcp4232-502", MCP423x_502 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	{ "mcp4232-103", MCP423x_103 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	{ "mcp4232-503", MCP423x_503 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	{ "mcp4232-104", MCP423x_104 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	{ "mcp4241-502", MCP424x_502 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	{ "mcp4241-103", MCP424x_103 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	{ "mcp4241-503", MCP424x_503 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	{ "mcp4241-104", MCP424x_104 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	{ "mcp4242-502", MCP424x_502 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	{ "mcp4242-103", MCP424x_103 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	{ "mcp4242-503", MCP424x_503 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	{ "mcp4242-104", MCP424x_104 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	{ "mcp4251-502", MCP425x_502 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	{ "mcp4251-103", MCP425x_103 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	{ "mcp4251-503", MCP425x_503 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	{ "mcp4251-104", MCP425x_104 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	{ "mcp4252-502", MCP425x_502 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	{ "mcp4252-103", MCP425x_103 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	{ "mcp4252-503", MCP425x_503 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	{ "mcp4252-104", MCP425x_104 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	{ "mcp4261-502", MCP426x_502 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	{ "mcp4261-103", MCP426x_103 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	{ "mcp4261-503", MCP426x_503 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	{ "mcp4261-104", MCP426x_104 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	{ "mcp4262-502", MCP426x_502 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	{ "mcp4262-103", MCP426x_103 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	{ "mcp4262-503", MCP426x_503 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	{ "mcp4262-104", MCP426x_104 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) MODULE_DEVICE_TABLE(spi, mcp4131_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static struct spi_driver mcp4131_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 		.name	= "mcp4131",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 		.of_match_table = mcp4131_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	.probe		= mcp4131_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	.id_table	= mcp4131_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) module_spi_driver(mcp4131_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) MODULE_AUTHOR("Slawomir Stepien <sst@poczta.fm>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) MODULE_DESCRIPTION("MCP4131 digital potentiometer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) MODULE_LICENSE("GPL v2");