^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Maxim Integrated MAX5481-MAX5484 digital potentiometer driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2016 Rockwell Collins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Datasheet:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * https://datasheets.maximintegrated.com/en/ds/MAX5481-MAX5484.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* write wiper reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MAX5481_WRITE_WIPER (0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* copy wiper reg to NV reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MAX5481_COPY_AB_TO_NV (2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* copy NV reg to wiper reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MAX5481_COPY_NV_TO_AB (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MAX5481_MAX_POS 1023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) enum max5481_variant {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) max5481,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) max5482,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) max5483,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) max5484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct max5481_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int kohms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const struct max5481_cfg max5481_cfg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) [max5481] = { .kohms = 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) [max5482] = { .kohms = 50, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) [max5483] = { .kohms = 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) [max5484] = { .kohms = 50, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct max5481_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) const struct max5481_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u8 msg[3] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MAX5481_CHANNEL { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .type = IIO_RESISTANCE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .output = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .channel = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static const struct iio_chan_spec max5481_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MAX5481_CHANNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int max5481_write_cmd(struct max5481_data *data, u8 cmd, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct spi_device *spi = data->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) data->msg[0] = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) case MAX5481_WRITE_WIPER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) data->msg[1] = val >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) data->msg[2] = (val & 0x3) << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return spi_write(spi, data->msg, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) case MAX5481_COPY_AB_TO_NV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) case MAX5481_COPY_NV_TO_AB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return spi_write(spi, data->msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int max5481_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct max5481_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (mask != IIO_CHAN_INFO_SCALE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) *val = 1000 * data->cfg->kohms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *val2 = MAX5481_MAX_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return IIO_VAL_FRACTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int max5481_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct max5481_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (mask != IIO_CHAN_INFO_RAW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (val < 0 || val > MAX5481_MAX_POS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return max5481_write_cmd(data, MAX5481_WRITE_WIPER, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const struct iio_info max5481_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .read_raw = max5481_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .write_raw = max5481_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const struct of_device_id max5481_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { .compatible = "maxim,max5481", .data = &max5481_cfg[max5481] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { .compatible = "maxim,max5482", .data = &max5481_cfg[max5482] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { .compatible = "maxim,max5483", .data = &max5481_cfg[max5483] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { .compatible = "maxim,max5484", .data = &max5481_cfg[max5484] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MODULE_DEVICE_TABLE(of, max5481_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int max5481_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct max5481_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) const struct spi_device_id *id = spi_get_device_id(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) dev_set_drvdata(&spi->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) data->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) data->cfg = device_get_match_data(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (!data->cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) data->cfg = &max5481_cfg[id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) indio_dev->name = id->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* variant specific configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) indio_dev->info = &max5481_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) indio_dev->channels = max5481_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) indio_dev->num_channels = ARRAY_SIZE(max5481_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* restore wiper from NV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret = max5481_write_cmd(data, MAX5481_COPY_NV_TO_AB, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int max5481_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct iio_dev *indio_dev = dev_get_drvdata(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct max5481_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* save wiper reg to NV reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return max5481_write_cmd(data, MAX5481_COPY_AB_TO_NV, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const struct spi_device_id max5481_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { "max5481", max5481 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { "max5482", max5482 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { "max5483", max5483 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { "max5484", max5484 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MODULE_DEVICE_TABLE(spi, max5481_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct spi_driver max5481_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .name = "max5481",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .of_match_table = max5481_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .probe = max5481_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .remove = max5481_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .id_table = max5481_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) module_spi_driver(max5481_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MODULE_AUTHOR("Maury Anderson <maury.anderson@rockwellcollins.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MODULE_DESCRIPTION("max5481 SPI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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