Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * MMC35240 - MEMSIC 3-axis Magnetic Sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2015, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * IIO driver for MMC35240 (7-bit I2C slave address 0x30).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * TODO: offset, ACPI, continuous measurement mode, PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MMC35240_DRV_NAME "mmc35240"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MMC35240_REGMAP_NAME "mmc35240_regmap"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MMC35240_REG_XOUT_L	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MMC35240_REG_XOUT_H	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MMC35240_REG_YOUT_L	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MMC35240_REG_YOUT_H	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MMC35240_REG_ZOUT_L	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MMC35240_REG_ZOUT_H	0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MMC35240_REG_STATUS	0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define MMC35240_REG_CTRL0	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MMC35240_REG_CTRL1	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MMC35240_REG_ID		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MMC35240_STATUS_MEAS_DONE_BIT	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MMC35240_CTRL0_REFILL_BIT	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MMC35240_CTRL0_RESET_BIT	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define MMC35240_CTRL0_SET_BIT		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MMC35240_CTRL0_CMM_BIT		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define MMC35240_CTRL0_TM_BIT		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /* output resolution bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MMC35240_CTRL1_BW0_BIT		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define MMC35240_CTRL1_BW1_BIT		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define MMC35240_CTRL1_BW_MASK	 (MMC35240_CTRL1_BW0_BIT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		 MMC35240_CTRL1_BW1_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define MMC35240_CTRL1_BW_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define MMC35240_WAIT_CHARGE_PUMP	50000	/* us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define MMC35240_WAIT_SET_RESET		1000	/* us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * Memsic OTP process code piece is put here for reference:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * #define OTP_CONVERT(REG)  ((float)((REG) >=32 ? (32 - (REG)) : (REG)) * 0.006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * 1) For X axis, the COEFFICIENT is always 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * 2) For Y axis, the COEFFICIENT is as below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  *    f_OTP_matrix[4] = OTP_CONVERT(((reg_data[1] & 0x03) << 4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  *                                   (reg_data[2] >> 4)) + 1.0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  * 3) For Z axis, the COEFFICIENT is as below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  *    f_OTP_matrix[8] = (OTP_CONVERT(reg_data[3] & 0x3f) + 1) * 1.35;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  * We implemented the OTP logic into driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) /* scale = 1000 here for Y otp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define MMC35240_OTP_CONVERT_Y(REG) (((REG) >= 32 ? (32 - (REG)) : (REG)) * 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /* 0.6 * 1.35 = 0.81, scale 10000 for Z otp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define MMC35240_OTP_CONVERT_Z(REG) (((REG) >= 32 ? (32 - (REG)) : (REG)) * 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define MMC35240_X_COEFF(x)	(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define MMC35240_Y_COEFF(y)	(y + 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define MMC35240_Z_COEFF(z)	(z + 13500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define MMC35240_OTP_START_ADDR		0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) enum mmc35240_resolution {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	MMC35240_16_BITS_SLOW = 0, /* 7.92 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	MMC35240_16_BITS_FAST,     /* 4.08 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	MMC35240_14_BITS,          /* 2.16 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	MMC35240_12_BITS,          /* 1.20 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) enum mmc35240_axis {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	AXIS_X = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	AXIS_Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	AXIS_Z,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	int sens[3]; /* sensitivity per X, Y, Z axis */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	int nfo; /* null field output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) } mmc35240_props_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	/* 16 bits, 125Hz ODR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		{1024, 1024, 1024},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		32768,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	/* 16 bits, 250Hz ODR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		{1024, 1024, 770},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		32768,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	/* 14 bits, 450Hz ODR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		{256, 256, 193},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		8192,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	/* 12 bits, 800Hz ODR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		{64, 64, 48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		2048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct mmc35240_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	enum mmc35240_resolution res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	/* OTP compensation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	int axis_coef[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	int axis_scale[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	int val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) } mmc35240_samp_freq[] = { {1, 500000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			   {13, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			   {25, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			   {50, 0} };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("1.5 13 25 50");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MMC35240_CHANNEL(_axis) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.type = IIO_MAGN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.modified = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.channel2 = IIO_MOD_ ## _axis, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.address = AXIS_ ## _axis, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const struct iio_chan_spec mmc35240_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	MMC35240_CHANNEL(X),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	MMC35240_CHANNEL(Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	MMC35240_CHANNEL(Z),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static struct attribute *mmc35240_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	&iio_const_attr_sampling_frequency_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const struct attribute_group mmc35240_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	.attrs = mmc35240_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int mmc35240_get_samp_freq_index(struct mmc35240_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 					int val, int val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	for (i = 0; i < ARRAY_SIZE(mmc35240_samp_freq); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		if (mmc35240_samp_freq[i].val == val &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		    mmc35240_samp_freq[i].val2 == val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int mmc35240_hw_set(struct mmc35240_data *data, bool set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	u8 coil_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	 * Recharge the capacitor at VCAP pin, requested to be issued
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	 * before a SET/RESET command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	ret = regmap_update_bits(data->regmap, MMC35240_REG_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 				 MMC35240_CTRL0_REFILL_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 				 MMC35240_CTRL0_REFILL_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	usleep_range(MMC35240_WAIT_CHARGE_PUMP, MMC35240_WAIT_CHARGE_PUMP + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		coil_bit = MMC35240_CTRL0_SET_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		coil_bit = MMC35240_CTRL0_RESET_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	return regmap_update_bits(data->regmap, MMC35240_REG_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 				  coil_bit, coil_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int mmc35240_init(struct mmc35240_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	int ret, y_convert, z_convert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	unsigned int reg_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	u8 otp_data[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	ret = regmap_read(data->regmap, MMC35240_REG_ID, &reg_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		dev_err(&data->client->dev, "Error reading product id\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	dev_dbg(&data->client->dev, "MMC35240 chip id %x\n", reg_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	 * make sure we restore sensor characteristics, by doing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	 * a SET/RESET sequence, the axis polarity being naturally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	 * aligned after RESET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	ret = mmc35240_hw_set(data, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	usleep_range(MMC35240_WAIT_SET_RESET, MMC35240_WAIT_SET_RESET + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	ret = mmc35240_hw_set(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	/* set default sampling frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	ret = regmap_update_bits(data->regmap, MMC35240_REG_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 				 MMC35240_CTRL1_BW_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 				 data->res << MMC35240_CTRL1_BW_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	ret = regmap_bulk_read(data->regmap, MMC35240_OTP_START_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			       otp_data, sizeof(otp_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	y_convert = MMC35240_OTP_CONVERT_Y(((otp_data[1] & 0x03) << 4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 					   (otp_data[2] >> 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	z_convert = MMC35240_OTP_CONVERT_Z(otp_data[3] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	data->axis_coef[0] = MMC35240_X_COEFF(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	data->axis_coef[1] = MMC35240_Y_COEFF(y_convert);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	data->axis_coef[2] = MMC35240_Z_COEFF(z_convert);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	data->axis_scale[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	data->axis_scale[1] = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	data->axis_scale[2] = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int mmc35240_take_measurement(struct mmc35240_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	int ret, tries = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	unsigned int reg_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	ret = regmap_write(data->regmap, MMC35240_REG_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			   MMC35240_CTRL0_TM_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	while (tries-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		ret = regmap_read(data->regmap, MMC35240_REG_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 				  &reg_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		if (reg_status & MMC35240_STATUS_MEAS_DONE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		/* minimum wait time to complete measurement is 10 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	if (tries < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		dev_err(&data->client->dev, "data not ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int mmc35240_read_measurement(struct mmc35240_data *data, __le16 buf[3])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	ret = mmc35240_take_measurement(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	return regmap_bulk_read(data->regmap, MMC35240_REG_XOUT_L, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 				3 * sizeof(__le16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)  * mmc35240_raw_to_mgauss - convert raw readings to milli gauss. Also apply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)  *			    compensation for output value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)  * @data: device private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)  * @index: axis index for which we want the conversion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)  * @buf: raw data to be converted, 2 bytes in little endian format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)  * @val: compensated output reading (unit is milli gauss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)  * Returns: 0 in case of success, -EINVAL when @index is not valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int mmc35240_raw_to_mgauss(struct mmc35240_data *data, int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 				  __le16 buf[], int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	int raw[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	int sens[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	int nfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	raw[AXIS_X] = le16_to_cpu(buf[AXIS_X]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	raw[AXIS_Y] = le16_to_cpu(buf[AXIS_Y]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	raw[AXIS_Z] = le16_to_cpu(buf[AXIS_Z]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	sens[AXIS_X] = mmc35240_props_table[data->res].sens[AXIS_X];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	sens[AXIS_Y] = mmc35240_props_table[data->res].sens[AXIS_Y];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	sens[AXIS_Z] = mmc35240_props_table[data->res].sens[AXIS_Z];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	nfo = mmc35240_props_table[data->res].nfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	switch (index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	case AXIS_X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		*val = (raw[AXIS_X] - nfo) * 1000 / sens[AXIS_X];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	case AXIS_Y:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		*val = (raw[AXIS_Y] - nfo) * 1000 / sens[AXIS_Y] -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			(raw[AXIS_Z] - nfo)  * 1000 / sens[AXIS_Z];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	case AXIS_Z:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		*val = (raw[AXIS_Y] - nfo) * 1000 / sens[AXIS_Y] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			(raw[AXIS_Z] - nfo) * 1000 / sens[AXIS_Z];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	/* apply OTP compensation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	*val = (*val) * data->axis_coef[index] / data->axis_scale[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static int mmc35240_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 			     struct iio_chan_spec const *chan, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 			     int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	struct mmc35240_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	__le16 buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		ret = mmc35240_read_measurement(data, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		ret = mmc35240_raw_to_mgauss(data, chan->address, buf, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		*val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		*val2 = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		ret = regmap_read(data->regmap, MMC35240_REG_CTRL1, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		i = (reg & MMC35240_CTRL1_BW_MASK) >> MMC35240_CTRL1_BW_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		if (i < 0 || i >= ARRAY_SIZE(mmc35240_samp_freq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		*val = mmc35240_samp_freq[i].val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		*val2 = mmc35240_samp_freq[i].val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static int mmc35240_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 			      struct iio_chan_spec const *chan, int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 			      int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	struct mmc35240_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		i = mmc35240_get_samp_freq_index(data, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		ret = regmap_update_bits(data->regmap, MMC35240_REG_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 					 MMC35240_CTRL1_BW_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 					 i << MMC35240_CTRL1_BW_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static const struct iio_info mmc35240_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	.read_raw	= mmc35240_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	.write_raw	= mmc35240_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	.attrs		= &mmc35240_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static bool mmc35240_is_writeable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	case MMC35240_REG_CTRL0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	case MMC35240_REG_CTRL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static bool mmc35240_is_readable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	case MMC35240_REG_XOUT_L:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	case MMC35240_REG_XOUT_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	case MMC35240_REG_YOUT_L:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	case MMC35240_REG_YOUT_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	case MMC35240_REG_ZOUT_L:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	case MMC35240_REG_ZOUT_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	case MMC35240_REG_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	case MMC35240_REG_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static bool mmc35240_is_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	case MMC35240_REG_CTRL0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	case MMC35240_REG_CTRL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static const struct reg_default mmc35240_reg_defaults[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	{ MMC35240_REG_CTRL0,  0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	{ MMC35240_REG_CTRL1,  0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static const struct regmap_config mmc35240_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	.name = MMC35240_REGMAP_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	.max_register = MMC35240_REG_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	.cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	.writeable_reg = mmc35240_is_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	.readable_reg = mmc35240_is_readable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	.volatile_reg = mmc35240_is_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	.reg_defaults = mmc35240_reg_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	.num_reg_defaults = ARRAY_SIZE(mmc35240_reg_defaults),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static int mmc35240_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 			  const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	struct mmc35240_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	regmap = devm_regmap_init_i2c(client, &mmc35240_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 		dev_err(&client->dev, "regmap initialization failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 		return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	data->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	data->res = MMC35240_16_BITS_SLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	mutex_init(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	indio_dev->info = &mmc35240_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	indio_dev->name = MMC35240_DRV_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	indio_dev->channels = mmc35240_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	indio_dev->num_channels = ARRAY_SIZE(mmc35240_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	ret = mmc35240_init(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 		dev_err(&client->dev, "mmc35240 chip init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	return devm_iio_device_register(&client->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static int mmc35240_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	struct mmc35240_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	regcache_cache_only(data->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static int mmc35240_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	struct mmc35240_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	regcache_mark_dirty(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	ret = regcache_sync_region(data->regmap, MMC35240_REG_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 				   MMC35240_REG_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 		dev_err(dev, "Failed to restore control registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	regcache_cache_only(data->regmap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static const struct dev_pm_ops mmc35240_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	SET_SYSTEM_SLEEP_PM_OPS(mmc35240_suspend, mmc35240_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static const struct of_device_id mmc35240_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	{ .compatible = "memsic,mmc35240", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) MODULE_DEVICE_TABLE(of, mmc35240_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static const struct acpi_device_id mmc35240_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 	{"MMC35240", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) MODULE_DEVICE_TABLE(acpi, mmc35240_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static const struct i2c_device_id mmc35240_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 	{"mmc35240", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) MODULE_DEVICE_TABLE(i2c, mmc35240_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static struct i2c_driver mmc35240_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 		.name = MMC35240_DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 		.of_match_table = mmc35240_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 		.pm = &mmc35240_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 		.acpi_match_table = ACPI_PTR(mmc35240_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 	.probe		= mmc35240_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 	.id_table	= mmc35240_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) module_i2c_driver(mmc35240_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) MODULE_DESCRIPTION("MEMSIC MMC35240 magnetic sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) MODULE_LICENSE("GPL v2");