^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for the Asahi Kasei EMD Corporation AK8974
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * and Aichi Steel AMI305 magnetometer chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Based on a patch from Samu Onkalo and the AK8975 IIO driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2010 Nokia Corporation and/or its subsidiary(-ies).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2010 NVIDIA Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2016 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Author: Samu Onkalo <samu.p.onkalo@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Author: Linus Walleij <linus.walleij@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/irq.h> /* For irq_get_irq_data() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/iio/trigger.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * 16-bit registers are little-endian. LSB is at the address defined below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * and MSB is at the next higher address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* These registers are common for AK8974 and AMI30x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AK8974_SELFTEST 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AK8974_SELFTEST_IDLE 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AK8974_SELFTEST_OK 0xAA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AK8974_INFO 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AK8974_WHOAMI 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AK8974_WHOAMI_VALUE_AMI306 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AK8974_WHOAMI_VALUE_AMI305 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AK8974_WHOAMI_VALUE_AK8974 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AK8974_WHOAMI_VALUE_HSCDTD008A 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AK8974_DATA_X 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AK8974_DATA_Y 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AK8974_DATA_Z 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AK8974_INT_SRC 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AK8974_STATUS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AK8974_INT_CLEAR 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AK8974_CTRL1 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AK8974_CTRL2 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AK8974_CTRL3 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AK8974_INT_CTRL 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AK8974_INT_THRES 0x26 /* Absolute any axis value threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AK8974_PRESET 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* AK8974-specific offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AK8974_OFFSET_X 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AK8974_OFFSET_Y 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AK8974_OFFSET_Z 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* AMI305-specific offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AMI305_OFFSET_X 0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AMI305_OFFSET_Y 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define AMI305_OFFSET_Z 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Different temperature registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AK8974_TEMP 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AMI305_TEMP 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* AMI306-specific control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define AMI306_CTRL4 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* AMI306 factory calibration data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* fine axis sensitivity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define AMI306_FINEOUTPUT_X 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AMI306_FINEOUTPUT_Y 0x92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define AMI306_FINEOUTPUT_Z 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* axis sensitivity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define AMI306_SENS_X 0x96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define AMI306_SENS_Y 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define AMI306_SENS_Z 0x9A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* axis cross-interference */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define AMI306_GAIN_PARA_XZ 0x9C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define AMI306_GAIN_PARA_XY 0x9D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AMI306_GAIN_PARA_YZ 0x9E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AMI306_GAIN_PARA_YX 0x9F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AMI306_GAIN_PARA_ZY 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AMI306_GAIN_PARA_ZX 0xA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* offset at ZERO magnetic field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AMI306_OFFZERO_X 0xF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AMI306_OFFZERO_Y 0xFA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AMI306_OFFZERO_Z 0xFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define AK8974_INT_X_HIGH BIT(7) /* Axis over +threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AK8974_INT_Y_HIGH BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AK8974_INT_Z_HIGH BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define AK8974_INT_X_LOW BIT(4) /* Axis below -threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AK8974_INT_Y_LOW BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define AK8974_INT_Z_LOW BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define AK8974_INT_RANGE BIT(1) /* Range overflow (any axis) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define AK8974_STATUS_DRDY BIT(6) /* Data ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AK8974_STATUS_OVERRUN BIT(5) /* Data overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AK8974_STATUS_INT BIT(4) /* Interrupt occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define AK8974_CTRL1_POWER BIT(7) /* 0 = standby; 1 = active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define AK8974_CTRL1_RATE BIT(4) /* 0 = 10 Hz; 1 = 20 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define AK8974_CTRL1_FORCE_EN BIT(1) /* 0 = normal; 1 = force */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define AK8974_CTRL1_MODE2 BIT(0) /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define AK8974_CTRL2_INT_EN BIT(4) /* 1 = enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define AK8974_CTRL2_DRDY_EN BIT(3) /* 1 = enable data ready signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define AK8974_CTRL2_DRDY_POL BIT(2) /* 1 = data ready active high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define AK8974_CTRL2_RESDEF (AK8974_CTRL2_DRDY_POL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define AK8974_CTRL3_RESET BIT(7) /* Software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define AK8974_CTRL3_FORCE BIT(6) /* Start forced measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define AK8974_CTRL3_SELFTEST BIT(4) /* Set selftest register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define AK8974_CTRL3_RESDEF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define AK8974_INT_CTRL_XEN BIT(7) /* Enable interrupt for this axis */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define AK8974_INT_CTRL_YEN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define AK8974_INT_CTRL_ZEN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AK8974_INT_CTRL_XYZEN (BIT(7)|BIT(6)|BIT(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define AK8974_INT_CTRL_POL BIT(3) /* 0 = active low; 1 = active high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define AK8974_INT_CTRL_PULSE BIT(1) /* 0 = latched; 1 = pulse (50 usec) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define AK8974_INT_CTRL_RESDEF (AK8974_INT_CTRL_XYZEN | AK8974_INT_CTRL_POL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* HSCDTD008A-specific control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define HSCDTD008A_CTRL4 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define HSCDTD008A_CTRL4_MMD BIT(7) /* must be set to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define HSCDTD008A_CTRL4_RANGE BIT(4) /* 0 = 14-bit output; 1 = 15-bit output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define HSCDTD008A_CTRL4_RESDEF (HSCDTD008A_CTRL4_MMD | HSCDTD008A_CTRL4_RANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* The AMI305 has elaborate FW version and serial number registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define AMI305_VER 0xE8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define AMI305_SN 0xEA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define AK8974_MAX_RANGE 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define AK8974_POWERON_DELAY 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define AK8974_ACTIVATE_DELAY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define AK8974_SELFTEST_DELAY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * Set the autosuspend to two orders of magnitude larger than the poweron
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * delay to make sane reasonable power tradeoff savings (5 seconds in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * this case).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define AK8974_AUTOSUSPEND_DELAY 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define AK8974_MEASTIME 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define AK8974_PWR_ON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define AK8974_PWR_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * struct ak8974 - state container for the AK8974 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @i2c: parent I2C client
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * @orientation: mounting matrix, flipped axis etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * @map: regmap to access the AK8974 registers over I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * @regs: the avdd and dvdd power regulators
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * @name: the name of the part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * @variant: the whoami ID value (for selecting code paths)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * @lock: locks the magnetometer for exclusive use during a measurement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @drdy_irq: uses the DRDY IRQ line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * @drdy_complete: completion for DRDY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * @drdy_active_low: the DRDY IRQ is active low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * @scan: timestamps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct ak8974 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct i2c_client *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct iio_mount_matrix orientation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct regulator_bulk_data regs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u8 variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) bool drdy_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct completion drdy_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) bool drdy_active_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Ensure timestamp is naturally aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) __le16 channels[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) s64 ts __aligned(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) } scan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const char ak8974_reg_avdd[] = "avdd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static const char ak8974_reg_dvdd[] = "dvdd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int ak8974_get_u16_val(struct ak8974 *ak8974, u8 reg, u16 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) __le16 bulk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ret = regmap_bulk_read(ak8974->map, reg, &bulk, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) *val = le16_to_cpu(bulk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int ak8974_set_u16_val(struct ak8974 *ak8974, u8 reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) __le16 bulk = cpu_to_le16(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return regmap_bulk_write(ak8974->map, reg, &bulk, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int ak8974_set_power(struct ak8974 *ak8974, bool mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) val = mode ? AK8974_CTRL1_POWER : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) val |= AK8974_CTRL1_FORCE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ret = regmap_write(ak8974->map, AK8974_CTRL1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) msleep(AK8974_ACTIVATE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int ak8974_reset(struct ak8974 *ak8974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Power on to get register access. Sets CTRL1 reg to reset state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ret = ak8974_set_power(ak8974, AK8974_PWR_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret = regmap_write(ak8974->map, AK8974_CTRL2, AK8974_CTRL2_RESDEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ret = regmap_write(ak8974->map, AK8974_CTRL3, AK8974_CTRL3_RESDEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (ak8974->variant != AK8974_WHOAMI_VALUE_HSCDTD008A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ret = regmap_write(ak8974->map, AK8974_INT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) AK8974_INT_CTRL_RESDEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ret = regmap_write(ak8974->map, HSCDTD008A_CTRL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) HSCDTD008A_CTRL4_RESDEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* After reset, power off is default state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return ak8974_set_power(ak8974, AK8974_PWR_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int ak8974_configure(struct ak8974 *ak8974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ret = regmap_write(ak8974->map, AK8974_CTRL2, AK8974_CTRL2_DRDY_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) AK8974_CTRL2_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ret = regmap_write(ak8974->map, AK8974_CTRL3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (ak8974->variant == AK8974_WHOAMI_VALUE_AMI306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* magic from datasheet: set high-speed measurement mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ret = ak8974_set_u16_val(ak8974, AMI306_CTRL4, 0xA07E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (ak8974->variant == AK8974_WHOAMI_VALUE_HSCDTD008A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ret = regmap_write(ak8974->map, AK8974_INT_CTRL, AK8974_INT_CTRL_POL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return regmap_write(ak8974->map, AK8974_PRESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int ak8974_trigmeas(struct ak8974 *ak8974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned int clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u8 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Clear any previous measurement overflow status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ret = regmap_read(ak8974->map, AK8974_INT_CLEAR, &clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* If we have a DRDY IRQ line, use it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (ak8974->drdy_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) mask = AK8974_CTRL2_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) AK8974_CTRL2_DRDY_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) AK8974_CTRL2_DRDY_POL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) val = AK8974_CTRL2_DRDY_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (!ak8974->drdy_active_low)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) val |= AK8974_CTRL2_DRDY_POL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) init_completion(&ak8974->drdy_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ret = regmap_update_bits(ak8974->map, AK8974_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Force a measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return regmap_update_bits(ak8974->map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) AK8974_CTRL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) AK8974_CTRL3_FORCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) AK8974_CTRL3_FORCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int ak8974_await_drdy(struct ak8974 *ak8974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int timeout = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (ak8974->drdy_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ret = wait_for_completion_timeout(&ak8974->drdy_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 1 + msecs_to_jiffies(1000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) dev_err(&ak8974->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) "timeout waiting for DRDY IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* Default delay-based poll loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) msleep(AK8974_MEASTIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ret = regmap_read(ak8974->map, AK8974_STATUS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (val & AK8974_STATUS_DRDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) } while (--timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dev_err(&ak8974->i2c->dev, "timeout waiting for DRDY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static int ak8974_getresult(struct ak8974 *ak8974, __le16 *result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned int src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ret = ak8974_await_drdy(ak8974);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = regmap_read(ak8974->map, AK8974_INT_SRC, &src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Out of range overflow! Strong magnet close? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (src & AK8974_INT_RANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dev_err(&ak8974->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) "range overflow in sensor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ret = regmap_bulk_read(ak8974->map, AK8974_DATA_X, result, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static irqreturn_t ak8974_drdy_irq(int irq, void *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct ak8974 *ak8974 = d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (!ak8974->drdy_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* TODO: timestamp here to get good measurement stamps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static irqreturn_t ak8974_drdy_irq_thread(int irq, void *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct ak8974 *ak8974 = d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Check if this was a DRDY from us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ret = regmap_read(ak8974->map, AK8974_STATUS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) dev_err(&ak8974->i2c->dev, "error reading DRDY status\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (val & AK8974_STATUS_DRDY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* Yes this was our IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) complete(&ak8974->drdy_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* We may be on a shared IRQ, let the next client check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static int ak8974_selftest(struct ak8974 *ak8974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct device *dev = &ak8974->i2c->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ret = regmap_read(ak8974->map, AK8974_SELFTEST, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (val != AK8974_SELFTEST_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dev_err(dev, "selftest not idle before test\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Trigger self-test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ret = regmap_update_bits(ak8974->map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) AK8974_CTRL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) AK8974_CTRL3_SELFTEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) AK8974_CTRL3_SELFTEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_err(dev, "could not write CTRL3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) msleep(AK8974_SELFTEST_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ret = regmap_read(ak8974->map, AK8974_SELFTEST, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (val != AK8974_SELFTEST_OK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) dev_err(dev, "selftest result NOT OK (%02x)\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ret = regmap_read(ak8974->map, AK8974_SELFTEST, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (val != AK8974_SELFTEST_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dev_err(dev, "selftest not idle after test (%02x)\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dev_dbg(dev, "passed self-test\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static void ak8974_read_calib_data(struct ak8974 *ak8974, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) __le16 *tab, size_t tab_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int ret = regmap_bulk_read(ak8974->map, reg, tab, tab_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) memset(tab, 0xFF, tab_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dev_warn(&ak8974->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) "can't read calibration data (regs %u..%zu): %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) reg, reg + tab_size - 1, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) add_device_randomness(tab, tab_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static int ak8974_detect(struct ak8974 *ak8974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) unsigned int whoami;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) unsigned int fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u16 sn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ret = regmap_read(ak8974->map, AK8974_WHOAMI, &whoami);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) name = "ami305";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) switch (whoami) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) case AK8974_WHOAMI_VALUE_AMI306:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) name = "ami306";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) case AK8974_WHOAMI_VALUE_AMI305:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ret = regmap_read(ak8974->map, AMI305_VER, &fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) fw &= 0x7f; /* only bits 0 thru 6 valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ret = ak8974_get_u16_val(ak8974, AMI305_SN, &sn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) add_device_randomness(&sn, sizeof(sn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) dev_info(&ak8974->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) "detected %s, FW ver %02x, S/N: %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) name, fw, sn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) case AK8974_WHOAMI_VALUE_AK8974:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) name = "ak8974";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dev_info(&ak8974->i2c->dev, "detected AK8974\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) case AK8974_WHOAMI_VALUE_HSCDTD008A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) name = "hscdtd008a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev_info(&ak8974->i2c->dev, "detected hscdtd008a\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) dev_err(&ak8974->i2c->dev, "unsupported device (%02x) ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) whoami);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ak8974->name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ak8974->variant = whoami;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (whoami == AK8974_WHOAMI_VALUE_AMI306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) __le16 fab_data1[9], fab_data2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ak8974_read_calib_data(ak8974, AMI306_FINEOUTPUT_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) fab_data1, sizeof(fab_data1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ak8974_read_calib_data(ak8974, AMI306_OFFZERO_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) fab_data2, sizeof(fab_data2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) for (i = 0; i < 3; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static const char axis[3] = "XYZ";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static const char pgaxis[6] = "ZYZXYX";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) unsigned offz = le16_to_cpu(fab_data2[i]) & 0x7F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) unsigned fine = le16_to_cpu(fab_data1[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) unsigned sens = le16_to_cpu(fab_data1[i + 3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) unsigned pgain1 = le16_to_cpu(fab_data1[i + 6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) unsigned pgain2 = pgain1 >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) pgain1 &= 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) dev_info(&ak8974->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) "factory calibration for axis %c: offz=%u sens=%u fine=%u pga%c=%u pga%c=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) axis[i], offz, sens, fine, pgaxis[i * 2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) pgain1, pgaxis[i * 2 + 1], pgain2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static int ak8974_measure_channel(struct ak8974 *ak8974, unsigned long address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) __le16 hw_values[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) pm_runtime_get_sync(&ak8974->i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) mutex_lock(&ak8974->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * We read all axes and discard all but one, for optimized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * reading, use the triggered buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ret = ak8974_trigmeas(ak8974);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) ret = ak8974_getresult(ak8974, hw_values);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * This explicit cast to (s16) is necessary as the measurement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * is done in 2's complement with positive and negative values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * The follwing assignment to *val will then convert the signed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * s16 value to a signed int value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) *val = (s16)le16_to_cpu(hw_values[address]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) mutex_unlock(&ak8974->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) pm_runtime_mark_last_busy(&ak8974->i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) pm_runtime_put_autosuspend(&ak8974->i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static int ak8974_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) int *val, int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct ak8974 *ak8974 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (chan->address > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) dev_err(&ak8974->i2c->dev, "faulty channel address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ret = ak8974_measure_channel(ak8974, chan->address, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) switch (ak8974->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) case AK8974_WHOAMI_VALUE_AMI306:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) case AK8974_WHOAMI_VALUE_AMI305:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * The datasheet for AMI305 and AMI306, page 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * specifies the range of the sensor to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * +/- 12 Gauss.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) *val = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * 12 bits are used, +/- 2^11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * [ -2048 .. 2047 ] (manual page 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * [ 0xf800 .. 0x07ff ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) *val2 = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) case AK8974_WHOAMI_VALUE_HSCDTD008A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * The datasheet for HSCDTF008A, page 3 specifies the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * range of the sensor as +/- 2.4 mT per axis, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * corresponds to +/- 2400 uT = +/- 24 Gauss.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) *val = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * 15 bits are used (set up in CTRL4), +/- 2^14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * [ -16384 .. 16383 ] (manual page 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * [ 0xc000 .. 0x3fff ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) *val2 = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* GUESSING +/- 12 Gauss */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) *val = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* GUESSING 12 bits ADC +/- 2^11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) *val2 = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* Unknown request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static void ak8974_fill_buffer(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct ak8974 *ak8974 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) pm_runtime_get_sync(&ak8974->i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) mutex_lock(&ak8974->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ret = ak8974_trigmeas(ak8974);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) dev_err(&ak8974->i2c->dev, "error triggering measure\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ret = ak8974_getresult(ak8974, ak8974->scan.channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dev_err(&ak8974->i2c->dev, "error getting measures\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) iio_push_to_buffers_with_timestamp(indio_dev, &ak8974->scan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) mutex_unlock(&ak8974->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) pm_runtime_mark_last_busy(&ak8974->i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) pm_runtime_put_autosuspend(&ak8974->i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static irqreturn_t ak8974_handle_trigger(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) const struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ak8974_fill_buffer(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static const struct iio_mount_matrix *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ak8974_get_mount_matrix(const struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) const struct iio_chan_spec *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct ak8974 *ak8974 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return &ak8974->orientation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static const struct iio_chan_spec_ext_info ak8974_ext_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, ak8974_get_mount_matrix),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define AK8974_AXIS_CHANNEL(axis, index, bits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .type = IIO_MAGN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .modified = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .channel2 = IIO_MOD_##axis, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .ext_info = ak8974_ext_info, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .address = index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .scan_index = index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .sign = 's', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .realbits = bits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .endianness = IIO_LE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * We have no datasheet for the AK8974 but we guess that its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * ADC is 12 bits. The AMI305 and AMI306 certainly has 12bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * ADC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static const struct iio_chan_spec ak8974_12_bits_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) AK8974_AXIS_CHANNEL(X, 0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) AK8974_AXIS_CHANNEL(Y, 1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) AK8974_AXIS_CHANNEL(Z, 2, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) IIO_CHAN_SOFT_TIMESTAMP(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * The HSCDTD008A has 15 bits resolution the way we set it up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * in CTRL4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static const struct iio_chan_spec ak8974_15_bits_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) AK8974_AXIS_CHANNEL(X, 0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) AK8974_AXIS_CHANNEL(Y, 1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) AK8974_AXIS_CHANNEL(Z, 2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) IIO_CHAN_SOFT_TIMESTAMP(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static const unsigned long ak8974_scan_masks[] = { 0x7, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static const struct iio_info ak8974_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .read_raw = &ak8974_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static bool ak8974_writeable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct i2c_client *i2c = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) struct iio_dev *indio_dev = i2c_get_clientdata(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct ak8974 *ak8974 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) case AK8974_CTRL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) case AK8974_CTRL2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) case AK8974_CTRL3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) case AK8974_INT_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) case AK8974_INT_THRES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) case AK8974_INT_THRES + 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) case AK8974_PRESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) case AK8974_PRESET + 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return ak8974->variant != AK8974_WHOAMI_VALUE_HSCDTD008A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) case AK8974_OFFSET_X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) case AK8974_OFFSET_X + 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) case AK8974_OFFSET_Y:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) case AK8974_OFFSET_Y + 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) case AK8974_OFFSET_Z:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) case AK8974_OFFSET_Z + 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return ak8974->variant == AK8974_WHOAMI_VALUE_AK8974 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) ak8974->variant == AK8974_WHOAMI_VALUE_HSCDTD008A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) case AMI305_OFFSET_X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) case AMI305_OFFSET_X + 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) case AMI305_OFFSET_Y:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) case AMI305_OFFSET_Y + 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) case AMI305_OFFSET_Z:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) case AMI305_OFFSET_Z + 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return ak8974->variant == AK8974_WHOAMI_VALUE_AMI305 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ak8974->variant == AK8974_WHOAMI_VALUE_AMI306;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) case AMI306_CTRL4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) case AMI306_CTRL4 + 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return ak8974->variant == AK8974_WHOAMI_VALUE_AMI306;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static bool ak8974_precious_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return reg == AK8974_INT_CLEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static const struct regmap_config ak8974_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .max_register = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .writeable_reg = ak8974_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .precious_reg = ak8974_precious_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static int ak8974_probe(struct i2c_client *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct ak8974 *ak8974;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) unsigned long irq_trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) int irq = i2c->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* Register with IIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) indio_dev = devm_iio_device_alloc(&i2c->dev, sizeof(*ak8974));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (indio_dev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) ak8974 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) i2c_set_clientdata(i2c, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ak8974->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) mutex_init(&ak8974->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) ret = iio_read_mount_matrix(&i2c->dev, "mount-matrix",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) &ak8974->orientation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) ak8974->regs[0].supply = ak8974_reg_avdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) ak8974->regs[1].supply = ak8974_reg_dvdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ret = devm_regulator_bulk_get(&i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ARRAY_SIZE(ak8974->regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ak8974->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return dev_err_probe(&i2c->dev, ret, "cannot get regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ret = regulator_bulk_enable(ARRAY_SIZE(ak8974->regs), ak8974->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) dev_err(&i2c->dev, "cannot enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* Take runtime PM online */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) pm_runtime_get_noresume(&i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) pm_runtime_set_active(&i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) pm_runtime_enable(&i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ak8974->map = devm_regmap_init_i2c(i2c, &ak8974_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (IS_ERR(ak8974->map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) dev_err(&i2c->dev, "failed to allocate register map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) pm_runtime_put_noidle(&i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) pm_runtime_disable(&i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return PTR_ERR(ak8974->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) ret = ak8974_set_power(ak8974, AK8974_PWR_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) dev_err(&i2c->dev, "could not power on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) goto disable_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) ret = ak8974_detect(ak8974);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) dev_err(&i2c->dev, "neither AK8974 nor AMI30x found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) goto disable_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ret = ak8974_selftest(ak8974);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) dev_err(&i2c->dev, "selftest failed (continuing anyway)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) ret = ak8974_reset(ak8974);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) dev_err(&i2c->dev, "AK8974 reset failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) goto disable_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) switch (ak8974->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) case AK8974_WHOAMI_VALUE_AMI306:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) case AK8974_WHOAMI_VALUE_AMI305:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) indio_dev->channels = ak8974_12_bits_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) indio_dev->num_channels = ARRAY_SIZE(ak8974_12_bits_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) case AK8974_WHOAMI_VALUE_HSCDTD008A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) indio_dev->channels = ak8974_15_bits_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) indio_dev->num_channels = ARRAY_SIZE(ak8974_15_bits_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) indio_dev->channels = ak8974_12_bits_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) indio_dev->num_channels = ARRAY_SIZE(ak8974_12_bits_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) indio_dev->info = &ak8974_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) indio_dev->available_scan_masks = ak8974_scan_masks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) indio_dev->name = ak8974->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) ret = iio_triggered_buffer_setup(indio_dev, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) ak8974_handle_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) dev_err(&i2c->dev, "triggered buffer setup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) goto disable_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /* If we have a valid DRDY IRQ, make use of it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (irq_trig == IRQF_TRIGGER_RISING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) dev_info(&i2c->dev, "enable rising edge DRDY IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) } else if (irq_trig == IRQF_TRIGGER_FALLING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ak8974->drdy_active_low = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) dev_info(&i2c->dev, "enable falling edge DRDY IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) irq_trig = IRQF_TRIGGER_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) irq_trig |= IRQF_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) irq_trig |= IRQF_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) ret = devm_request_threaded_irq(&i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) ak8974_drdy_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) ak8974_drdy_irq_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) irq_trig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) ak8974->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) ak8974);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) dev_err(&i2c->dev, "unable to request DRDY IRQ "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) "- proceeding without IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) goto no_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) ak8974->drdy_irq = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) no_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) dev_err(&i2c->dev, "device register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) goto cleanup_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) pm_runtime_set_autosuspend_delay(&i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) AK8974_AUTOSUSPEND_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) pm_runtime_use_autosuspend(&i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) pm_runtime_put(&i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) cleanup_buffer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) disable_pm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) pm_runtime_put_noidle(&i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) pm_runtime_disable(&i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) ak8974_set_power(ak8974, AK8974_PWR_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) regulator_bulk_disable(ARRAY_SIZE(ak8974->regs), ak8974->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static int ak8974_remove(struct i2c_client *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) struct iio_dev *indio_dev = i2c_get_clientdata(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) struct ak8974 *ak8974 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) pm_runtime_get_sync(&i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) pm_runtime_put_noidle(&i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) pm_runtime_disable(&i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) ak8974_set_power(ak8974, AK8974_PWR_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) regulator_bulk_disable(ARRAY_SIZE(ak8974->regs), ak8974->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) static int __maybe_unused ak8974_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct ak8974 *ak8974 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) iio_priv(i2c_get_clientdata(to_i2c_client(dev)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ak8974_set_power(ak8974, AK8974_PWR_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) regulator_bulk_disable(ARRAY_SIZE(ak8974->regs), ak8974->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) static int __maybe_unused ak8974_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) struct ak8974 *ak8974 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) iio_priv(i2c_get_clientdata(to_i2c_client(dev)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) ret = regulator_bulk_enable(ARRAY_SIZE(ak8974->regs), ak8974->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) msleep(AK8974_POWERON_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) ret = ak8974_set_power(ak8974, AK8974_PWR_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) goto out_regulator_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) ret = ak8974_configure(ak8974);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) goto out_disable_power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) out_disable_power:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) ak8974_set_power(ak8974, AK8974_PWR_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) out_regulator_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) regulator_bulk_disable(ARRAY_SIZE(ak8974->regs), ak8974->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static const struct dev_pm_ops ak8974_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) SET_RUNTIME_PM_OPS(ak8974_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) ak8974_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) static const struct i2c_device_id ak8974_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) {"ami305", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) {"ami306", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) {"ak8974", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) {"hscdtd008a", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) MODULE_DEVICE_TABLE(i2c, ak8974_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) static const struct of_device_id ak8974_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) { .compatible = "asahi-kasei,ak8974", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) { .compatible = "alps,hscdtd008a", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) MODULE_DEVICE_TABLE(of, ak8974_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static struct i2c_driver ak8974_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .name = "ak8974",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .pm = &ak8974_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .of_match_table = ak8974_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .probe = ak8974_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .remove = ak8974_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .id_table = ak8974_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) module_i2c_driver(ak8974_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) MODULE_DESCRIPTION("AK8974 and AMI30x 3-axis magnetometer driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) MODULE_AUTHOR("Samu Onkalo");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) MODULE_AUTHOR("Linus Walleij");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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