Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * VCNL4035 Ambient Light and Proximity Sensor - 7-bit I2C slave address 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2018, DENX Software Engineering GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Parthiban Nallathambi <pn@denx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * TODO: Proximity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/iio/events.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/iio/trigger.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define VCNL4035_DRV_NAME	"vcnl4035"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define VCNL4035_IRQ_NAME	"vcnl4035_event"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define VCNL4035_REGMAP_NAME	"vcnl4035_regmap"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* Device registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define VCNL4035_ALS_CONF	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define VCNL4035_ALS_THDH	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define VCNL4035_ALS_THDL	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define VCNL4035_ALS_DATA	0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define VCNL4035_WHITE_DATA	0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define VCNL4035_INT_FLAG	0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define VCNL4035_DEV_ID		0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) /* Register masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define VCNL4035_MODE_ALS_MASK		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define VCNL4035_MODE_ALS_WHITE_CHAN	BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define VCNL4035_MODE_ALS_INT_MASK	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define VCNL4035_ALS_IT_MASK		GENMASK(7, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define VCNL4035_ALS_PERS_MASK		GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define VCNL4035_INT_ALS_IF_H_MASK	BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define VCNL4035_INT_ALS_IF_L_MASK	BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /* Default values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define VCNL4035_MODE_ALS_ENABLE	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define VCNL4035_MODE_ALS_DISABLE	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define VCNL4035_MODE_ALS_INT_ENABLE	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define VCNL4035_MODE_ALS_INT_DISABLE	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define VCNL4035_DEV_ID_VAL		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define VCNL4035_ALS_IT_DEFAULT		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define VCNL4035_ALS_PERS_DEFAULT	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define VCNL4035_ALS_THDH_DEFAULT	5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define VCNL4035_ALS_THDL_DEFAULT	100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define VCNL4035_SLEEP_DELAY_MS		2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) struct vcnl4035_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	unsigned int als_it_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	unsigned int als_persistence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	unsigned int als_thresh_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	unsigned int als_thresh_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct iio_trigger *drdy_trigger0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static inline bool vcnl4035_is_triggered(struct vcnl4035_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	ret = regmap_read(data->regmap, VCNL4035_INT_FLAG, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	return !!(reg &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		(VCNL4035_INT_ALS_IF_H_MASK | VCNL4035_INT_ALS_IF_L_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static irqreturn_t vcnl4035_drdy_irq_thread(int irq, void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	struct iio_dev *indio_dev = private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct vcnl4035_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	if (vcnl4035_is_triggered(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		iio_push_event(indio_dev, IIO_UNMOD_EVENT_CODE(IIO_LIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 							0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 							IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 							IIO_EV_DIR_EITHER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 				iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		iio_trigger_poll_chained(data->drdy_trigger0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) /* Triggered buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static irqreturn_t vcnl4035_trigger_consumer_handler(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	struct vcnl4035_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	/* Ensure naturally aligned timestamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	u8 buffer[ALIGN(sizeof(u16), sizeof(s64)) + sizeof(s64)]  __aligned(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	ret = regmap_read(data->regmap, VCNL4035_ALS_DATA, (int *)buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		dev_err(&data->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			"Trigger consumer can't read from sensor.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		goto fail_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	iio_push_to_buffers_with_timestamp(indio_dev, buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 					iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) fail_read:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int vcnl4035_als_drdy_set_state(struct iio_trigger *trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 					bool enable_drdy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	struct iio_dev *indio_dev = iio_trigger_get_drvdata(trigger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	struct vcnl4035_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	int val = enable_drdy ? VCNL4035_MODE_ALS_INT_ENABLE :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 					VCNL4035_MODE_ALS_INT_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	return regmap_update_bits(data->regmap, VCNL4035_ALS_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 				 VCNL4035_MODE_ALS_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 				 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const struct iio_trigger_ops vcnl4035_trigger_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.validate_device = iio_trigger_validate_own_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.set_trigger_state = vcnl4035_als_drdy_set_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int vcnl4035_set_pm_runtime_state(struct vcnl4035_data *data, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	struct device *dev = &data->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		ret = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			pm_runtime_put_noidle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		pm_runtime_mark_last_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		ret = pm_runtime_put_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  *	Device IT	INT Time (ms)	Scale (lux/step)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  *	000		50		0.064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  *	001		100		0.032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  *	010		200		0.016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  *	100		400		0.008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  *	101 - 111	800		0.004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  * Values are proportional, so ALS INT is selected for input due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)  * simplicity reason. Integration time value and scaling is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  * calculated based on device INT value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)  * Raw value needs to be scaled using ALS steps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int vcnl4035_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			    struct iio_chan_spec const *chan, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			    int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	struct vcnl4035_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	int raw_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		ret = vcnl4035_set_pm_runtime_state(data, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		if  (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		ret = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			if (chan->channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 				reg = VCNL4035_ALS_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 				reg = VCNL4035_WHITE_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			ret = regmap_read(data->regmap, reg, &raw_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 				*val = raw_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 				ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		vcnl4035_set_pm_runtime_state(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	case IIO_CHAN_INFO_INT_TIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		*val = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		if (data->als_it_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			*val = data->als_it_val * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		*val = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		if (!data->als_it_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			*val2 = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			*val2 = data->als_it_val * 2 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		return IIO_VAL_FRACTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int vcnl4035_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 				struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 				int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	struct vcnl4035_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	case IIO_CHAN_INFO_INT_TIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		if (val <= 0 || val > 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		ret = vcnl4035_set_pm_runtime_state(data, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		if  (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		ret = regmap_update_bits(data->regmap, VCNL4035_ALS_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 					 VCNL4035_ALS_IT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 					 val / 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			data->als_it_val = val / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		vcnl4035_set_pm_runtime_state(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* No direct ABI for persistence and threshold, so eventing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int vcnl4035_read_thresh(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		enum iio_event_direction dir, enum iio_event_info info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		int *val, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	struct vcnl4035_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	case IIO_EV_INFO_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		switch (dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		case IIO_EV_DIR_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			*val = data->als_thresh_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		case IIO_EV_DIR_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			*val = data->als_thresh_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	case IIO_EV_INFO_PERIOD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		*val = data->als_persistence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int vcnl4035_write_thresh(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		enum iio_event_direction dir, enum iio_event_info info, int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		int val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	struct vcnl4035_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	case IIO_EV_INFO_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		/* 16 bit threshold range 0 - 65535 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		if (val < 0 || val > 65535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		if (dir == IIO_EV_DIR_RISING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			if (val < data->als_thresh_low)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 				return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 			ret = regmap_write(data->regmap, VCNL4035_ALS_THDH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 					   val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 			data->als_thresh_high = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 			if (val > data->als_thresh_high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 				return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			ret = regmap_write(data->regmap, VCNL4035_ALS_THDL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 					   val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 			if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 			data->als_thresh_low = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	case IIO_EV_INFO_PERIOD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		/* allow only 1 2 4 8 as persistence value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		if (val < 0 || val > 8 || hweight8(val) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		ret = regmap_update_bits(data->regmap, VCNL4035_ALS_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 					 VCNL4035_ALS_PERS_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 			data->als_persistence = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static IIO_CONST_ATTR_INT_TIME_AVAIL("50 100 200 400 800");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static struct attribute *vcnl4035_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	&iio_const_attr_integration_time_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const struct attribute_group vcnl4035_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	.attrs = vcnl4035_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static const struct iio_info vcnl4035_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	.read_raw		= vcnl4035_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	.write_raw		= vcnl4035_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	.read_event_value	= vcnl4035_read_thresh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	.write_event_value	= vcnl4035_write_thresh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	.attrs			= &vcnl4035_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static const struct iio_event_spec vcnl4035_event_spec[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		.type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		.dir = IIO_EV_DIR_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		.mask_separate = BIT(IIO_EV_INFO_VALUE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		.type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		.dir = IIO_EV_DIR_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		.mask_separate = BIT(IIO_EV_INFO_VALUE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		.type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		.dir = IIO_EV_DIR_EITHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		.mask_separate = BIT(IIO_EV_INFO_PERIOD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) enum vcnl4035_scan_index_order {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	VCNL4035_CHAN_INDEX_LIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	VCNL4035_CHAN_INDEX_WHITE_LED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static const struct iio_buffer_setup_ops iio_triggered_buffer_setup_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	.validate_scan_mask = &iio_validate_scan_mask_onehot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const struct iio_chan_spec vcnl4035_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		.type = IIO_LIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		.channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 				BIT(IIO_CHAN_INFO_INT_TIME) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 				BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		.event_spec = vcnl4035_event_spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		.num_event_specs = ARRAY_SIZE(vcnl4035_event_spec),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		.scan_index = VCNL4035_CHAN_INDEX_LIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		.scan_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 			.sign = 'u',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 			.realbits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 			.storagebits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 			.endianness = IIO_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		.type = IIO_INTENSITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		.channel = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		.modified = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		.channel2 = IIO_MOD_LIGHT_BOTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		.scan_index = VCNL4035_CHAN_INDEX_WHITE_LED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		.scan_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 			.sign = 'u',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 			.realbits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 			.storagebits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 			.endianness = IIO_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int vcnl4035_set_als_power_state(struct vcnl4035_data *data, u8 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	return regmap_update_bits(data->regmap, VCNL4035_ALS_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 					VCNL4035_MODE_ALS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 					status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int vcnl4035_init(struct vcnl4035_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	ret = regmap_read(data->regmap, VCNL4035_DEV_ID, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		dev_err(&data->client->dev, "Failed to read DEV_ID register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	if (id != VCNL4035_DEV_ID_VAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		dev_err(&data->client->dev, "Wrong id, got %x, expected %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 			id, VCNL4035_DEV_ID_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	ret = vcnl4035_set_als_power_state(data, VCNL4035_MODE_ALS_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	/* ALS white channel enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	ret = regmap_update_bits(data->regmap, VCNL4035_ALS_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 				 VCNL4035_MODE_ALS_WHITE_CHAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 				 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		dev_err(&data->client->dev, "set white channel enable %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 			ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	/* set default integration time - 100 ms for ALS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	ret = regmap_update_bits(data->regmap, VCNL4035_ALS_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 				 VCNL4035_ALS_IT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 				 VCNL4035_ALS_IT_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		dev_err(&data->client->dev, "set default ALS IT returned %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 			ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	data->als_it_val = VCNL4035_ALS_IT_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	/* set default persistence time - 1 for ALS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	ret = regmap_update_bits(data->regmap, VCNL4035_ALS_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 				 VCNL4035_ALS_PERS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 				 VCNL4035_ALS_PERS_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		dev_err(&data->client->dev, "set default PERS returned %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 			ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	data->als_persistence = VCNL4035_ALS_PERS_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	/* set default HIGH threshold for ALS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	ret = regmap_write(data->regmap, VCNL4035_ALS_THDH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 				VCNL4035_ALS_THDH_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 		dev_err(&data->client->dev, "set default THDH returned %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 			ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	data->als_thresh_high = VCNL4035_ALS_THDH_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	/* set default LOW threshold for ALS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	ret = regmap_write(data->regmap, VCNL4035_ALS_THDL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 				VCNL4035_ALS_THDL_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		dev_err(&data->client->dev, "set default THDL returned %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 			ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	data->als_thresh_low = VCNL4035_ALS_THDL_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static bool vcnl4035_is_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	case VCNL4035_ALS_CONF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	case VCNL4035_DEV_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static const struct regmap_config vcnl4035_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	.name		= VCNL4035_REGMAP_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	.reg_bits	= 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	.val_bits	= 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	.max_register	= VCNL4035_DEV_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	.cache_type	= REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	.volatile_reg	= vcnl4035_is_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	.val_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static int vcnl4035_probe_trigger(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	struct vcnl4035_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	data->drdy_trigger0 = devm_iio_trigger_alloc(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 			indio_dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 			"%s-dev%d", indio_dev->name, indio_dev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	if (!data->drdy_trigger0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	data->drdy_trigger0->dev.parent = indio_dev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	data->drdy_trigger0->ops = &vcnl4035_trigger_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	iio_trigger_set_drvdata(data->drdy_trigger0, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	ret = devm_iio_trigger_register(indio_dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 					data->drdy_trigger0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 		dev_err(&data->client->dev, "iio trigger register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	/* Trigger setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	ret = devm_iio_triggered_buffer_setup(indio_dev->dev.parent, indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 					NULL, vcnl4035_trigger_consumer_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 					&iio_triggered_buffer_setup_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 		dev_err(&data->client->dev, "iio triggered buffer setup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	/* IRQ to trigger mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	ret = devm_request_threaded_irq(&data->client->dev, data->client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 			NULL, vcnl4035_drdy_irq_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 			IRQF_TRIGGER_LOW | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 			VCNL4035_IRQ_NAME, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 		dev_err(&data->client->dev, "request irq %d for trigger0 failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 				data->client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static int vcnl4035_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 				const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	struct vcnl4035_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 	regmap = devm_regmap_init_i2c(client, &vcnl4035_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 		dev_err(&client->dev, "regmap_init failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 		return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 	data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 	i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 	data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	data->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 	indio_dev->info = &vcnl4035_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 	indio_dev->name = VCNL4035_DRV_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 	indio_dev->channels = vcnl4035_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 	indio_dev->num_channels = ARRAY_SIZE(vcnl4035_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 	ret = vcnl4035_init(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 		dev_err(&client->dev, "vcnl4035 chip init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 	if (client->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 		ret = vcnl4035_probe_trigger(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 			dev_err(&client->dev, "vcnl4035 unable init trigger\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 			goto fail_poweroff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 	ret = pm_runtime_set_active(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 		goto fail_poweroff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 	ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 		goto fail_poweroff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 	pm_runtime_enable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 	pm_runtime_set_autosuspend_delay(&client->dev, VCNL4035_SLEEP_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 	pm_runtime_use_autosuspend(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) fail_poweroff:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 	vcnl4035_set_als_power_state(data, VCNL4035_MODE_ALS_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static int vcnl4035_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 	struct iio_dev *indio_dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 	pm_runtime_dont_use_autosuspend(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 	pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 	pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 	return vcnl4035_set_als_power_state(iio_priv(indio_dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 					VCNL4035_MODE_ALS_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static int __maybe_unused vcnl4035_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 	struct vcnl4035_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 	ret = vcnl4035_set_als_power_state(data, VCNL4035_MODE_ALS_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 	regcache_mark_dirty(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static int __maybe_unused vcnl4035_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 	struct vcnl4035_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 	regcache_sync(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 	ret = vcnl4035_set_als_power_state(data, VCNL4035_MODE_ALS_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 	/* wait for 1 ALS integration cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 	msleep(data->als_it_val * 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static const struct dev_pm_ops vcnl4035_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 				pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 	SET_RUNTIME_PM_OPS(vcnl4035_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 			   vcnl4035_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static const struct of_device_id vcnl4035_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 	{ .compatible = "vishay,vcnl4035", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) MODULE_DEVICE_TABLE(of, vcnl4035_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static struct i2c_driver vcnl4035_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 		.name   = VCNL4035_DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 		.pm	= &vcnl4035_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 		.of_match_table = vcnl4035_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 	.probe  = vcnl4035_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 	.remove	= vcnl4035_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) module_i2c_driver(vcnl4035_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) MODULE_AUTHOR("Parthiban Nallathambi <pn@denx.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) MODULE_DESCRIPTION("VCNL4035 Ambient Light Sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) MODULE_LICENSE("GPL v2");