^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * UCS12CM0 illuminance and correlated color temperature sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2022-2025 ROCKCHIP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Jason Zhang <jason.zhang@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * IIO driver for UCS12CM0 (7-bit I2C slave address 0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/util_macros.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/iio/kfifo_buf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define UCS12CM0_SYS_CTRL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define UCS12CM0_INT_CTRL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define UCS12CM0_INT_FLAG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define UCS12CM0_WAIT 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define UCS12CM0_ALS_GAIN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define UCS12CM0_ALS_TIME 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define UCS12CM0_PS_LED 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define UCS12CM0_PS_GAIN 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define UCS12CM0_PS_PULSE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define UCS12CM0_PS_TIME 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define UCS12CM0_PS_AVERAGE 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define UCS12CM0_PS_PERSIST 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define UCS12CM0_ALS_THDLL 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define UCS12CM0_ALS_THDLH 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define UCS12CM0_ALS_THDHL 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define UCS12CM0_ALS_THDHH 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define UCS12CM0_PS_THDLL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define UCS12CM0_PS_THDLH 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define UCS12CM0_PS_THDHL 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define UCS12CM0_PS_THDHH 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define UCS12CM0_PS_OFFSET_L 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define UCS12CM0_PS_OFFSET_H 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define UCS12CM0_PS_DATA_L 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define UCS12CM0_PS_DATA_H 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define UCS12CM0_CLS_R_DATA_L 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define UCS12CM0_CLS_R_DATA_H 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define UCS12CM0_CLS_G_DATA_L 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define UCS12CM0_CLS_G_DATA_H 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define UCS12CM0_CLS_B_DATA_L 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define UCS12CM0_CLS_B_DATA_H 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define UCS12CM0_CLS_W_DATA_L 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define UCS12CM0_CLS_W_DATA_H 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define UCS12CM0_IR_DATA_L 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define UCS12CM0_IR_DATA_H 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define UCS12CM0_ID 0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* bis of the SYS_CTRL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define UCS12CM0_EN_CLS BIT(0) /* Enables CLS function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define UCS12CM0_EN_IR BIT(1) /* Enables IR function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define UCS12CM0_EN_FRST BIT(5) /* Enables Brown Out Reset circuit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define UCS12CM0_EN_WAIT BIT(6) /* Waiting time will be inserted between two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * measurements
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define UCS12CM0_SWRST BIT(7) /* Software reset. Reset all register to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * default value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* bis of the INT_FLAG register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define UCS12CM0_INT_CLS BIT(0) /* CLS Interrupt flag. It correlation with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * sensor data and CLS high/low threshold.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * Write zero to clear the flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define UCS12CM0_INT_DATA BIT(6)/* It shows if any data is invalid after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * completion of each conversion cycle. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * bit is read-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define UCS12CM0_INT_POR BIT(7) /* Power-On-Reset Interrupt flag trigger the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * INT pin when the flag sets to one. Write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * zero to clear the flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define UCS12CM0_CCT_CHANNEL(_si, _mod) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .type = IIO_CCT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .address = _si, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .channel2 = _mod, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) BIT(IIO_CHAN_INFO_SCALE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .modified = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .scan_index = _si, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .sign = 'u', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .realbits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) UCS12CM0_CCT_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) UCS12CM0_CCT_GREEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) UCS12CM0_CCT_BLUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) UCS12CM0_CCT_WHITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) UCS12CM0_CCT_ALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct ucs12cm0_scan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u16 chans[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Ensure natural alignment of timestamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) s64 timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct ucs12cm0_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int calibrated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 raw[UCS12CM0_CCT_ALL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 average[UCS12CM0_CCT_ALL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const u8 ucs12cm0_chan_regs[UCS12CM0_CCT_ALL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) UCS12CM0_CLS_R_DATA_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) UCS12CM0_CLS_G_DATA_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) UCS12CM0_CLS_B_DATA_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) UCS12CM0_CLS_W_DATA_L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const struct iio_chan_spec ucs12cm0_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) UCS12CM0_CCT_CHANNEL(UCS12CM0_CCT_READ, IIO_MOD_LIGHT_RED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) UCS12CM0_CCT_CHANNEL(UCS12CM0_CCT_GREEN, IIO_MOD_LIGHT_GREEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) UCS12CM0_CCT_CHANNEL(UCS12CM0_CCT_BLUE, IIO_MOD_LIGHT_BLUE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) UCS12CM0_CCT_CHANNEL(UCS12CM0_CCT_WHITE, IIO_MOD_LIGHT_CLEAR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) IIO_CHAN_SOFT_TIMESTAMP(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int ucs12cm0_read(struct i2c_client *client, u8 cmd, void *databuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u8 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct i2c_msg msgs[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .len = sizeof(cmd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .buf = (u8 *) &cmd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .len = len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .buf = databuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .flags = I2C_M_RD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dev_err(&client->dev, "failed reading register 0x%04x\n", cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int ucs12cm0_read_byte(struct i2c_client *client, u8 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ret = ucs12cm0_read(client, cmd, &data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int ucs12cm0_read_word(struct i2c_client *client, u8 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) __le16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ret = ucs12cm0_read(client, cmd, &data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return le16_to_cpu(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int ucs12cm0_read_average(struct ucs12cm0_data *data, int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u8 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int sum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int average;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) cmd = ucs12cm0_chan_regs[chan];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) for (i = 0; i < 10; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ret = ucs12cm0_read_word(data->client, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) sum += ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) average = sum / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return average;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int ucs12cm0_write_byte(struct i2c_client *client, u8 cmd, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct i2c_msg msgs[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .len = sizeof(buf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .buf = (u8 *) &buf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) buf[0] = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dev_err(&client->dev, "failed writing register 0x%04x\n", cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int ucs12cm0_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct ucs12cm0_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u8 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) cmd = ucs12cm0_chan_regs[chan->address];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ret = ucs12cm0_read_word(data->client, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) *val = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (data->calibrated) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) *val = data->average[chan->address];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) *val2 = data->raw[chan->address];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) *val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) *val2 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return IIO_VAL_FRACTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case IIO_CHAN_INFO_AVERAGE_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) *val = data->average[chan->address];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int ucs12cm0_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct ucs12cm0_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) data->raw[chan->address] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case IIO_CHAN_INFO_AVERAGE_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int ucs12cm0_write_raw_get_fmt(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return IIO_VAL_FRACTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) case IIO_CHAN_INFO_AVERAGE_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static ssize_t start_calibrating_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) const char *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct iio_dev *indio_dev = dev_to_iio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct ucs12cm0_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) long chans = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (!strncmp(buf, "red", 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) set_bit(UCS12CM0_CCT_READ, &chans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) } else if (!strncmp(buf, "green", 5)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) set_bit(UCS12CM0_CCT_GREEN, &chans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) } else if (!strncmp(buf, "blue", 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) set_bit(UCS12CM0_CCT_BLUE, &chans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) } else if (!strncmp(buf, "white", 5)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) set_bit(UCS12CM0_CCT_WHITE, &chans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) } else if (!strncmp(buf, "all", 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) set_bit(UCS12CM0_CCT_READ, &chans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) set_bit(UCS12CM0_CCT_GREEN, &chans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) set_bit(UCS12CM0_CCT_BLUE, &chans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) set_bit(UCS12CM0_CCT_WHITE, &chans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) for_each_set_bit(i, &chans, UCS12CM0_CCT_ALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (!data->raw[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dev_info(&data->client->dev, "raw = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) data->raw[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) for_each_set_bit(i, &chans, UCS12CM0_CCT_ALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ret = ucs12cm0_read_average(data, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) else if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) data->average[i] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) dev_info(&data->client->dev, "average = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) data->average[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * TODO: store the calibration data in the ROM because UCS12CM0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * doesn't have any rom-related register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) data->calibrated = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static IIO_DEVICE_ATTR_WO(start_calibrating, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static struct attribute *ucs12cm0_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) &iio_dev_attr_start_calibrating.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static const struct attribute_group ucs12cm0_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .attrs = ucs12cm0_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static const struct iio_info ucs12cm0_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .read_raw = ucs12cm0_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .write_raw = ucs12cm0_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .write_raw_get_fmt = ucs12cm0_write_raw_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .attrs = &ucs12cm0_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * ucs12cm0_active - enable or disable the CLS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * @client: the i2c client used by the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * @enable: enable/disable the CLS of ucs12cm0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * Returns negative errno, else the number of messages executed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static int ucs12cm0_active(struct i2c_client *client, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ret = ucs12cm0_read_byte(client, UCS12CM0_SYS_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) val = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) val |= UCS12CM0_EN_CLS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) val &= ~UCS12CM0_EN_CLS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ret = ucs12cm0_write_byte(client, UCS12CM0_SYS_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dev_err(&client->dev, "Failed to active sensor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static int ucs12cm0_buffer_postenable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct ucs12cm0_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return ucs12cm0_active(data->client, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int ucs12cm0_buffer_predisable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct ucs12cm0_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return ucs12cm0_active(data->client, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static const struct iio_buffer_setup_ops ucs12cm0_buffer_setup_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .postenable = ucs12cm0_buffer_postenable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .predisable = ucs12cm0_buffer_predisable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int ucs12cm0_init(struct ucs12cm0_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ret = ucs12cm0_write_byte(client, UCS12CM0_SYS_CTRL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ret = ucs12cm0_write_byte(client, UCS12CM0_INT_CTRL, 0x13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ret = ucs12cm0_write_byte(client, UCS12CM0_INT_FLAG, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ret = ucs12cm0_write_byte(client, UCS12CM0_WAIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) ret = ucs12cm0_write_byte(client, UCS12CM0_ALS_GAIN, 0x84);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ret = ucs12cm0_write_byte(client, UCS12CM0_ALS_TIME, 0x33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ret = ucs12cm0_write_byte(client, UCS12CM0_PS_LED, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ret = ucs12cm0_write_byte(client, UCS12CM0_PS_GAIN, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ret = ucs12cm0_write_byte(client, UCS12CM0_PS_PULSE, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ret = ucs12cm0_write_byte(client, UCS12CM0_PS_TIME, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ret = ucs12cm0_write_byte(client, UCS12CM0_PS_AVERAGE, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ret = ucs12cm0_write_byte(client, UCS12CM0_PS_PERSIST, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ret = ucs12cm0_write_byte(client, UCS12CM0_PS_OFFSET_L, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ret = ucs12cm0_write_byte(client, UCS12CM0_ALS_THDHL, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ret = ucs12cm0_write_byte(client, UCS12CM0_ALS_THDHH, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ret = ucs12cm0_write_byte(client, UCS12CM0_ALS_THDLL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ret = ucs12cm0_write_byte(client, UCS12CM0_ALS_THDLH, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static irqreturn_t ucs12cm0_interrupt_handler(int irq, void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct iio_dev *indio_dev = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct ucs12cm0_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct ucs12cm0_scan scan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ret = ucs12cm0_read_byte(client, UCS12CM0_INT_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (ret & UCS12CM0_INT_CLS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (ucs12cm0_read(client, UCS12CM0_CLS_R_DATA_L, scan.chans,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) sizeof(scan.chans)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) goto clear_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) iio_push_to_buffers_with_timestamp(indio_dev, &scan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ktime_get_boottime_ns());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) clear_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (ret & UCS12CM0_INT_CLS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ret &= ~UCS12CM0_INT_CLS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ucs12cm0_write_byte(client, UCS12CM0_INT_FLAG, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (ret & UCS12CM0_INT_POR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ret &= ~UCS12CM0_INT_POR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ucs12cm0_write_byte(client, UCS12CM0_INT_FLAG, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static int ucs12cm0_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct ucs12cm0_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct iio_buffer *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) buffer = devm_iio_kfifo_allocate(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (!buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) iio_device_attach_buffer(indio_dev, buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) indio_dev->info = &ucs12cm0_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) indio_dev->channels = ucs12cm0_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) indio_dev->num_channels = ARRAY_SIZE(ucs12cm0_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) indio_dev->name = "ucs12cm0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) indio_dev->modes = (INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) indio_dev->setup_ops = &ucs12cm0_buffer_setup_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ret = ucs12cm0_init(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (client->irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) dev_err(&client->dev, "no valid irq defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) type = irqd_get_trigger_type(irq_get_irq_data(client->irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (type != IRQF_TRIGGER_LOW && type != IRQF_TRIGGER_FALLING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) "unsupported IRQ trigger specified (%x)\n", type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) ret = devm_request_threaded_irq(&client->dev, client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) NULL, ucs12cm0_interrupt_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) type | IRQF_ONESHOT, "ucs12cm0_irq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) dev_err(&client->dev, "request irq (%d) failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return devm_iio_device_register(&client->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static const struct of_device_id ucs12cm0_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) { .compatible = "ultracapteur,ucs12cm0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) MODULE_DEVICE_TABLE(of, ucs12cm0_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static const struct i2c_device_id ucs12cm0_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) { "ucs12cm0", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) MODULE_DEVICE_TABLE(i2c, ucs12cm0_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static int ucs12cm0_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct iio_dev *indio_dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct ucs12cm0_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ret = ucs12cm0_init(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static const struct dev_pm_ops ucs12cm0_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .resume = ucs12cm0_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static struct i2c_driver ucs12cm0_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .name = "ucs12cm0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .of_match_table = ucs12cm0_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .pm = &ucs12cm0_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .probe = ucs12cm0_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .id_table = ucs12cm0_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) module_i2c_driver(ucs12cm0_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) MODULE_AUTHOR("Jason Zhang <jason.zhang@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) MODULE_DESCRIPTION("UCS12CM0 illuminance and correlated color temperature sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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