^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Device driver for monitoring ambient light intensity in (lux) and proximity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * detection (prox) within the TAOS TSL2571, TSL2671, TMD2671, TSL2771, TMD2771,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * TSL2572, TSL2672, TMD2672, TSL2772, and TMD2772 devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2012, TAOS Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2017-2018 Brian Masney <masneyb@onstation.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iio/events.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_data/tsl2772.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Cal defs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PROX_STAT_CAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PROX_STAT_SAMP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MAX_SAMPLES_CAL 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* TSL2772 Device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TRITON_ID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SWORDFISH_ID 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HALIBUT_ID 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Lux calculation constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TSL2772_LUX_CALC_OVER_FLOW 65535
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * TAOS Register definitions - Note: depending on device, some of these register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * are not used and the register address is benign.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TSL2772_MAX_CONFIG_REG 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Device Registers and Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TSL2772_CNTRL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TSL2772_ALS_TIME 0X01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TSL2772_PRX_TIME 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TSL2772_WAIT_TIME 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TSL2772_ALS_MINTHRESHLO 0X04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TSL2772_ALS_MINTHRESHHI 0X05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TSL2772_ALS_MAXTHRESHLO 0X06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TSL2772_ALS_MAXTHRESHHI 0X07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TSL2772_PRX_MINTHRESHLO 0X08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TSL2772_PRX_MINTHRESHHI 0X09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TSL2772_PRX_MAXTHRESHLO 0X0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TSL2772_PRX_MAXTHRESHHI 0X0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TSL2772_PERSISTENCE 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TSL2772_ALS_PRX_CONFIG 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TSL2772_PRX_COUNT 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TSL2772_GAIN 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TSL2772_NOTUSED 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TSL2772_REVID 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TSL2772_CHIPID 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TSL2772_STATUS 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TSL2772_ALS_CHAN0LO 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TSL2772_ALS_CHAN0HI 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TSL2772_ALS_CHAN1LO 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TSL2772_ALS_CHAN1HI 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TSL2772_PRX_LO 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TSL2772_PRX_HI 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* tsl2772 cmd reg masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TSL2772_CMD_REG 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TSL2772_CMD_SPL_FN 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TSL2772_CMD_REPEAT_PROTO 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TSL2772_CMD_AUTOINC_PROTO 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TSL2772_CMD_PROX_INT_CLR 0X05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TSL2772_CMD_ALS_INT_CLR 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TSL2772_CMD_PROXALS_INT_CLR 0X07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* tsl2772 cntrl reg masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TSL2772_CNTL_ADC_ENBL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TSL2772_CNTL_PWR_ON 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* tsl2772 status reg masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TSL2772_STA_ADC_VALID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TSL2772_STA_PRX_VALID 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TSL2772_STA_ADC_PRX_VALID (TSL2772_STA_ADC_VALID | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) TSL2772_STA_PRX_VALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TSL2772_STA_ALS_INTR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TSL2772_STA_PRX_INTR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* tsl2772 cntrl reg masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TSL2772_CNTL_REG_CLEAR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TSL2772_CNTL_PROX_INT_ENBL 0X20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TSL2772_CNTL_ALS_INT_ENBL 0X10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TSL2772_CNTL_WAIT_TMR_ENBL 0X08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TSL2772_CNTL_PROX_DET_ENBL 0X04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TSL2772_CNTL_PWRON 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TSL2772_CNTL_ALSPON_ENBL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TSL2772_CNTL_INTALSPON_ENBL 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TSL2772_CNTL_PROXPON_ENBL 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TSL2772_CNTL_INTPROXPON_ENBL 0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TSL2772_ALS_GAIN_TRIM_MIN 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TSL2772_ALS_GAIN_TRIM_MAX 4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TSL2772_MAX_PROX_LEDS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TSL2772_BOOT_MIN_SLEEP_TIME 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TSL2772_BOOT_MAX_SLEEP_TIME 28000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Device family members */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) tsl2571,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) tsl2671,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) tmd2671,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) tsl2771,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) tmd2771,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) tsl2572,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) tsl2672,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) tmd2672,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) tsl2772,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) tmd2772,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) apds9930,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) TSL2772_CHIP_UNKNOWN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) TSL2772_CHIP_WORKING = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) TSL2772_CHIP_SUSPENDED = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) TSL2772_SUPPLY_VDD = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) TSL2772_SUPPLY_VDDIO = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) TSL2772_NUM_SUPPLIES = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Per-device data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct tsl2772_als_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u16 als_ch0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u16 als_ch1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u16 lux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct tsl2772_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int chan_table_elements;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct iio_chan_spec channel_with_events[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct iio_chan_spec channel_without_events[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) const struct iio_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const int tsl2772_led_currents[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { 100000, TSL2772_100_mA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { 50000, TSL2772_50_mA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { 25000, TSL2772_25_mA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { 13000, TSL2772_13_mA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct tsl2772_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) kernel_ulong_t id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct mutex prox_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct mutex als_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct regulator_bulk_data supplies[TSL2772_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u16 prox_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct tsl2772_als_info als_cur_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct tsl2772_settings settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct tsl2772_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int als_gain_time_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int als_saturation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int tsl2772_chip_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u8 tsl2772_config[TSL2772_MAX_CONFIG_REG];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) const struct tsl2772_chip_info *chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) const struct iio_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) s64 event_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * This structure is intentionally large to accommodate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * updates via sysfs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * Sized to 9 = max 8 segments + 1 termination segment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct tsl2772_lux tsl2772_device_lux[TSL2772_MAX_LUX_TABLE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * Different devices require different coefficents, and these numbers were
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * derived from the 'Lux Equation' section of the various device datasheets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * All of these coefficients assume a Glass Attenuation (GA) factor of 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * The coefficients are multiplied by 1000 to avoid floating point operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * The two rows in each table correspond to the Lux1 and Lux2 equations from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * the datasheets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const struct tsl2772_lux tsl2x71_lux_table[TSL2772_DEF_LUX_TABLE_SZ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { 53000, 106000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { 31800, 53000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const struct tsl2772_lux tmd2x71_lux_table[TSL2772_DEF_LUX_TABLE_SZ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { 24000, 48000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { 14400, 24000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const struct tsl2772_lux tsl2x72_lux_table[TSL2772_DEF_LUX_TABLE_SZ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { 60000, 112200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { 37800, 60000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const struct tsl2772_lux tmd2x72_lux_table[TSL2772_DEF_LUX_TABLE_SZ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { 20000, 35000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { 12600, 20000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const struct tsl2772_lux apds9930_lux_table[TSL2772_DEF_LUX_TABLE_SZ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { 52000, 96824 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { 38792, 67132 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const struct tsl2772_lux *tsl2772_default_lux_table_group[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) [tsl2571] = tsl2x71_lux_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) [tsl2671] = tsl2x71_lux_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) [tmd2671] = tmd2x71_lux_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) [tsl2771] = tsl2x71_lux_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) [tmd2771] = tmd2x71_lux_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) [tsl2572] = tsl2x72_lux_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) [tsl2672] = tsl2x72_lux_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) [tmd2672] = tmd2x72_lux_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) [tsl2772] = tsl2x72_lux_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) [tmd2772] = tmd2x72_lux_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) [apds9930] = apds9930_lux_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const struct tsl2772_settings tsl2772_default_settings = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .als_time = 255, /* 2.72 / 2.73 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .als_gain = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .prox_time = 255, /* 2.72 / 2.73 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .prox_gain = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .wait_time = 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .als_prox_config = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .als_gain_trim = 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .als_cal_target = 150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .als_persistence = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .als_interrupt_en = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .als_thresh_low = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .als_thresh_high = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .prox_persistence = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .prox_interrupt_en = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .prox_thres_low = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .prox_thres_high = 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .prox_max_samples_cal = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .prox_pulse_count = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .prox_diode = TSL2772_DIODE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .prox_power = TSL2772_100_mA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const s16 tsl2772_als_gain[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const s16 tsl2772_prox_gain[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static const int tsl2772_int_time_avail[][6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) [tsl2571] = { 0, 2720, 0, 2720, 0, 696000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) [tsl2671] = { 0, 2720, 0, 2720, 0, 696000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) [tmd2671] = { 0, 2720, 0, 2720, 0, 696000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) [tsl2771] = { 0, 2720, 0, 2720, 0, 696000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) [tmd2771] = { 0, 2720, 0, 2720, 0, 696000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) [tsl2572] = { 0, 2730, 0, 2730, 0, 699000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) [tsl2672] = { 0, 2730, 0, 2730, 0, 699000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) [tmd2672] = { 0, 2730, 0, 2730, 0, 699000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) [tsl2772] = { 0, 2730, 0, 2730, 0, 699000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) [tmd2772] = { 0, 2730, 0, 2730, 0, 699000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) [apds9930] = { 0, 2730, 0, 2730, 0, 699000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int tsl2772_int_calibscale_avail[] = { 1, 8, 16, 120 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int tsl2772_prox_calibscale_avail[] = { 1, 2, 4, 8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Channel variations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ALS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PRX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ALSPRX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PRX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ALSPRX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const u8 device_channel_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) [tsl2571] = ALS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) [tsl2671] = PRX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) [tmd2671] = PRX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) [tsl2771] = ALSPRX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) [tmd2771] = ALSPRX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) [tsl2572] = ALS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) [tsl2672] = PRX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) [tmd2672] = PRX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) [tsl2772] = ALSPRX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) [tmd2772] = ALSPRX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) [apds9930] = ALSPRX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int tsl2772_read_status(struct tsl2772_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ret = i2c_smbus_read_byte_data(chip->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) TSL2772_CMD_REG | TSL2772_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) dev_err(&chip->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) "%s: failed to read STATUS register: %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int tsl2772_write_control_reg(struct tsl2772_chip *chip, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ret = i2c_smbus_write_byte_data(chip->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) TSL2772_CMD_REG | TSL2772_CNTRL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dev_err(&chip->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) "%s: failed to write to control register %x: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) __func__, data, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int tsl2772_read_autoinc_regs(struct tsl2772_chip *chip, int lower_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int upper_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ret = i2c_smbus_write_byte(chip->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) TSL2772_CMD_REG | TSL2772_CMD_AUTOINC_PROTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) lower_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) dev_err(&chip->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) "%s: failed to enable auto increment protocol: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ret = i2c_smbus_read_byte_data(chip->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) TSL2772_CMD_REG | lower_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dev_err(&chip->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) "%s: failed to read from register %x: %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) lower_reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) buf[0] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = i2c_smbus_read_byte_data(chip->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) TSL2772_CMD_REG | upper_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev_err(&chip->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) "%s: failed to read from register %x: %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) upper_reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) buf[1] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ret = i2c_smbus_write_byte(chip->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) TSL2772_CMD_REG | TSL2772_CMD_REPEAT_PROTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) lower_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dev_err(&chip->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) "%s: failed to enable repeated byte protocol: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return le16_to_cpup((const __le16 *)&buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * tsl2772_get_lux() - Reads and calculates current lux value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * @indio_dev: pointer to IIO device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * The raw ch0 and ch1 values of the ambient light sensed in the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * integration cycle are read from the device. The raw values are multiplied
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * by a device-specific scale factor, and divided by the integration time and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * device gain. The code supports multiple lux equations through the lux table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * coefficients. A lux gain trim is applied to each lux equation, and then the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * maximum lux within the interval 0..65535 is selected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static int tsl2772_get_lux(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct tsl2772_chip *chip = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct tsl2772_lux *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int max_lux, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) bool overflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) mutex_lock(&chip->als_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (chip->tsl2772_chip_status != TSL2772_CHIP_WORKING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dev_err(&chip->client->dev, "%s: device is not enabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ret = tsl2772_read_status(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (!(ret & TSL2772_STA_ADC_VALID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dev_err(&chip->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) "%s: data not valid yet\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ret = chip->als_cur_info.lux; /* return LAST VALUE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ret = tsl2772_read_autoinc_regs(chip, TSL2772_ALS_CHAN0LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) TSL2772_ALS_CHAN0HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) chip->als_cur_info.als_ch0 = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ret = tsl2772_read_autoinc_regs(chip, TSL2772_ALS_CHAN1LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) TSL2772_ALS_CHAN1HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) chip->als_cur_info.als_ch1 = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (chip->als_cur_info.als_ch0 >= chip->als_saturation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) max_lux = TSL2772_LUX_CALC_OVER_FLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) goto update_struct_with_max_lux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (!chip->als_cur_info.als_ch0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* have no data, so return LAST VALUE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ret = chip->als_cur_info.lux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) max_lux = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) overflow = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) for (p = (struct tsl2772_lux *)chip->tsl2772_device_lux; p->ch0 != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) p++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) int lux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) lux = ((chip->als_cur_info.als_ch0 * p->ch0) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) (chip->als_cur_info.als_ch1 * p->ch1)) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) chip->als_gain_time_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * The als_gain_trim can have a value within the range 250..4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * and is a multiplier for the lux. A trim of 1000 makes no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * changes to the lux, less than 1000 scales it down, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * greater than 1000 scales it up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) lux = (lux * chip->settings.als_gain_trim) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (lux > TSL2772_LUX_CALC_OVER_FLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) overflow = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) max_lux = max(max_lux, lux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (overflow && max_lux == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) max_lux = TSL2772_LUX_CALC_OVER_FLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) update_struct_with_max_lux:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) chip->als_cur_info.lux = max_lux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ret = max_lux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) mutex_unlock(&chip->als_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * tsl2772_get_prox() - Reads proximity data registers and updates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * chip->prox_data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * @indio_dev: pointer to IIO device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static int tsl2772_get_prox(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct tsl2772_chip *chip = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) mutex_lock(&chip->prox_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) ret = tsl2772_read_status(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) goto prox_poll_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) switch (chip->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) case tsl2571:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) case tsl2671:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) case tmd2671:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) case tsl2771:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) case tmd2771:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (!(ret & TSL2772_STA_ADC_VALID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) goto prox_poll_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) case tsl2572:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) case tsl2672:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) case tmd2672:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) case tsl2772:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) case tmd2772:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) case apds9930:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (!(ret & TSL2772_STA_PRX_VALID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) goto prox_poll_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ret = tsl2772_read_autoinc_regs(chip, TSL2772_PRX_LO, TSL2772_PRX_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) goto prox_poll_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) chip->prox_data = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) prox_poll_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) mutex_unlock(&chip->prox_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static int tsl2772_read_prox_led_current(struct tsl2772_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct device_node *of_node = chip->client->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int ret, tmp, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ret = of_property_read_u32(of_node, "led-max-microamp", &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) for (i = 0; tsl2772_led_currents[i][0] != 0; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (tmp == tsl2772_led_currents[i][0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) chip->settings.prox_power = tsl2772_led_currents[i][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) dev_err(&chip->client->dev, "Invalid value %d for led-max-microamp\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static int tsl2772_read_prox_diodes(struct tsl2772_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct device_node *of_node = chip->client->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) int i, ret, num_leds, prox_diode_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) u32 leds[TSL2772_MAX_PROX_LEDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ret = of_property_count_u32_elems(of_node, "amstaos,proximity-diodes");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) num_leds = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (num_leds > TSL2772_MAX_PROX_LEDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) num_leds = TSL2772_MAX_PROX_LEDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ret = of_property_read_u32_array(of_node, "amstaos,proximity-diodes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) leds, num_leds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dev_err(&chip->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) "Invalid value for amstaos,proximity-diodes: %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) prox_diode_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) for (i = 0; i < num_leds; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (leds[i] == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) prox_diode_mask |= TSL2772_DIODE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) else if (leds[i] == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) prox_diode_mask |= TSL2772_DIODE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) dev_err(&chip->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) "Invalid value %d in amstaos,proximity-diodes.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) leds[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static void tsl2772_parse_dt(struct tsl2772_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) tsl2772_read_prox_led_current(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) tsl2772_read_prox_diodes(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * tsl2772_defaults() - Populates the device nominal operating parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * with those provided by a 'platform' data struct or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * with prefined defaults.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * @chip: pointer to device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static void tsl2772_defaults(struct tsl2772_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* If Operational settings defined elsewhere.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (chip->pdata && chip->pdata->platform_default_settings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) memcpy(&chip->settings, chip->pdata->platform_default_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) sizeof(tsl2772_default_settings));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) memcpy(&chip->settings, &tsl2772_default_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) sizeof(tsl2772_default_settings));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* Load up the proper lux table. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (chip->pdata && chip->pdata->platform_lux_table[0].ch0 != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) memcpy(chip->tsl2772_device_lux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) chip->pdata->platform_lux_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) sizeof(chip->pdata->platform_lux_table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) memcpy(chip->tsl2772_device_lux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) tsl2772_default_lux_table_group[chip->id],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) TSL2772_DEFAULT_TABLE_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) tsl2772_parse_dt(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * tsl2772_als_calibrate() - Obtain single reading and calculate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * the als_gain_trim.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * @indio_dev: pointer to IIO device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static int tsl2772_als_calibrate(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct tsl2772_chip *chip = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) int ret, lux_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ret = i2c_smbus_read_byte_data(chip->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) TSL2772_CMD_REG | TSL2772_CNTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) dev_err(&chip->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) "%s: failed to read from the CNTRL register\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if ((ret & (TSL2772_CNTL_ADC_ENBL | TSL2772_CNTL_PWR_ON))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) != (TSL2772_CNTL_ADC_ENBL | TSL2772_CNTL_PWR_ON)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) dev_err(&chip->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) "%s: Device is not powered on and/or ADC is not enabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) } else if ((ret & TSL2772_STA_ADC_VALID) != TSL2772_STA_ADC_VALID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) dev_err(&chip->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) "%s: The two ADC channels have not completed an integration cycle\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) lux_val = tsl2772_get_lux(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (lux_val < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) dev_err(&chip->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) "%s: failed to get lux\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return lux_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (lux_val == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ret = (chip->settings.als_cal_target * chip->settings.als_gain_trim) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) lux_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (ret < TSL2772_ALS_GAIN_TRIM_MIN || ret > TSL2772_ALS_GAIN_TRIM_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) chip->settings.als_gain_trim = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static void tsl2772_disable_regulators_action(void *_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct tsl2772_chip *chip = _data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) regulator_bulk_disable(ARRAY_SIZE(chip->supplies), chip->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static int tsl2772_chip_on(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct tsl2772_chip *chip = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) int ret, i, als_count, als_time_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) u8 *dev_reg, reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* Non calculated parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) chip->tsl2772_config[TSL2772_ALS_TIME] = chip->settings.als_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) chip->tsl2772_config[TSL2772_PRX_TIME] = chip->settings.prox_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) chip->tsl2772_config[TSL2772_WAIT_TIME] = chip->settings.wait_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) chip->tsl2772_config[TSL2772_ALS_PRX_CONFIG] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) chip->settings.als_prox_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) chip->tsl2772_config[TSL2772_ALS_MINTHRESHLO] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) (chip->settings.als_thresh_low) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) chip->tsl2772_config[TSL2772_ALS_MINTHRESHHI] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) (chip->settings.als_thresh_low >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) chip->tsl2772_config[TSL2772_ALS_MAXTHRESHLO] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) (chip->settings.als_thresh_high) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) chip->tsl2772_config[TSL2772_ALS_MAXTHRESHHI] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) (chip->settings.als_thresh_high >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) chip->tsl2772_config[TSL2772_PERSISTENCE] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) (chip->settings.prox_persistence & 0xFF) << 4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) (chip->settings.als_persistence & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) chip->tsl2772_config[TSL2772_PRX_COUNT] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) chip->settings.prox_pulse_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) chip->tsl2772_config[TSL2772_PRX_MINTHRESHLO] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) (chip->settings.prox_thres_low) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) chip->tsl2772_config[TSL2772_PRX_MINTHRESHHI] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) (chip->settings.prox_thres_low >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) chip->tsl2772_config[TSL2772_PRX_MAXTHRESHLO] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) (chip->settings.prox_thres_high) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) chip->tsl2772_config[TSL2772_PRX_MAXTHRESHHI] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) (chip->settings.prox_thres_high >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* and make sure we're not already on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (chip->tsl2772_chip_status == TSL2772_CHIP_WORKING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* if forcing a register update - turn off, then on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) dev_info(&chip->client->dev, "device is already enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* Set the gain based on tsl2772_settings struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) chip->tsl2772_config[TSL2772_GAIN] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) (chip->settings.als_gain & 0xFF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ((chip->settings.prox_gain & 0xFF) << 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) (chip->settings.prox_diode << 4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) (chip->settings.prox_power << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* set chip time scaling and saturation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) als_count = 256 - chip->settings.als_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) als_time_us = als_count * tsl2772_int_time_avail[chip->id][3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) chip->als_saturation = als_count * 768; /* 75% of full scale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) chip->als_gain_time_scale = als_time_us *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) tsl2772_als_gain[chip->settings.als_gain];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * TSL2772 Specific power-on / adc enable sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * Power on the device 1st.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) ret = tsl2772_write_control_reg(chip, TSL2772_CNTL_PWR_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * Use the following shadow copy for our delay before enabling ADC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * Write all the registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) for (i = 0, dev_reg = chip->tsl2772_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) i < TSL2772_MAX_CONFIG_REG; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) int reg = TSL2772_CMD_REG + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) ret = i2c_smbus_write_byte_data(chip->client, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) *dev_reg++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) dev_err(&chip->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) "%s: failed to write to register %x: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) __func__, reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* Power-on settling time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) usleep_range(3000, 3500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) reg_val = TSL2772_CNTL_PWR_ON | TSL2772_CNTL_ADC_ENBL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) TSL2772_CNTL_PROX_DET_ENBL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (chip->settings.als_interrupt_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) reg_val |= TSL2772_CNTL_ALS_INT_ENBL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (chip->settings.prox_interrupt_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) reg_val |= TSL2772_CNTL_PROX_INT_ENBL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ret = tsl2772_write_control_reg(chip, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) ret = i2c_smbus_write_byte(chip->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) TSL2772_CMD_REG | TSL2772_CMD_SPL_FN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) TSL2772_CMD_PROXALS_INT_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) dev_err(&chip->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) "%s: failed to clear interrupt status: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) chip->tsl2772_chip_status = TSL2772_CHIP_WORKING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static int tsl2772_chip_off(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct tsl2772_chip *chip = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /* turn device off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) chip->tsl2772_chip_status = TSL2772_CHIP_SUSPENDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return tsl2772_write_control_reg(chip, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static void tsl2772_chip_off_action(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct iio_dev *indio_dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) tsl2772_chip_off(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * tsl2772_invoke_change - power cycle the device to implement the user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * @indio_dev: pointer to IIO device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * Obtain and lock both ALS and PROX resources, determine and save device state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * (On/Off), cycle device to implement updated parameter, put device back into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * proper state, and unlock resource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static int tsl2772_invoke_change(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct tsl2772_chip *chip = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) int device_status = chip->tsl2772_chip_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) mutex_lock(&chip->als_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) mutex_lock(&chip->prox_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (device_status == TSL2772_CHIP_WORKING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ret = tsl2772_chip_off(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ret = tsl2772_chip_on(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) mutex_unlock(&chip->prox_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) mutex_unlock(&chip->als_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static int tsl2772_prox_cal(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct tsl2772_chip *chip = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) int prox_history[MAX_SAMPLES_CAL + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) int i, ret, mean, max, sample_sum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (chip->settings.prox_max_samples_cal < 1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) chip->settings.prox_max_samples_cal > MAX_SAMPLES_CAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) for (i = 0; i < chip->settings.prox_max_samples_cal; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) usleep_range(15000, 17500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ret = tsl2772_get_prox(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) prox_history[i] = chip->prox_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) sample_sum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) max = INT_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) for (i = 0; i < chip->settings.prox_max_samples_cal; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) sample_sum += prox_history[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) max = max(max, prox_history[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) mean = sample_sum / chip->settings.prox_max_samples_cal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) chip->settings.prox_thres_high = (max << 1) - mean;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return tsl2772_invoke_change(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static int tsl2772_read_avail(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) const int **vals, int *type, int *length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct tsl2772_chip *chip = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) case IIO_CHAN_INFO_CALIBSCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (chan->type == IIO_INTENSITY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) *length = ARRAY_SIZE(tsl2772_int_calibscale_avail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) *vals = tsl2772_int_calibscale_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) *length = ARRAY_SIZE(tsl2772_prox_calibscale_avail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) *vals = tsl2772_prox_calibscale_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) *type = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return IIO_AVAIL_LIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) case IIO_CHAN_INFO_INT_TIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) *length = ARRAY_SIZE(tsl2772_int_time_avail[chip->id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) *vals = tsl2772_int_time_avail[chip->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) *type = IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return IIO_AVAIL_RANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static ssize_t in_illuminance0_target_input_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) struct tsl2772_chip *chip = iio_priv(dev_to_iio_dev(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) return scnprintf(buf, PAGE_SIZE, "%d\n", chip->settings.als_cal_target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static ssize_t in_illuminance0_target_input_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) const char *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) struct iio_dev *indio_dev = dev_to_iio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) struct tsl2772_chip *chip = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) u16 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (kstrtou16(buf, 0, &value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) chip->settings.als_cal_target = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) ret = tsl2772_invoke_change(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static ssize_t in_illuminance0_calibrate_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) const char *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct iio_dev *indio_dev = dev_to_iio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) bool value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (kstrtobool(buf, &value) || !value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) ret = tsl2772_als_calibrate(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) ret = tsl2772_invoke_change(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static ssize_t in_illuminance0_lux_table_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct tsl2772_chip *chip = iio_priv(dev_to_iio_dev(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) int offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) while (i < TSL2772_MAX_LUX_TABLE_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%u,%u,",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) chip->tsl2772_device_lux[i].ch0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) chip->tsl2772_device_lux[i].ch1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (chip->tsl2772_device_lux[i].ch0 == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * We just printed the first "0" entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) * Now get rid of the extra "," and break.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) offset--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) offset += scnprintf(buf + offset, PAGE_SIZE - offset, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static ssize_t in_illuminance0_lux_table_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) const char *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct iio_dev *indio_dev = dev_to_iio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) struct tsl2772_chip *chip = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) int value[ARRAY_SIZE(chip->tsl2772_device_lux) * 2 + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) int n, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) get_options(buf, ARRAY_SIZE(value), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) * We now have an array of ints starting at value[1], and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) * enumerated by value[0].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) * We expect each group of two ints to be one table entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * and the last table entry is all 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) n = value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if ((n % 2) || n < 4 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) n > ((ARRAY_SIZE(chip->tsl2772_device_lux) - 1) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if ((value[(n - 1)] | value[n]) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (chip->tsl2772_chip_status == TSL2772_CHIP_WORKING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) ret = tsl2772_chip_off(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) /* Zero out the table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) memset(chip->tsl2772_device_lux, 0, sizeof(chip->tsl2772_device_lux));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) memcpy(chip->tsl2772_device_lux, &value[1], (value[0] * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) ret = tsl2772_invoke_change(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static ssize_t in_proximity0_calibrate_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) const char *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) struct iio_dev *indio_dev = dev_to_iio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) bool value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) if (kstrtobool(buf, &value) || !value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) ret = tsl2772_prox_cal(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) ret = tsl2772_invoke_change(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static int tsl2772_read_interrupt_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) enum iio_event_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) struct tsl2772_chip *chip = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (chan->type == IIO_INTENSITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) return chip->settings.als_interrupt_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) return chip->settings.prox_interrupt_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) static int tsl2772_write_interrupt_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) enum iio_event_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) struct tsl2772_chip *chip = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (chan->type == IIO_INTENSITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) chip->settings.als_interrupt_en = val ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) chip->settings.prox_interrupt_en = val ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) return tsl2772_invoke_change(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static int tsl2772_write_event_value(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) enum iio_event_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) enum iio_event_info info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) int val, int val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) struct tsl2772_chip *chip = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) int ret = -EINVAL, count, persistence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) u8 time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) case IIO_EV_INFO_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (chan->type == IIO_INTENSITY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) switch (dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) case IIO_EV_DIR_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) chip->settings.als_thresh_high = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) case IIO_EV_DIR_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) chip->settings.als_thresh_low = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) switch (dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) case IIO_EV_DIR_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) chip->settings.prox_thres_high = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) case IIO_EV_DIR_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) chip->settings.prox_thres_low = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) case IIO_EV_INFO_PERIOD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (chan->type == IIO_INTENSITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) time = chip->settings.als_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) time = chip->settings.prox_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) count = 256 - time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) persistence = ((val * 1000000) + val2) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) (count * tsl2772_int_time_avail[chip->id][3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (chan->type == IIO_INTENSITY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /* ALS filter values are 1, 2, 3, 5, 10, 15, ..., 60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (persistence > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) persistence = (persistence / 5) + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) chip->settings.als_persistence = persistence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) chip->settings.prox_persistence = persistence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return tsl2772_invoke_change(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) static int tsl2772_read_event_value(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) enum iio_event_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) enum iio_event_info info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) int *val, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) struct tsl2772_chip *chip = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) int filter_delay, persistence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) u8 time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) case IIO_EV_INFO_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (chan->type == IIO_INTENSITY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) switch (dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) case IIO_EV_DIR_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) *val = chip->settings.als_thresh_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) case IIO_EV_DIR_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) *val = chip->settings.als_thresh_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) switch (dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) case IIO_EV_DIR_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) *val = chip->settings.prox_thres_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) case IIO_EV_DIR_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) *val = chip->settings.prox_thres_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) case IIO_EV_INFO_PERIOD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if (chan->type == IIO_INTENSITY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) time = chip->settings.als_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) persistence = chip->settings.als_persistence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) /* ALS filter values are 1, 2, 3, 5, 10, 15, ..., 60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) if (persistence > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) persistence = (persistence - 3) * 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) time = chip->settings.prox_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) persistence = chip->settings.prox_persistence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) filter_delay = persistence * (256 - time) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) tsl2772_int_time_avail[chip->id][3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) *val = filter_delay / 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) *val2 = filter_delay % 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) static int tsl2772_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) struct tsl2772_chip *chip = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) case IIO_CHAN_INFO_PROCESSED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) case IIO_LIGHT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) tsl2772_get_lux(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) *val = chip->als_cur_info.lux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) case IIO_INTENSITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) tsl2772_get_lux(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) if (chan->channel == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) *val = chip->als_cur_info.als_ch0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) *val = chip->als_cur_info.als_ch1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) case IIO_PROXIMITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) tsl2772_get_prox(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) *val = chip->prox_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) case IIO_CHAN_INFO_CALIBSCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (chan->type == IIO_LIGHT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) *val = tsl2772_als_gain[chip->settings.als_gain];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) *val = tsl2772_prox_gain[chip->settings.prox_gain];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) case IIO_CHAN_INFO_CALIBBIAS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) *val = chip->settings.als_gain_trim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) case IIO_CHAN_INFO_INT_TIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) *val2 = (256 - chip->settings.als_time) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) tsl2772_int_time_avail[chip->id][3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) static int tsl2772_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) int val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) struct tsl2772_chip *chip = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) case IIO_CHAN_INFO_CALIBSCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (chan->type == IIO_INTENSITY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) chip->settings.als_gain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) chip->settings.als_gain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) chip->settings.als_gain = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) case 120:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) chip->settings.als_gain = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) chip->settings.prox_gain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) chip->settings.prox_gain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) chip->settings.prox_gain = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) chip->settings.prox_gain = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) case IIO_CHAN_INFO_CALIBBIAS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (val < TSL2772_ALS_GAIN_TRIM_MIN ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) val > TSL2772_ALS_GAIN_TRIM_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) chip->settings.als_gain_trim = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) case IIO_CHAN_INFO_INT_TIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) if (val != 0 || val2 < tsl2772_int_time_avail[chip->id][1] ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) val2 > tsl2772_int_time_avail[chip->id][5])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) chip->settings.als_time = 256 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) (val2 / tsl2772_int_time_avail[chip->id][3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) return tsl2772_invoke_change(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) static DEVICE_ATTR_RW(in_illuminance0_target_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) static DEVICE_ATTR_WO(in_illuminance0_calibrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) static DEVICE_ATTR_WO(in_proximity0_calibrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) static DEVICE_ATTR_RW(in_illuminance0_lux_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) /* Use the default register values to identify the Taos device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) static int tsl2772_device_id_verif(int id, int target)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) switch (target) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) case tsl2571:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) case tsl2671:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) case tsl2771:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) return (id & 0xf0) == TRITON_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) case tmd2671:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) case tmd2771:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) return (id & 0xf0) == HALIBUT_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) case tsl2572:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) case tsl2672:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) case tmd2672:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) case tsl2772:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) case tmd2772:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) case apds9930:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) return (id & 0xf0) == SWORDFISH_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) static irqreturn_t tsl2772_event_handler(int irq, void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) struct iio_dev *indio_dev = private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) struct tsl2772_chip *chip = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) s64 timestamp = iio_get_time_ns(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) ret = tsl2772_read_status(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) /* What type of interrupt do we need to process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if (ret & TSL2772_STA_PRX_INTR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) iio_push_event(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) IIO_EV_DIR_EITHER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if (ret & TSL2772_STA_ALS_INTR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) iio_push_event(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) IIO_UNMOD_EVENT_CODE(IIO_LIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) IIO_EV_DIR_EITHER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) ret = i2c_smbus_write_byte(chip->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) TSL2772_CMD_REG | TSL2772_CMD_SPL_FN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) TSL2772_CMD_PROXALS_INT_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) dev_err(&chip->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) "%s: failed to clear interrupt status: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) static struct attribute *tsl2772_ALS_device_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) &dev_attr_in_illuminance0_target_input.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) &dev_attr_in_illuminance0_calibrate.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) &dev_attr_in_illuminance0_lux_table.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) static struct attribute *tsl2772_PRX_device_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) &dev_attr_in_proximity0_calibrate.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) static struct attribute *tsl2772_ALSPRX_device_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) &dev_attr_in_illuminance0_target_input.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) &dev_attr_in_illuminance0_calibrate.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) &dev_attr_in_illuminance0_lux_table.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) static struct attribute *tsl2772_PRX2_device_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) &dev_attr_in_proximity0_calibrate.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) static struct attribute *tsl2772_ALSPRX2_device_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) &dev_attr_in_illuminance0_target_input.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) &dev_attr_in_illuminance0_calibrate.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) &dev_attr_in_illuminance0_lux_table.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) &dev_attr_in_proximity0_calibrate.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) static const struct attribute_group tsl2772_device_attr_group_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) [ALS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .attrs = tsl2772_ALS_device_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) [PRX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .attrs = tsl2772_PRX_device_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) [ALSPRX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) .attrs = tsl2772_ALSPRX_device_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) [PRX2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .attrs = tsl2772_PRX2_device_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) [ALSPRX2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .attrs = tsl2772_ALSPRX2_device_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) #define TSL2772_DEVICE_INFO(type)[type] = \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .attrs = &tsl2772_device_attr_group_tbl[type], \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .read_raw = &tsl2772_read_raw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .read_avail = &tsl2772_read_avail, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .write_raw = &tsl2772_write_raw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .read_event_value = &tsl2772_read_event_value, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .write_event_value = &tsl2772_write_event_value, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .read_event_config = &tsl2772_read_interrupt_config, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .write_event_config = &tsl2772_write_interrupt_config, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) static const struct iio_info tsl2772_device_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) TSL2772_DEVICE_INFO(ALS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) TSL2772_DEVICE_INFO(PRX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) TSL2772_DEVICE_INFO(ALSPRX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) TSL2772_DEVICE_INFO(PRX2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) TSL2772_DEVICE_INFO(ALSPRX2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) static const struct iio_event_spec tsl2772_events[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) .dir = IIO_EV_DIR_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .mask_separate = BIT(IIO_EV_INFO_VALUE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) .dir = IIO_EV_DIR_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) .mask_separate = BIT(IIO_EV_INFO_VALUE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .dir = IIO_EV_DIR_EITHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .mask_separate = BIT(IIO_EV_INFO_PERIOD) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) BIT(IIO_EV_INFO_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) static const struct tsl2772_chip_info tsl2772_chip_info_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) [ALS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .channel_with_events = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .type = IIO_LIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .type = IIO_INTENSITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) BIT(IIO_CHAN_INFO_INT_TIME) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) BIT(IIO_CHAN_INFO_CALIBSCALE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) BIT(IIO_CHAN_INFO_CALIBBIAS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .info_mask_separate_available =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) BIT(IIO_CHAN_INFO_INT_TIME) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) BIT(IIO_CHAN_INFO_CALIBSCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .event_spec = tsl2772_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .num_event_specs = ARRAY_SIZE(tsl2772_events),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .type = IIO_INTENSITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .channel = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .channel_without_events = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .type = IIO_LIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .type = IIO_INTENSITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) BIT(IIO_CHAN_INFO_INT_TIME) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) BIT(IIO_CHAN_INFO_CALIBSCALE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) BIT(IIO_CHAN_INFO_CALIBBIAS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .info_mask_separate_available =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) BIT(IIO_CHAN_INFO_INT_TIME) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) BIT(IIO_CHAN_INFO_CALIBSCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .type = IIO_INTENSITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .channel = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .chan_table_elements = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .info = &tsl2772_device_info[ALS],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) [PRX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .channel_with_events = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .type = IIO_PROXIMITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .event_spec = tsl2772_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .num_event_specs = ARRAY_SIZE(tsl2772_events),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .channel_without_events = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .type = IIO_PROXIMITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .chan_table_elements = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .info = &tsl2772_device_info[PRX],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) [ALSPRX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .channel_with_events = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .type = IIO_LIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .type = IIO_INTENSITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) BIT(IIO_CHAN_INFO_INT_TIME) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) BIT(IIO_CHAN_INFO_CALIBSCALE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) BIT(IIO_CHAN_INFO_CALIBBIAS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) .info_mask_separate_available =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) BIT(IIO_CHAN_INFO_INT_TIME) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) BIT(IIO_CHAN_INFO_CALIBSCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) .event_spec = tsl2772_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .num_event_specs = ARRAY_SIZE(tsl2772_events),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .type = IIO_INTENSITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .channel = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .type = IIO_PROXIMITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) .event_spec = tsl2772_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) .num_event_specs = ARRAY_SIZE(tsl2772_events),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .channel_without_events = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) .type = IIO_LIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .type = IIO_INTENSITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) BIT(IIO_CHAN_INFO_INT_TIME) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) BIT(IIO_CHAN_INFO_CALIBSCALE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) BIT(IIO_CHAN_INFO_CALIBBIAS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) .info_mask_separate_available =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) BIT(IIO_CHAN_INFO_INT_TIME) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) BIT(IIO_CHAN_INFO_CALIBSCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .type = IIO_INTENSITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .channel = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .type = IIO_PROXIMITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .chan_table_elements = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .info = &tsl2772_device_info[ALSPRX],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) [PRX2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .channel_with_events = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .type = IIO_PROXIMITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) BIT(IIO_CHAN_INFO_CALIBSCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .info_mask_separate_available =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) BIT(IIO_CHAN_INFO_CALIBSCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .event_spec = tsl2772_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .num_event_specs = ARRAY_SIZE(tsl2772_events),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .channel_without_events = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .type = IIO_PROXIMITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) BIT(IIO_CHAN_INFO_CALIBSCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .info_mask_separate_available =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) BIT(IIO_CHAN_INFO_CALIBSCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .chan_table_elements = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .info = &tsl2772_device_info[PRX2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) [ALSPRX2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .channel_with_events = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .type = IIO_LIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .type = IIO_INTENSITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) BIT(IIO_CHAN_INFO_INT_TIME) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) BIT(IIO_CHAN_INFO_CALIBSCALE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) BIT(IIO_CHAN_INFO_CALIBBIAS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .info_mask_separate_available =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) BIT(IIO_CHAN_INFO_INT_TIME) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) BIT(IIO_CHAN_INFO_CALIBSCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) .event_spec = tsl2772_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .num_event_specs = ARRAY_SIZE(tsl2772_events),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .type = IIO_INTENSITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .channel = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .type = IIO_PROXIMITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) BIT(IIO_CHAN_INFO_CALIBSCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .info_mask_separate_available =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) BIT(IIO_CHAN_INFO_CALIBSCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .event_spec = tsl2772_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .num_event_specs = ARRAY_SIZE(tsl2772_events),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .channel_without_events = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .type = IIO_LIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .type = IIO_INTENSITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) BIT(IIO_CHAN_INFO_INT_TIME) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) BIT(IIO_CHAN_INFO_CALIBSCALE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) BIT(IIO_CHAN_INFO_CALIBBIAS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .info_mask_separate_available =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) BIT(IIO_CHAN_INFO_INT_TIME) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) BIT(IIO_CHAN_INFO_CALIBSCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .type = IIO_INTENSITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .channel = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .type = IIO_PROXIMITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) BIT(IIO_CHAN_INFO_CALIBSCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .info_mask_separate_available =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) BIT(IIO_CHAN_INFO_CALIBSCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) .chan_table_elements = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) .info = &tsl2772_device_info[ALSPRX2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) static int tsl2772_probe(struct i2c_client *clientp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) struct tsl2772_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) indio_dev = devm_iio_device_alloc(&clientp->dev, sizeof(*chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) chip = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) chip->client = clientp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) i2c_set_clientdata(clientp, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) chip->supplies[TSL2772_SUPPLY_VDD].supply = "vdd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) chip->supplies[TSL2772_SUPPLY_VDDIO].supply = "vddio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) ret = devm_regulator_bulk_get(&clientp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) ARRAY_SIZE(chip->supplies),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) chip->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) return dev_err_probe(&clientp->dev, ret, "Failed to get regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) ret = regulator_bulk_enable(ARRAY_SIZE(chip->supplies), chip->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) dev_err(&clientp->dev, "Failed to enable regulators: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) ret = devm_add_action_or_reset(&clientp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) tsl2772_disable_regulators_action,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) dev_err(&clientp->dev, "Failed to setup regulator cleanup action %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) usleep_range(TSL2772_BOOT_MIN_SLEEP_TIME, TSL2772_BOOT_MAX_SLEEP_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) ret = i2c_smbus_read_byte_data(chip->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) TSL2772_CMD_REG | TSL2772_CHIPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) if (tsl2772_device_id_verif(ret, id->driver_data) <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) dev_info(&chip->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) "%s: i2c device found does not match expected id\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) ret = i2c_smbus_write_byte(clientp, TSL2772_CMD_REG | TSL2772_CNTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) dev_err(&clientp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) "%s: Failed to write to CMD register: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) mutex_init(&chip->als_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) mutex_init(&chip->prox_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) chip->tsl2772_chip_status = TSL2772_CHIP_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) chip->pdata = dev_get_platdata(&clientp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) chip->id = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) chip->chip_info =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) &tsl2772_chip_info_tbl[device_channel_config[id->driver_data]];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) indio_dev->info = chip->chip_info->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) indio_dev->name = chip->client->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) indio_dev->num_channels = chip->chip_info->chan_table_elements;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) if (clientp->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) indio_dev->channels = chip->chip_info->channel_with_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) ret = devm_request_threaded_irq(&clientp->dev, clientp->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) &tsl2772_event_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) IRQF_TRIGGER_FALLING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) "TSL2772_event",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) dev_err(&clientp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) "%s: irq request failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) indio_dev->channels = chip->chip_info->channel_without_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) tsl2772_defaults(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) ret = tsl2772_chip_on(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) ret = devm_add_action_or_reset(&clientp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) tsl2772_chip_off_action,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) return devm_iio_device_register(&clientp->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) static int tsl2772_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) struct iio_dev *indio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) struct tsl2772_chip *chip = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) ret = tsl2772_chip_off(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) regulator_bulk_disable(ARRAY_SIZE(chip->supplies), chip->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) static int tsl2772_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) struct iio_dev *indio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) struct tsl2772_chip *chip = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) ret = regulator_bulk_enable(ARRAY_SIZE(chip->supplies), chip->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) usleep_range(TSL2772_BOOT_MIN_SLEEP_TIME, TSL2772_BOOT_MAX_SLEEP_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) return tsl2772_chip_on(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) static const struct i2c_device_id tsl2772_idtable[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) { "tsl2571", tsl2571 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) { "tsl2671", tsl2671 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) { "tmd2671", tmd2671 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) { "tsl2771", tsl2771 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) { "tmd2771", tmd2771 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) { "tsl2572", tsl2572 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) { "tsl2672", tsl2672 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) { "tmd2672", tmd2672 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) { "tsl2772", tsl2772 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) { "tmd2772", tmd2772 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) { "apds9930", apds9930},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) MODULE_DEVICE_TABLE(i2c, tsl2772_idtable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) static const struct of_device_id tsl2772_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) { .compatible = "amstaos,tsl2571" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) { .compatible = "amstaos,tsl2671" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) { .compatible = "amstaos,tmd2671" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) { .compatible = "amstaos,tsl2771" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) { .compatible = "amstaos,tmd2771" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) { .compatible = "amstaos,tsl2572" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) { .compatible = "amstaos,tsl2672" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) { .compatible = "amstaos,tmd2672" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) { .compatible = "amstaos,tsl2772" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) { .compatible = "amstaos,tmd2772" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) { .compatible = "avago,apds9930" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) MODULE_DEVICE_TABLE(of, tsl2772_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) static const struct dev_pm_ops tsl2772_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .suspend = tsl2772_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .resume = tsl2772_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) static struct i2c_driver tsl2772_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) .name = "tsl2772",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .of_match_table = tsl2772_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .pm = &tsl2772_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .id_table = tsl2772_idtable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) .probe = tsl2772_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) module_i2c_driver(tsl2772_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) MODULE_AUTHOR("J. August Brenner <Jon.Brenner@ams.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) MODULE_AUTHOR("Brian Masney <masneyb@onstation.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) MODULE_DESCRIPTION("TAOS tsl2772 ambient and proximity light sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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