^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * tcs3472.c - Support for TAOS TCS3472 color light-to-digital converter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2013 Peter Meerwald <pmeerw@pmeerw.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Color light sensor with 16-bit channels for red, green, blue, clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * 7-bit I2C slave address 0x39 (TCS34721, TCS34723) or 0x29 (TCS34725,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * TCS34727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Datasheet: http://ams.com/eng/content/download/319364/1117183/file/TCS3472_Datasheet_EN_v2.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * TODO: wait time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/iio/events.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TCS3472_DRV_NAME "tcs3472"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TCS3472_COMMAND BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TCS3472_AUTO_INCR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TCS3472_SPECIAL_FUNC (BIT(5) | BIT(6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TCS3472_INTR_CLEAR (TCS3472_COMMAND | TCS3472_SPECIAL_FUNC | 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TCS3472_ENABLE (TCS3472_COMMAND | 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TCS3472_ATIME (TCS3472_COMMAND | 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TCS3472_WTIME (TCS3472_COMMAND | 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TCS3472_AILT (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TCS3472_AIHT (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TCS3472_PERS (TCS3472_COMMAND | 0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TCS3472_CONFIG (TCS3472_COMMAND | 0x0d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TCS3472_CONTROL (TCS3472_COMMAND | 0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TCS3472_ID (TCS3472_COMMAND | 0x12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TCS3472_STATUS (TCS3472_COMMAND | 0x13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TCS3472_CDATA (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TCS3472_RDATA (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TCS3472_GDATA (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TCS3472_BDATA (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x1a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TCS3472_STATUS_AINT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TCS3472_STATUS_AVALID BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TCS3472_ENABLE_AIEN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TCS3472_ENABLE_AEN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TCS3472_ENABLE_PON BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TCS3472_CONTROL_AGAIN_MASK (BIT(0) | BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct tcs3472_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u16 low_thresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u16 high_thresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u8 enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u8 atime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u8 apers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Ensure timestamp is naturally aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u16 chans[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) s64 timestamp __aligned(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) } scan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static const struct iio_event_spec tcs3472_events[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .dir = IIO_EV_DIR_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .mask_separate = BIT(IIO_EV_INFO_VALUE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .dir = IIO_EV_DIR_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .mask_separate = BIT(IIO_EV_INFO_VALUE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .dir = IIO_EV_DIR_EITHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) BIT(IIO_EV_INFO_PERIOD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TCS3472_CHANNEL(_color, _si, _addr) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .type = IIO_INTENSITY, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .modified = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBSCALE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) BIT(IIO_CHAN_INFO_INT_TIME), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .channel2 = IIO_MOD_LIGHT_##_color, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .address = _addr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .scan_index = _si, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .sign = 'u', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .realbits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .endianness = IIO_CPU, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .event_spec = _si ? NULL : tcs3472_events, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .num_event_specs = _si ? 0 : ARRAY_SIZE(tcs3472_events), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static const int tcs3472_agains[] = { 1, 4, 16, 60 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const struct iio_chan_spec tcs3472_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) TCS3472_CHANNEL(CLEAR, 0, TCS3472_CDATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) TCS3472_CHANNEL(RED, 1, TCS3472_RDATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) TCS3472_CHANNEL(GREEN, 2, TCS3472_GDATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) TCS3472_CHANNEL(BLUE, 3, TCS3472_BDATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) IIO_CHAN_SOFT_TIMESTAMP(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int tcs3472_req_data(struct tcs3472_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int tries = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) while (tries--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ret = i2c_smbus_read_byte_data(data->client, TCS3472_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (ret & TCS3472_STATUS_AVALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (tries < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dev_err(&data->client->dev, "data not ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int tcs3472_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct tcs3472_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ret = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ret = tcs3472_req_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ret = i2c_smbus_read_word_data(data->client, chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) *val = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) case IIO_CHAN_INFO_CALIBSCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) *val = tcs3472_agains[data->control &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) TCS3472_CONTROL_AGAIN_MASK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case IIO_CHAN_INFO_INT_TIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) *val2 = (256 - data->atime) * 2400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int tcs3472_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct tcs3472_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) case IIO_CHAN_INFO_CALIBSCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (val2 != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) for (i = 0; i < ARRAY_SIZE(tcs3472_agains); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (val == tcs3472_agains[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) data->control &= ~TCS3472_CONTROL_AGAIN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) data->control |= i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return i2c_smbus_write_byte_data(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) data->client, TCS3472_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) data->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) case IIO_CHAN_INFO_INT_TIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (val != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) for (i = 0; i < 256; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (val2 == (256 - i) * 2400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) data->atime = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return i2c_smbus_write_byte_data(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) data->client, TCS3472_ATIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) data->atime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * Translation from APERS field value to the number of consecutive out-of-range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * clear channel values before an interrupt is generated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const int tcs3472_intr_pers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 0, 1, 2, 3, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int tcs3472_read_event(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) enum iio_event_direction dir, enum iio_event_info info, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct tcs3472_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) unsigned int period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) case IIO_EV_INFO_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) *val = (dir == IIO_EV_DIR_RISING) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) data->high_thresh : data->low_thresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) case IIO_EV_INFO_PERIOD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) period = (256 - data->atime) * 2400 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) tcs3472_intr_pers[data->apers];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) *val = period / USEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) *val2 = period % USEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ret = IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int tcs3472_write_event(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) enum iio_event_direction dir, enum iio_event_info info, int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct tcs3472_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u8 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case IIO_EV_INFO_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) switch (dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) case IIO_EV_DIR_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) command = TCS3472_AIHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) case IIO_EV_DIR_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) command = TCS3472_AILT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ret = i2c_smbus_write_word_data(data->client, command, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (dir == IIO_EV_DIR_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) data->high_thresh = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) data->low_thresh = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) case IIO_EV_INFO_PERIOD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) period = val * USEC_PER_SEC + val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) for (i = 1; i < ARRAY_SIZE(tcs3472_intr_pers) - 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (period <= (256 - data->atime) * 2400 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) tcs3472_intr_pers[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ret = i2c_smbus_write_byte_data(data->client, TCS3472_PERS, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) data->apers = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int tcs3472_read_event_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) enum iio_event_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct tcs3472_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ret = !!(data->enable & TCS3472_ENABLE_AIEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static int tcs3472_write_event_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) enum iio_event_direction dir, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct tcs3472_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u8 enable_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) enable_old = data->enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) data->enable |= TCS3472_ENABLE_AIEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) data->enable &= ~TCS3472_ENABLE_AIEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (enable_old != data->enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ret = i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) data->enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) data->enable = enable_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static irqreturn_t tcs3472_event_handler(int irq, void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct iio_dev *indio_dev = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct tcs3472_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ret = i2c_smbus_read_byte_data(data->client, TCS3472_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (ret >= 0 && (ret & TCS3472_STATUS_AINT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) iio_push_event(indio_dev, IIO_UNMOD_EVENT_CODE(IIO_INTENSITY, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) IIO_EV_DIR_EITHER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) i2c_smbus_read_byte_data(data->client, TCS3472_INTR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static irqreturn_t tcs3472_trigger_handler(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct tcs3472_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int i, j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int ret = tcs3472_req_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) for_each_set_bit(i, indio_dev->active_scan_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) indio_dev->masklength) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ret = i2c_smbus_read_word_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) TCS3472_CDATA + 2*i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) data->scan.chans[j++] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static ssize_t tcs3472_show_int_time_available(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) size_t len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) for (i = 1; i <= 256; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) len += scnprintf(buf + len, PAGE_SIZE - len, "0.%06d ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 2400 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* replace trailing space by newline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) buf[len - 1] = '\n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static IIO_CONST_ATTR(calibscale_available, "1 4 16 60");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static IIO_DEV_ATTR_INT_TIME_AVAIL(tcs3472_show_int_time_available);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static struct attribute *tcs3472_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) &iio_const_attr_calibscale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) &iio_dev_attr_integration_time_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static const struct attribute_group tcs3472_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .attrs = tcs3472_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static const struct iio_info tcs3472_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .read_raw = tcs3472_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .write_raw = tcs3472_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .read_event_value = tcs3472_read_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .write_event_value = tcs3472_write_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .read_event_config = tcs3472_read_event_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .write_event_config = tcs3472_write_event_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .attrs = &tcs3472_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static int tcs3472_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct tcs3472_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (indio_dev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) mutex_init(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) indio_dev->info = &tcs3472_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) indio_dev->name = TCS3472_DRV_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) indio_dev->channels = tcs3472_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) indio_dev->num_channels = ARRAY_SIZE(tcs3472_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ret = i2c_smbus_read_byte_data(data->client, TCS3472_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (ret == 0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dev_info(&client->dev, "TCS34721/34725 found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) else if (ret == 0x4d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev_info(&client->dev, "TCS34723/34727 found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ret = i2c_smbus_read_byte_data(data->client, TCS3472_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) data->control = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ret = i2c_smbus_read_byte_data(data->client, TCS3472_ATIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) data->atime = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ret = i2c_smbus_read_word_data(data->client, TCS3472_AILT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) data->low_thresh = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ret = i2c_smbus_read_word_data(data->client, TCS3472_AIHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) data->high_thresh = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) data->apers = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ret = i2c_smbus_write_byte_data(data->client, TCS3472_PERS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) data->apers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) ret = i2c_smbus_read_byte_data(data->client, TCS3472_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* enable device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) data->enable = ret | TCS3472_ENABLE_PON | TCS3472_ENABLE_AEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) data->enable &= ~TCS3472_ENABLE_AIEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) ret = i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) data->enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ret = iio_triggered_buffer_setup(indio_dev, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) tcs3472_trigger_handler, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (client->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ret = request_threaded_irq(client->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) tcs3472_event_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) IRQF_TRIGGER_FALLING | IRQF_SHARED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) client->name, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) goto buffer_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) goto free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (client->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) free_irq(client->irq, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) buffer_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static int tcs3472_powerdown(struct tcs3472_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u8 enable_mask = TCS3472_ENABLE_AEN | TCS3472_ENABLE_PON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ret = i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) data->enable & ~enable_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) data->enable &= ~enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static int tcs3472_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct iio_dev *indio_dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (client->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) free_irq(client->irq, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) tcs3472_powerdown(iio_priv(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static int tcs3472_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct tcs3472_data *data = iio_priv(i2c_get_clientdata(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) to_i2c_client(dev)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return tcs3472_powerdown(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static int tcs3472_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct tcs3472_data *data = iio_priv(i2c_get_clientdata(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) to_i2c_client(dev)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u8 enable_mask = TCS3472_ENABLE_AEN | TCS3472_ENABLE_PON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ret = i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) data->enable | enable_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) data->enable |= enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static SIMPLE_DEV_PM_OPS(tcs3472_pm_ops, tcs3472_suspend, tcs3472_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static const struct i2c_device_id tcs3472_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) { "tcs3472", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) MODULE_DEVICE_TABLE(i2c, tcs3472_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static struct i2c_driver tcs3472_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .name = TCS3472_DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .pm = &tcs3472_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .probe = tcs3472_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .remove = tcs3472_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .id_table = tcs3472_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) module_i2c_driver(tcs3472_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) MODULE_DESCRIPTION("TCS3472 color light sensors driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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