^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * si1133.c - Support for Silabs SI1133 combined ambient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * light and UV index sensors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2018 Maxime Roussin-Belanger <maxime.roussinbelanger@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/util_macros.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SI1133_REG_PART_ID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SI1133_REG_REV_ID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SI1133_REG_MFR_ID 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SI1133_REG_INFO0 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SI1133_REG_INFO1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SI1133_PART_ID 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SI1133_REG_HOSTIN0 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SI1133_REG_COMMAND 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SI1133_REG_IRQ_ENABLE 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SI1133_REG_RESPONSE1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SI1133_REG_RESPONSE0 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SI1133_REG_IRQ_STATUS 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SI1133_REG_MEAS_RATE 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SI1133_IRQ_CHANNEL_ENABLE 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SI1133_CMD_RESET_CTR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SI1133_CMD_RESET_SW 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SI1133_CMD_FORCE 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SI1133_CMD_START_AUTONOMOUS 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SI1133_CMD_PARAM_SET 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SI1133_CMD_PARAM_QUERY 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SI1133_CMD_PARAM_MASK 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SI1133_CMD_ERR_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SI1133_CMD_SEQ_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SI1133_MAX_CMD_CTR 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SI1133_PARAM_REG_CHAN_LIST 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SI1133_PARAM_REG_ADCCONFIG(x) ((x) * 4) + 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SI1133_PARAM_REG_ADCSENS(x) ((x) * 4) + 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SI1133_PARAM_REG_ADCPOST(x) ((x) * 4) + 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SI1133_ADCMUX_MASK 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SI1133_ADCCONFIG_DECIM_RATE(x) (x) << 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SI1133_ADCSENS_SCALE_MASK 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SI1133_ADCSENS_SCALE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SI1133_ADCSENS_HSIG_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SI1133_ADCSENS_HSIG_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SI1133_ADCSENS_HW_GAIN_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SI1133_ADCSENS_NB_MEAS(x) fls(x) << SI1133_ADCSENS_SCALE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SI1133_ADCPOST_24BIT_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SI1133_ADCPOST_POSTSHIFT_BITQTY(x) (x & GENMASK(2, 0)) << 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SI1133_PARAM_ADCMUX_SMALL_IR 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SI1133_PARAM_ADCMUX_MED_IR 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SI1133_PARAM_ADCMUX_LARGE_IR 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SI1133_PARAM_ADCMUX_WHITE 0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SI1133_PARAM_ADCMUX_LARGE_WHITE 0xD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SI1133_PARAM_ADCMUX_UV 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SI1133_PARAM_ADCMUX_UV_DEEP 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SI1133_ERR_INVALID_CMD 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SI1133_ERR_INVALID_LOCATION_CMD 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SI1133_ERR_SATURATION_ADC_OR_OVERFLOW_ACCUMULATION 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SI1133_ERR_OUTPUT_BUFFER_OVERFLOW 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SI1133_COMPLETION_TIMEOUT_MS 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SI1133_CMD_MINSLEEP_US_LOW 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SI1133_CMD_MINSLEEP_US_HIGH 7500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SI1133_CMD_TIMEOUT_MS 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SI1133_CMD_LUX_TIMEOUT_MS 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SI1133_CMD_TIMEOUT_US SI1133_CMD_TIMEOUT_MS * 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SI1133_REG_HOSTOUT(x) (x) + 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SI1133_MEASUREMENT_FREQUENCY 1250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SI1133_X_ORDER_MASK 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SI1133_Y_ORDER_MASK 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define si1133_get_x_order(m) ((m) & SI1133_X_ORDER_MASK) >> 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define si1133_get_y_order(m) ((m) & SI1133_Y_ORDER_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SI1133_LUX_ADC_MASK 0xE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SI1133_ADC_THRESHOLD 16000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SI1133_INPUT_FRACTION_HIGH 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SI1133_INPUT_FRACTION_LOW 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SI1133_LUX_OUTPUT_FRACTION 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SI1133_LUX_BUFFER_SIZE 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SI1133_MEASURE_BUFFER_SIZE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const int si1133_scale_available[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 1, 2, 4, 8, 16, 32, 64, 128};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static IIO_CONST_ATTR(scale_available, "1 2 4 8 16 32 64 128");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static IIO_CONST_ATTR_INT_TIME_AVAIL("0.0244 0.0488 0.0975 0.195 0.390 0.780 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) "1.560 3.120 6.24 12.48 25.0 50.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* A.K.A. HW_GAIN in datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) enum si1133_int_time {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) _24_4_us = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) _48_8_us = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) _97_5_us = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) _195_0_us = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) _390_0_us = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) _780_0_us = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) _1_560_0_us = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) _3_120_0_us = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) _6_240_0_us = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) _12_480_0_us = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) _25_ms = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) _50_ms = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Integration time in milliseconds, nanoseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const int si1133_int_time_table[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) [_24_4_us] = {0, 24400},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) [_48_8_us] = {0, 48800},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) [_97_5_us] = {0, 97500},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) [_195_0_us] = {0, 195000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) [_390_0_us] = {0, 390000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) [_780_0_us] = {0, 780000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) [_1_560_0_us] = {1, 560000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) [_3_120_0_us] = {3, 120000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) [_6_240_0_us] = {6, 240000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) [_12_480_0_us] = {12, 480000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) [_25_ms] = {25, 000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) [_50_ms] = {50, 000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const struct regmap_range si1133_reg_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) regmap_reg_range(0x00, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) regmap_reg_range(0x0A, 0x0B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) regmap_reg_range(0x0F, 0x0F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) regmap_reg_range(0x10, 0x12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) regmap_reg_range(0x13, 0x2C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const struct regmap_range si1133_reg_ro_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) regmap_reg_range(0x00, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) regmap_reg_range(0x10, 0x2C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const struct regmap_range si1133_precious_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) regmap_reg_range(0x12, 0x12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct regmap_access_table si1133_write_ranges_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .yes_ranges = si1133_reg_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .n_yes_ranges = ARRAY_SIZE(si1133_reg_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .no_ranges = si1133_reg_ro_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .n_no_ranges = ARRAY_SIZE(si1133_reg_ro_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const struct regmap_access_table si1133_read_ranges_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .yes_ranges = si1133_reg_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .n_yes_ranges = ARRAY_SIZE(si1133_reg_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const struct regmap_access_table si1133_precious_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .yes_ranges = si1133_precious_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .n_yes_ranges = ARRAY_SIZE(si1133_precious_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const struct regmap_config si1133_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .max_register = 0x2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .wr_table = &si1133_write_ranges_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .rd_table = &si1133_read_ranges_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .precious_table = &si1133_precious_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct si1133_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Lock protecting one command at a time can be processed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int rsp_seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u8 scan_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u8 adc_sens[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u8 adc_config[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct completion completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct si1133_coeff {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) s16 info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u16 mag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct si1133_lux_coeff {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct si1133_coeff coeff_high[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct si1133_coeff coeff_low[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const struct si1133_lux_coeff lux_coeff = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { 0, 209},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { 1665, 93},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { 2064, 65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {-2671, 234}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { 1921, 29053},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {-1022, 36363},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { 2320, 20789},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { -367, 57909},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {-1774, 38240},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { -608, 46775},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {-1503, 51831},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {-1886, 58928}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int si1133_calculate_polynomial_inner(s32 input, u8 fraction, u16 mag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) s8 shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return ((input << fraction) / mag) << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int si1133_calculate_output(s32 x, s32 y, u8 x_order, u8 y_order,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u8 input_fraction, s8 sign,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) const struct si1133_coeff *coeffs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) s8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int x1 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int x2 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int y1 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int y2 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) shift = ((u16)coeffs->info & 0xFF00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) shift ^= 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) shift += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) shift = -shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (x_order > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) x1 = si1133_calculate_polynomial_inner(x, input_fraction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) coeffs->mag, shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (x_order > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) x2 = x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (y_order > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) y1 = si1133_calculate_polynomial_inner(y, input_fraction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) coeffs->mag, shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (y_order > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) y2 = y1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return sign * x1 * x2 * y1 * y2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * The algorithm is from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * https://siliconlabs.github.io/Gecko_SDK_Doc/efm32zg/html/si1133_8c_source.html#l00716
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int si1133_calc_polynomial(s32 x, s32 y, u8 input_fraction, u8 num_coeff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) const struct si1133_coeff *coeffs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u8 x_order, y_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u8 counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) s8 sign;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int output = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) for (counter = 0; counter < num_coeff; counter++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (coeffs->info < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) sign = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) sign = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) x_order = si1133_get_x_order(coeffs->info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) y_order = si1133_get_y_order(coeffs->info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if ((x_order == 0) && (y_order == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) output +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) sign * coeffs->mag << SI1133_LUX_OUTPUT_FRACTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) output += si1133_calculate_output(x, y, x_order,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) y_order,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) input_fraction, sign,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) coeffs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) coeffs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return abs(output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int si1133_cmd_reset_sw(struct si1133_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct device *dev = &data->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) unsigned int resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) err = regmap_write(data->regmap, SI1133_REG_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) SI1133_CMD_RESET_SW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) timeout = jiffies + msecs_to_jiffies(SI1133_CMD_TIMEOUT_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) while (true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) err = regmap_read(data->regmap, SI1133_REG_RESPONSE0, &resp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (err == -ENXIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) usleep_range(SI1133_CMD_MINSLEEP_US_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) SI1133_CMD_MINSLEEP_US_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if ((resp & SI1133_MAX_CMD_CTR) == SI1133_MAX_CMD_CTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dev_warn(dev, "Timeout on reset ctr resp: %d\n", resp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) data->rsp_seq = SI1133_MAX_CMD_CTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int si1133_parse_response_err(struct device *dev, u32 resp, u8 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) resp &= 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) switch (resp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) case SI1133_ERR_OUTPUT_BUFFER_OVERFLOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) dev_warn(dev, "Output buffer overflow: %#02hhx\n", cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return -EOVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) case SI1133_ERR_SATURATION_ADC_OR_OVERFLOW_ACCUMULATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dev_warn(dev, "Saturation of the ADC or overflow of accumulation: %#02hhx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return -EOVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) case SI1133_ERR_INVALID_LOCATION_CMD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) "Parameter access to an invalid location: %#02hhx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) case SI1133_ERR_INVALID_CMD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dev_warn(dev, "Invalid command %#02hhx\n", cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dev_warn(dev, "Unknown error %#02hhx\n", cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static int si1133_cmd_reset_counter(struct si1133_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int err = regmap_write(data->regmap, SI1133_REG_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) SI1133_CMD_RESET_CTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) data->rsp_seq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int si1133_command(struct si1133_data *data, u8 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct device *dev = &data->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u32 resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) int expected_seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) expected_seq = (data->rsp_seq + 1) & SI1133_MAX_CMD_CTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (cmd == SI1133_CMD_FORCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) reinit_completion(&data->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) err = regmap_write(data->regmap, SI1133_REG_COMMAND, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) dev_warn(dev, "Failed to write command %#02hhx, ret=%d\n", cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (cmd == SI1133_CMD_FORCE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* wait for irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (!wait_for_completion_timeout(&data->completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) msecs_to_jiffies(SI1133_COMPLETION_TIMEOUT_MS))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) err = regmap_read(data->regmap, SI1133_REG_RESPONSE0, &resp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) err = regmap_read_poll_timeout(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) SI1133_REG_RESPONSE0, resp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) (resp & SI1133_CMD_SEQ_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) expected_seq ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) (resp & SI1133_CMD_ERR_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) SI1133_CMD_MINSLEEP_US_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) SI1133_CMD_TIMEOUT_MS * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) "Failed to read command %#02hhx, ret=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) cmd, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (resp & SI1133_CMD_ERR_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) err = si1133_parse_response_err(dev, resp, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) si1133_cmd_reset_counter(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) data->rsp_seq = expected_seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static int si1133_param_set(struct si1133_data *data, u8 param, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) int err = regmap_write(data->regmap, SI1133_REG_HOSTIN0, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return si1133_command(data, SI1133_CMD_PARAM_SET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) (param & SI1133_CMD_PARAM_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static int si1133_param_query(struct si1133_data *data, u8 param, u32 *result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int err = si1133_command(data, SI1133_CMD_PARAM_QUERY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) (param & SI1133_CMD_PARAM_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return regmap_read(data->regmap, SI1133_REG_RESPONSE1, result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define SI1133_CHANNEL(_ch, _type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .type = _type, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .channel = _ch, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) BIT(IIO_CHAN_INFO_SCALE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) BIT(IIO_CHAN_INFO_HARDWAREGAIN), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static const struct iio_chan_spec si1133_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .type = IIO_LIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) SI1133_CHANNEL(SI1133_PARAM_ADCMUX_WHITE, IIO_INTENSITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .channel2 = IIO_MOD_LIGHT_BOTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) SI1133_CHANNEL(SI1133_PARAM_ADCMUX_LARGE_WHITE, IIO_INTENSITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .channel2 = IIO_MOD_LIGHT_BOTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .extend_name = "large",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) SI1133_CHANNEL(SI1133_PARAM_ADCMUX_SMALL_IR, IIO_INTENSITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .extend_name = "small",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .modified = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .channel2 = IIO_MOD_LIGHT_IR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) SI1133_CHANNEL(SI1133_PARAM_ADCMUX_MED_IR, IIO_INTENSITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .modified = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .channel2 = IIO_MOD_LIGHT_IR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) SI1133_CHANNEL(SI1133_PARAM_ADCMUX_LARGE_IR, IIO_INTENSITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .extend_name = "large",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .modified = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .channel2 = IIO_MOD_LIGHT_IR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) SI1133_CHANNEL(SI1133_PARAM_ADCMUX_UV, IIO_UVINDEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) SI1133_CHANNEL(SI1133_PARAM_ADCMUX_UV_DEEP, IIO_UVINDEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .modified = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .channel2 = IIO_MOD_LIGHT_DUV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static int si1133_get_int_time_index(int milliseconds, int nanoseconds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) for (i = 0; i < ARRAY_SIZE(si1133_int_time_table); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (milliseconds == si1133_int_time_table[i][0] &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) nanoseconds == si1133_int_time_table[i][1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static int si1133_set_integration_time(struct si1133_data *data, u8 adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) int milliseconds, int nanoseconds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) index = si1133_get_int_time_index(milliseconds, nanoseconds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (index < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) data->adc_sens[adc] &= 0xF0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) data->adc_sens[adc] |= index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return si1133_param_set(data, SI1133_PARAM_REG_ADCSENS(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) data->adc_sens[adc]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static int si1133_set_chlist(struct si1133_data *data, u8 scan_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* channel list already set, no need to reprogram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (data->scan_mask == scan_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) data->scan_mask = scan_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return si1133_param_set(data, SI1133_PARAM_REG_CHAN_LIST, scan_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static int si1133_chan_set_adcconfig(struct si1133_data *data, u8 adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u8 adc_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) err = si1133_param_set(data, SI1133_PARAM_REG_ADCCONFIG(adc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) adc_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) data->adc_config[adc] = adc_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static int si1133_update_adcconfig(struct si1133_data *data, uint8_t adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) u8 mask, u8 shift, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u32 adc_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) err = si1133_param_query(data, SI1133_PARAM_REG_ADCCONFIG(adc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) &adc_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) adc_config &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) adc_config |= (value << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return si1133_chan_set_adcconfig(data, adc, adc_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static int si1133_set_adcmux(struct si1133_data *data, u8 adc, u8 mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if ((mux & data->adc_config[adc]) == mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return 0; /* mux already set to correct value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return si1133_update_adcconfig(data, adc, SI1133_ADCMUX_MASK, 0, mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static int si1133_force_measurement(struct si1133_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return si1133_command(data, SI1133_CMD_FORCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static int si1133_bulk_read(struct si1133_data *data, u8 start_reg, u8 length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u8 *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) err = si1133_force_measurement(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return regmap_bulk_read(data->regmap, start_reg, buffer, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static int si1133_measure(struct si1133_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) u8 buffer[SI1133_MEASURE_BUFFER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) err = si1133_set_adcmux(data, 0, chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* Deactivate lux measurements if they were active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) err = si1133_set_chlist(data, BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) err = si1133_bulk_read(data, SI1133_REG_HOSTOUT(0), sizeof(buffer),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) *val = sign_extend32(get_unaligned_be24(&buffer[0]), 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static irqreturn_t si1133_threaded_irq_handler(int irq, void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct iio_dev *iio_dev = private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct si1133_data *data = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) u32 irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) err = regmap_read(data->regmap, SI1133_REG_IRQ_STATUS, &irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) dev_err_ratelimited(&iio_dev->dev, "Error reading IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (irq_status != data->scan_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) complete(&data->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static int si1133_scale_to_swgain(int scale_integer, int scale_fractional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) scale_integer = find_closest(scale_integer, si1133_scale_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ARRAY_SIZE(si1133_scale_available));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (scale_integer < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) scale_integer > ARRAY_SIZE(si1133_scale_available) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) scale_fractional != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return scale_integer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static int si1133_chan_set_adcsens(struct si1133_data *data, u8 adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u8 adc_sens)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) err = si1133_param_set(data, SI1133_PARAM_REG_ADCSENS(adc), adc_sens);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) data->adc_sens[adc] = adc_sens;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static int si1133_update_adcsens(struct si1133_data *data, u8 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) u8 shift, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) u32 adc_sens;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) err = si1133_param_query(data, SI1133_PARAM_REG_ADCSENS(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) &adc_sens);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) adc_sens &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) adc_sens |= (value << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return si1133_chan_set_adcsens(data, 0, adc_sens);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static int si1133_get_lux(struct si1133_data *data, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) int lux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) s32 high_vis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) s32 low_vis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) s32 ir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) u8 buffer[SI1133_LUX_BUFFER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* Activate lux channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) err = si1133_set_chlist(data, SI1133_LUX_ADC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) err = si1133_bulk_read(data, SI1133_REG_HOSTOUT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) SI1133_LUX_BUFFER_SIZE, buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) high_vis = sign_extend32(get_unaligned_be24(&buffer[0]), 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) low_vis = sign_extend32(get_unaligned_be24(&buffer[3]), 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) ir = sign_extend32(get_unaligned_be24(&buffer[6]), 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (high_vis > SI1133_ADC_THRESHOLD || ir > SI1133_ADC_THRESHOLD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) lux = si1133_calc_polynomial(high_vis, ir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) SI1133_INPUT_FRACTION_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ARRAY_SIZE(lux_coeff.coeff_high),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) &lux_coeff.coeff_high[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) lux = si1133_calc_polynomial(low_vis, ir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) SI1133_INPUT_FRACTION_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ARRAY_SIZE(lux_coeff.coeff_low),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) &lux_coeff.coeff_low[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) *val = lux >> SI1133_LUX_OUTPUT_FRACTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static int si1133_read_raw(struct iio_dev *iio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct si1133_data *data = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) u8 adc_sens = data->adc_sens[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) case IIO_CHAN_INFO_PROCESSED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) case IIO_LIGHT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) err = si1133_get_lux(data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) case IIO_INTENSITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) case IIO_UVINDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) err = si1133_measure(data, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) case IIO_CHAN_INFO_INT_TIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) case IIO_INTENSITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) case IIO_UVINDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) adc_sens &= SI1133_ADCSENS_HW_GAIN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) *val = si1133_int_time_table[adc_sens][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) *val2 = si1133_int_time_table[adc_sens][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) case IIO_INTENSITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) case IIO_UVINDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) adc_sens &= SI1133_ADCSENS_SCALE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) adc_sens >>= SI1133_ADCSENS_SCALE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) *val = BIT(adc_sens);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) case IIO_CHAN_INFO_HARDWAREGAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) case IIO_INTENSITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) case IIO_UVINDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) adc_sens >>= SI1133_ADCSENS_HSIG_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) *val = adc_sens;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static int si1133_write_raw(struct iio_dev *iio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct si1133_data *data = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) case IIO_INTENSITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) case IIO_UVINDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) val = si1133_scale_to_swgain(val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return si1133_update_adcsens(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) SI1133_ADCSENS_SCALE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) SI1133_ADCSENS_SCALE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) case IIO_CHAN_INFO_INT_TIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return si1133_set_integration_time(data, 0, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) case IIO_CHAN_INFO_HARDWAREGAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) case IIO_INTENSITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) case IIO_UVINDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (val != 0 && val != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return si1133_update_adcsens(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) SI1133_ADCSENS_HSIG_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) SI1133_ADCSENS_HSIG_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static struct attribute *si1133_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) &iio_const_attr_integration_time_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) &iio_const_attr_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static const struct attribute_group si1133_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .attrs = si1133_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static const struct iio_info si1133_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .read_raw = si1133_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .write_raw = si1133_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .attrs = &si1133_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * si1133_init_lux_channels - Configure 3 different channels(adc) (1,2 and 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * The channel configuration for the lux measurement was taken from :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) * https://siliconlabs.github.io/Gecko_SDK_Doc/efm32zg/html/si1133_8c_source.html#l00578
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) * Reserved the channel 0 for the other raw measurements
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static int si1133_init_lux_channels(struct si1133_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) err = si1133_chan_set_adcconfig(data, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) SI1133_ADCCONFIG_DECIM_RATE(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) SI1133_PARAM_ADCMUX_LARGE_WHITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) err = si1133_param_set(data, SI1133_PARAM_REG_ADCPOST(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) SI1133_ADCPOST_24BIT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) SI1133_ADCPOST_POSTSHIFT_BITQTY(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) err = si1133_chan_set_adcsens(data, 1, SI1133_ADCSENS_HSIG_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) SI1133_ADCSENS_NB_MEAS(64) | _48_8_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) err = si1133_chan_set_adcconfig(data, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) SI1133_ADCCONFIG_DECIM_RATE(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) SI1133_PARAM_ADCMUX_LARGE_WHITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) err = si1133_param_set(data, SI1133_PARAM_REG_ADCPOST(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) SI1133_ADCPOST_24BIT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) SI1133_ADCPOST_POSTSHIFT_BITQTY(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) err = si1133_chan_set_adcsens(data, 2, SI1133_ADCSENS_HSIG_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) SI1133_ADCSENS_NB_MEAS(1) | _3_120_0_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) err = si1133_chan_set_adcconfig(data, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) SI1133_ADCCONFIG_DECIM_RATE(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) SI1133_PARAM_ADCMUX_MED_IR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) err = si1133_param_set(data, SI1133_PARAM_REG_ADCPOST(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) SI1133_ADCPOST_24BIT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) SI1133_ADCPOST_POSTSHIFT_BITQTY(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return si1133_chan_set_adcsens(data, 3, SI1133_ADCSENS_HSIG_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) SI1133_ADCSENS_NB_MEAS(64) | _48_8_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static int si1133_initialize(struct si1133_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) err = si1133_cmd_reset_sw(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /* Turn off autonomous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) err = si1133_param_set(data, SI1133_REG_MEAS_RATE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) err = si1133_init_lux_channels(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) return regmap_write(data->regmap, SI1133_REG_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) SI1133_IRQ_CHANNEL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static int si1133_validate_ids(struct iio_dev *iio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct si1133_data *data = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) unsigned int part_id, rev_id, mfr_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) err = regmap_read(data->regmap, SI1133_REG_PART_ID, &part_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) err = regmap_read(data->regmap, SI1133_REG_REV_ID, &rev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) err = regmap_read(data->regmap, SI1133_REG_MFR_ID, &mfr_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) dev_info(&iio_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) "Device ID part %#02hhx rev %#02hhx mfr %#02hhx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) part_id, rev_id, mfr_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (part_id != SI1133_PART_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) dev_err(&iio_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) "Part ID mismatch got %#02hhx, expected %#02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) part_id, SI1133_PART_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static int si1133_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct si1133_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct iio_dev *iio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) iio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (!iio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) data = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) init_completion(&data->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) data->regmap = devm_regmap_init_i2c(client, &si1133_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (IS_ERR(data->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) err = PTR_ERR(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) dev_err(&client->dev, "Failed to initialise regmap: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) i2c_set_clientdata(client, iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) iio_dev->name = id->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) iio_dev->channels = si1133_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) iio_dev->num_channels = ARRAY_SIZE(si1133_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) iio_dev->info = &si1133_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) iio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) mutex_init(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) err = si1133_validate_ids(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) err = si1133_initialize(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) "Error when initializing chip: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (!client->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) "Required interrupt not provided, cannot proceed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) err = devm_request_threaded_irq(&client->dev, client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) si1133_threaded_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) IRQF_ONESHOT | IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) client->name, iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) dev_warn(&client->dev, "Request irq %d failed: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) client->irq, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return devm_iio_device_register(&client->dev, iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static const struct i2c_device_id si1133_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) { "si1133", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) MODULE_DEVICE_TABLE(i2c, si1133_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) static struct i2c_driver si1133_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .name = "si1133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .probe = si1133_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .id_table = si1133_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) module_i2c_driver(si1133_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) MODULE_AUTHOR("Maxime Roussin-Belanger <maxime.roussinbelanger@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) MODULE_DESCRIPTION("Silabs SI1133, UV index sensor and ambient light sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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