^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * RPR-0521 ROHM Ambient Light and Proximity Sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2015, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * IIO driver for RPR-0521RS (7-bit I2C slave address 0x38).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * TODO: illuminance channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/iio/trigger.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RPR0521_REG_SYSTEM_CTRL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RPR0521_REG_MODE_CTRL 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RPR0521_REG_ALS_CTRL 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RPR0521_REG_PXS_CTRL 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RPR0521_REG_PXS_DATA 0x44 /* 16-bit, little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RPR0521_REG_ALS_DATA0 0x46 /* 16-bit, little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RPR0521_REG_ALS_DATA1 0x48 /* 16-bit, little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RPR0521_REG_INTERRUPT 0x4A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RPR0521_REG_PS_OFFSET_LSB 0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RPR0521_REG_ID 0x92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RPR0521_MODE_ALS_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RPR0521_MODE_PXS_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RPR0521_MODE_MEAS_TIME_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RPR0521_ALS_DATA0_GAIN_MASK GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RPR0521_ALS_DATA0_GAIN_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RPR0521_ALS_DATA1_GAIN_MASK GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RPR0521_ALS_DATA1_GAIN_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RPR0521_PXS_GAIN_MASK GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RPR0521_PXS_GAIN_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RPR0521_PXS_PERSISTENCE_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RPR0521_INTERRUPT_INT_TRIG_PS_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RPR0521_INTERRUPT_INT_TRIG_ALS_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RPR0521_INTERRUPT_INT_REASSERT_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RPR0521_INTERRUPT_ALS_INT_STATUS_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RPR0521_INTERRUPT_PS_INT_STATUS_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RPR0521_MODE_ALS_ENABLE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RPR0521_MODE_ALS_DISABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RPR0521_MODE_PXS_ENABLE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RPR0521_MODE_PXS_DISABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RPR0521_PXS_PERSISTENCE_DRDY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RPR0521_INTERRUPT_INT_TRIG_PS_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RPR0521_INTERRUPT_INT_TRIG_PS_DISABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RPR0521_INTERRUPT_INT_TRIG_ALS_ENABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RPR0521_INTERRUPT_INT_TRIG_ALS_DISABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RPR0521_INTERRUPT_INT_REASSERT_ENABLE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RPR0521_INTERRUPT_INT_REASSERT_DISABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RPR0521_MANUFACT_ID 0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RPR0521_DEFAULT_MEAS_TIME 0x06 /* ALS - 100ms, PXS - 100ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RPR0521_DRV_NAME "RPR0521"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RPR0521_IRQ_NAME "rpr0521_event"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RPR0521_REGMAP_NAME "rpr0521_regmap"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RPR0521_SLEEP_DELAY_MS 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RPR0521_ALS_SCALE_AVAIL "0.007812 0.015625 0.5 1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RPR0521_PXS_SCALE_AVAIL "0.125 0.5 1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct rpr0521_gain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int uscale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static const struct rpr0521_gain rpr0521_als_gain[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {1, 0}, /* x1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {0, 500000}, /* x2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {0, 15625}, /* x64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {0, 7812}, /* x128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static const struct rpr0521_gain rpr0521_pxs_gain[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {1, 0}, /* x1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {0, 500000}, /* x2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {0, 125000}, /* x4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) enum rpr0521_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) RPR0521_CHAN_PXS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) RPR0521_CHAN_ALS_DATA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) RPR0521_CHAN_ALS_DATA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct rpr0521_reg_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u8 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 device_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static const struct rpr0521_reg_desc rpr0521_data_reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) [RPR0521_CHAN_PXS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .address = RPR0521_REG_PXS_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .device_mask = RPR0521_MODE_PXS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) [RPR0521_CHAN_ALS_DATA0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .address = RPR0521_REG_ALS_DATA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .device_mask = RPR0521_MODE_ALS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) [RPR0521_CHAN_ALS_DATA1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .address = RPR0521_REG_ALS_DATA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .device_mask = RPR0521_MODE_ALS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const struct rpr0521_gain_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u8 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const struct rpr0521_gain *gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) } rpr0521_gain[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) [RPR0521_CHAN_PXS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .reg = RPR0521_REG_PXS_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .mask = RPR0521_PXS_GAIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .shift = RPR0521_PXS_GAIN_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .gain = rpr0521_pxs_gain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .size = ARRAY_SIZE(rpr0521_pxs_gain),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) [RPR0521_CHAN_ALS_DATA0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .reg = RPR0521_REG_ALS_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .mask = RPR0521_ALS_DATA0_GAIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .shift = RPR0521_ALS_DATA0_GAIN_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .gain = rpr0521_als_gain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .size = ARRAY_SIZE(rpr0521_als_gain),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) [RPR0521_CHAN_ALS_DATA1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .reg = RPR0521_REG_ALS_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .mask = RPR0521_ALS_DATA1_GAIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .shift = RPR0521_ALS_DATA1_GAIN_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .gain = rpr0521_als_gain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .size = ARRAY_SIZE(rpr0521_als_gain),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct rpr0521_samp_freq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int als_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int als_uhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int pxs_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int pxs_uhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const struct rpr0521_samp_freq rpr0521_samp_freq_i[13] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* {ALS, PXS}, W==currently writable option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0, 0, 0, 0}, /* W0000, 0=standby */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {0, 0, 100, 0}, /* 0001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0, 0, 25, 0}, /* 0010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0, 0, 10, 0}, /* 0011 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0, 0, 2, 500000}, /* 0100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {10, 0, 20, 0}, /* 0101 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {10, 0, 10, 0}, /* W0110 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {10, 0, 2, 500000}, /* 0111 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {2, 500000, 20, 0}, /* 1000, measurement 100ms, sleep 300ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {2, 500000, 10, 0}, /* 1001, measurement 100ms, sleep 300ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {2, 500000, 0, 0}, /* 1010, high sensitivity mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {2, 500000, 2, 500000}, /* W1011, high sensitivity mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {20, 0, 20, 0} /* 1100, ALS_data x 0.5, see specification P.18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct rpr0521_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* protect device params updates (e.g state, gain) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* device active status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) bool als_dev_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) bool pxs_dev_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct iio_trigger *drdy_trigger0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) s64 irq_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* optimize runtime pm ops - enable/disable device only if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) bool als_ps_need_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) bool pxs_ps_need_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) bool als_need_dis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) bool pxs_need_dis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * Ensure correct naturally aligned timestamp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * Note that the read will put garbage data into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * the padding but this should not be a problem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) __le16 channels[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u8 garbage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) s64 ts __aligned(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) } scan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static IIO_CONST_ATTR(in_intensity_scale_available, RPR0521_ALS_SCALE_AVAIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static IIO_CONST_ATTR(in_proximity_scale_available, RPR0521_PXS_SCALE_AVAIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * Start with easy freq first, whole table of freq combinations is more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * complicated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("2.5 10");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static struct attribute *rpr0521_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) &iio_const_attr_in_intensity_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) &iio_const_attr_in_proximity_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) &iio_const_attr_sampling_frequency_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const struct attribute_group rpr0521_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .attrs = rpr0521_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Order of the channel data in buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) enum rpr0521_scan_index_order {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) RPR0521_CHAN_INDEX_PXS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) RPR0521_CHAN_INDEX_BOTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) RPR0521_CHAN_INDEX_IR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const unsigned long rpr0521_available_scan_masks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) BIT(RPR0521_CHAN_INDEX_PXS) | BIT(RPR0521_CHAN_INDEX_BOTH) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) BIT(RPR0521_CHAN_INDEX_IR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static const struct iio_chan_spec rpr0521_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .type = IIO_PROXIMITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .address = RPR0521_CHAN_PXS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) BIT(IIO_CHAN_INFO_OFFSET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .scan_index = RPR0521_CHAN_INDEX_PXS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .scan_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .sign = 'u',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .realbits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .storagebits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .endianness = IIO_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .type = IIO_INTENSITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .modified = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .address = RPR0521_CHAN_ALS_DATA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .channel2 = IIO_MOD_LIGHT_BOTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .scan_index = RPR0521_CHAN_INDEX_BOTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .scan_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .sign = 'u',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .realbits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .storagebits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .endianness = IIO_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .type = IIO_INTENSITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .modified = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .address = RPR0521_CHAN_ALS_DATA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .channel2 = IIO_MOD_LIGHT_IR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .scan_index = RPR0521_CHAN_INDEX_IR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .scan_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .sign = 'u',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .realbits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .storagebits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .endianness = IIO_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int rpr0521_als_enable(struct rpr0521_data *data, u8 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ret = regmap_update_bits(data->regmap, RPR0521_REG_MODE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) RPR0521_MODE_ALS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (status & RPR0521_MODE_ALS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) data->als_dev_en = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) data->als_dev_en = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int rpr0521_pxs_enable(struct rpr0521_data *data, u8 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret = regmap_update_bits(data->regmap, RPR0521_REG_MODE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) RPR0521_MODE_PXS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (status & RPR0521_MODE_PXS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) data->pxs_dev_en = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) data->pxs_dev_en = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * rpr0521_set_power_state - handles runtime PM state and sensors enabled status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * @data: rpr0521 device private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * @on: state to be set for devices in @device_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * @device_mask: bitmask specifying for which device we need to update @on state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * Calls for this function must be balanced so that each ON should have matching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * OFF. Otherwise pm usage_count gets out of sync.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static int rpr0521_set_power_state(struct rpr0521_data *data, bool on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u8 device_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (device_mask & RPR0521_MODE_ALS_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) data->als_ps_need_en = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) data->als_need_dis = !on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (device_mask & RPR0521_MODE_PXS_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) data->pxs_ps_need_en = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) data->pxs_need_dis = !on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * On: _resume() is called only when we are suspended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * Off: _suspend() is called after delay if _resume() is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * called before that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * Note: If either measurement is re-enabled before _suspend(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * both stay enabled until _suspend().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ret = pm_runtime_get_sync(&data->client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) pm_runtime_mark_last_busy(&data->client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ret = pm_runtime_put_autosuspend(&data->client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) dev_err(&data->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) "Failed: rpr0521_set_power_state for %d, ret %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) on, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pm_runtime_put_noidle(&data->client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* If _resume() was not called, enable measurement now. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (data->als_ps_need_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ret = rpr0521_als_enable(data, RPR0521_MODE_ALS_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) data->als_ps_need_en = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (data->pxs_ps_need_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ret = rpr0521_pxs_enable(data, RPR0521_MODE_PXS_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) data->pxs_ps_need_en = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Interrupt register tells if this sensor caused the interrupt or not. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static inline bool rpr0521_is_triggered(struct rpr0521_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ret = regmap_read(data->regmap, RPR0521_REG_INTERRUPT, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return false; /* Reg read failed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (reg &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) (RPR0521_INTERRUPT_ALS_INT_STATUS_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) RPR0521_INTERRUPT_PS_INT_STATUS_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return false; /* Int not from this sensor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* IRQ to trigger handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static irqreturn_t rpr0521_drdy_irq_handler(int irq, void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct iio_dev *indio_dev = private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct rpr0521_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) data->irq_timestamp = iio_get_time_ns(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * We need to wake the thread to read the interrupt reg. It
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * is not possible to do that here because regmap_read takes a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * mutex.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static irqreturn_t rpr0521_drdy_irq_thread(int irq, void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct iio_dev *indio_dev = private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct rpr0521_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (rpr0521_is_triggered(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) iio_trigger_poll_chained(data->drdy_trigger0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static irqreturn_t rpr0521_trigger_consumer_store_time(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* Other trigger polls store time here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (!iio_trigger_using_own(indio_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) pf->timestamp = iio_get_time_ns(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static irqreturn_t rpr0521_trigger_consumer_handler(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct rpr0521_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Use irq timestamp when reasonable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (iio_trigger_using_own(indio_dev) && data->irq_timestamp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) pf->timestamp = data->irq_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) data->irq_timestamp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* Other chained trigger polls get timestamp only here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (!pf->timestamp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) pf->timestamp = iio_get_time_ns(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) err = regmap_bulk_read(data->regmap, RPR0521_REG_PXS_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) data->scan.channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) (3 * 2) + 1); /* 3 * 16-bit + (discarded) int clear reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) iio_push_to_buffers_with_timestamp(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) &data->scan, pf->timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) dev_err(&data->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) "Trigger consumer can't read from sensor.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) pf->timestamp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static int rpr0521_write_int_enable(struct rpr0521_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* Interrupt after each measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) err = regmap_update_bits(data->regmap, RPR0521_REG_PXS_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) RPR0521_PXS_PERSISTENCE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) RPR0521_PXS_PERSISTENCE_DRDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dev_err(&data->client->dev, "PS control reg write fail.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* Ignore latch and mode because of drdy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) err = regmap_write(data->regmap, RPR0521_REG_INTERRUPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) RPR0521_INTERRUPT_INT_REASSERT_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) RPR0521_INTERRUPT_INT_TRIG_ALS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) RPR0521_INTERRUPT_INT_TRIG_PS_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dev_err(&data->client->dev, "Interrupt setup write fail.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static int rpr0521_write_int_disable(struct rpr0521_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* Don't care of clearing mode, assert and latch. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return regmap_write(data->regmap, RPR0521_REG_INTERRUPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) RPR0521_INTERRUPT_INT_TRIG_ALS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) RPR0521_INTERRUPT_INT_TRIG_PS_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * Trigger producer enable / disable. Note that there will be trigs only when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * measurement data is ready to be read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static int rpr0521_pxs_drdy_set_state(struct iio_trigger *trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) bool enable_drdy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct iio_dev *indio_dev = iio_trigger_get_drvdata(trigger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct rpr0521_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (enable_drdy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) err = rpr0521_write_int_enable(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) err = rpr0521_write_int_disable(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) dev_err(&data->client->dev, "rpr0521_pxs_drdy_set_state failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static const struct iio_trigger_ops rpr0521_trigger_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .set_trigger_state = rpr0521_pxs_drdy_set_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static int rpr0521_buffer_preenable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct rpr0521_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) err = rpr0521_set_power_state(data, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) (RPR0521_MODE_PXS_MASK | RPR0521_MODE_ALS_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) dev_err(&data->client->dev, "_buffer_preenable fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static int rpr0521_buffer_postdisable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct rpr0521_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) err = rpr0521_set_power_state(data, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) (RPR0521_MODE_PXS_MASK | RPR0521_MODE_ALS_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) dev_err(&data->client->dev, "_buffer_postdisable fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static const struct iio_buffer_setup_ops rpr0521_buffer_setup_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .preenable = rpr0521_buffer_preenable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .postdisable = rpr0521_buffer_postdisable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static int rpr0521_get_gain(struct rpr0521_data *data, int chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) int *val, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) int ret, reg, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ret = regmap_read(data->regmap, rpr0521_gain[chan].reg, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) idx = (rpr0521_gain[chan].mask & reg) >> rpr0521_gain[chan].shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) *val = rpr0521_gain[chan].gain[idx].scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) *val2 = rpr0521_gain[chan].gain[idx].uscale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static int rpr0521_set_gain(struct rpr0521_data *data, int chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) int val, int val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) int i, idx = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* get gain index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) for (i = 0; i < rpr0521_gain[chan].size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (val == rpr0521_gain[chan].gain[i].scale &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) val2 == rpr0521_gain[chan].gain[i].uscale) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (idx < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return regmap_update_bits(data->regmap, rpr0521_gain[chan].reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) rpr0521_gain[chan].mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) idx << rpr0521_gain[chan].shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static int rpr0521_read_samp_freq(struct rpr0521_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) enum iio_chan_type chan_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) int *val, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) int reg, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) ret = regmap_read(data->regmap, RPR0521_REG_MODE_CTRL, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) reg &= RPR0521_MODE_MEAS_TIME_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (reg >= ARRAY_SIZE(rpr0521_samp_freq_i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) switch (chan_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) case IIO_INTENSITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) *val = rpr0521_samp_freq_i[reg].als_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) *val2 = rpr0521_samp_freq_i[reg].als_uhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) case IIO_PROXIMITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) *val = rpr0521_samp_freq_i[reg].pxs_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) *val2 = rpr0521_samp_freq_i[reg].pxs_uhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static int rpr0521_write_samp_freq_common(struct rpr0521_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) enum iio_chan_type chan_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) int val, int val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * Ignore channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * both pxs and als are setup only to same freq because of simplicity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (val2 != 500000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) i = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) case 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) i = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return regmap_update_bits(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) RPR0521_REG_MODE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) RPR0521_MODE_MEAS_TIME_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static int rpr0521_read_ps_offset(struct rpr0521_data *data, int *offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) __le16 buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ret = regmap_bulk_read(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) RPR0521_REG_PS_OFFSET_LSB, &buffer, sizeof(buffer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) dev_err(&data->client->dev, "Failed to read PS OFFSET register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) *offset = le16_to_cpu(buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static int rpr0521_write_ps_offset(struct rpr0521_data *data, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) __le16 buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) buffer = cpu_to_le16(offset & 0x3ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ret = regmap_raw_write(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) RPR0521_REG_PS_OFFSET_LSB, &buffer, sizeof(buffer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dev_err(&data->client->dev, "Failed to write PS OFFSET register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static int rpr0521_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct iio_chan_spec const *chan, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct rpr0521_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) int busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) u8 device_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) __le16 raw_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (chan->type != IIO_INTENSITY && chan->type != IIO_PROXIMITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) busy = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (busy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) device_mask = rpr0521_data_reg[chan->address].device_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) ret = rpr0521_set_power_state(data, true, device_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) goto rpr0521_read_raw_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) ret = regmap_bulk_read(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) rpr0521_data_reg[chan->address].address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) &raw_data, sizeof(raw_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) rpr0521_set_power_state(data, false, device_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) goto rpr0521_read_raw_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) ret = rpr0521_set_power_state(data, false, device_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) rpr0521_read_raw_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) *val = le16_to_cpu(raw_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) ret = rpr0521_get_gain(data, chan->address, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) ret = rpr0521_read_samp_freq(data, chan->type, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) ret = rpr0521_read_ps_offset(data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static int rpr0521_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct iio_chan_spec const *chan, int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct rpr0521_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ret = rpr0521_set_gain(data, chan->address, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) ret = rpr0521_write_samp_freq_common(data, chan->type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) ret = rpr0521_write_ps_offset(data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static const struct iio_info rpr0521_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .read_raw = rpr0521_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .write_raw = rpr0521_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .attrs = &rpr0521_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static int rpr0521_init(struct rpr0521_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ret = regmap_read(data->regmap, RPR0521_REG_ID, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) dev_err(&data->client->dev, "Failed to read REG_ID register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (id != RPR0521_MANUFACT_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) dev_err(&data->client->dev, "Wrong id, got %x, expected %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) id, RPR0521_MANUFACT_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /* set default measurement time - 100 ms for both ALS and PS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ret = regmap_update_bits(data->regmap, RPR0521_REG_MODE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) RPR0521_MODE_MEAS_TIME_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) RPR0521_DEFAULT_MEAS_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) pr_err("regmap_update_bits returned %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #ifndef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ret = rpr0521_als_enable(data, RPR0521_MODE_ALS_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) ret = rpr0521_pxs_enable(data, RPR0521_MODE_PXS_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) data->irq_timestamp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static int rpr0521_poweroff(struct rpr0521_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) ret = regmap_update_bits(data->regmap, RPR0521_REG_MODE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) RPR0521_MODE_ALS_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) RPR0521_MODE_PXS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) RPR0521_MODE_ALS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) RPR0521_MODE_PXS_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) data->als_dev_en = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) data->pxs_dev_en = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * Int pin keeps state after power off. Set pin to high impedance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * mode to prevent power drain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) ret = regmap_read(data->regmap, RPR0521_REG_INTERRUPT, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) dev_err(&data->client->dev, "Failed to reset int pin.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static bool rpr0521_is_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) case RPR0521_REG_MODE_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) case RPR0521_REG_ALS_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) case RPR0521_REG_PXS_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static const struct regmap_config rpr0521_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .name = RPR0521_REGMAP_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .max_register = RPR0521_REG_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .volatile_reg = rpr0521_is_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static int rpr0521_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct rpr0521_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) regmap = devm_regmap_init_i2c(client, &rpr0521_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) dev_err(&client->dev, "regmap_init failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) data->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) mutex_init(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) indio_dev->info = &rpr0521_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) indio_dev->name = RPR0521_DRV_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) indio_dev->channels = rpr0521_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) indio_dev->num_channels = ARRAY_SIZE(rpr0521_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) ret = rpr0521_init(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) dev_err(&client->dev, "rpr0521 chip init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) ret = pm_runtime_set_active(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) goto err_poweroff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) pm_runtime_enable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) pm_runtime_set_autosuspend_delay(&client->dev, RPR0521_SLEEP_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) pm_runtime_use_autosuspend(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) * If sensor write/read is needed in _probe after _use_autosuspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) * sensor needs to be _resumed first using rpr0521_set_power_state().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) /* IRQ to trigger setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (client->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /* Trigger0 producer setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) data->drdy_trigger0 = devm_iio_trigger_alloc(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) indio_dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) "%s-dev%d", indio_dev->name, indio_dev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (!data->drdy_trigger0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) data->drdy_trigger0->dev.parent = indio_dev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) data->drdy_trigger0->ops = &rpr0521_trigger_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) indio_dev->available_scan_masks = rpr0521_available_scan_masks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) iio_trigger_set_drvdata(data->drdy_trigger0, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /* Ties irq to trigger producer handler. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) ret = devm_request_threaded_irq(&client->dev, client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) rpr0521_drdy_irq_handler, rpr0521_drdy_irq_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) RPR0521_IRQ_NAME, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) dev_err(&client->dev, "request irq %d for trigger0 failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) ret = devm_iio_trigger_register(indio_dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) data->drdy_trigger0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) dev_err(&client->dev, "iio trigger register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * Now whole pipe from physical interrupt (irq defined by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * devicetree to device) to trigger0 output is set up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /* Trigger consumer setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) ret = devm_iio_triggered_buffer_setup(indio_dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) rpr0521_trigger_consumer_store_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) rpr0521_trigger_consumer_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) &rpr0521_buffer_setup_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) dev_err(&client->dev, "iio triggered buffer setup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) err_pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) err_poweroff:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) rpr0521_poweroff(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static int rpr0521_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) struct iio_dev *indio_dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) rpr0521_poweroff(iio_priv(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static int rpr0521_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) struct rpr0521_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /* If measurements are enabled, enable them on resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (!data->als_need_dis)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) data->als_ps_need_en = data->als_dev_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (!data->pxs_need_dis)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) data->pxs_ps_need_en = data->pxs_dev_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /* disable channels and sets {als,pxs}_dev_en to false */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) ret = rpr0521_poweroff(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) regcache_mark_dirty(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) static int rpr0521_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) struct rpr0521_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) regcache_sync(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (data->als_ps_need_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) ret = rpr0521_als_enable(data, RPR0521_MODE_ALS_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) data->als_ps_need_en = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (data->pxs_ps_need_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) ret = rpr0521_pxs_enable(data, RPR0521_MODE_PXS_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) data->pxs_ps_need_en = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) msleep(100); //wait for first measurement result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static const struct dev_pm_ops rpr0521_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) SET_RUNTIME_PM_OPS(rpr0521_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) rpr0521_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) static const struct acpi_device_id rpr0521_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) {"RPR0521", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) MODULE_DEVICE_TABLE(acpi, rpr0521_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) static const struct i2c_device_id rpr0521_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) {"rpr0521", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) MODULE_DEVICE_TABLE(i2c, rpr0521_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) static struct i2c_driver rpr0521_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .name = RPR0521_DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .pm = &rpr0521_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .acpi_match_table = ACPI_PTR(rpr0521_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .probe = rpr0521_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .remove = rpr0521_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .id_table = rpr0521_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) module_i2c_driver(rpr0521_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) MODULE_DESCRIPTION("RPR0521 ROHM Ambient Light and Proximity Sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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