Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2015 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Driver for TXC PA12203001 Proximity and Ambient Light Sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * To do: Interrupt support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define PA12203001_DRIVER_NAME	"pa12203001"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define PA12203001_REG_CFG0		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define PA12203001_REG_CFG1		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define PA12203001_REG_CFG2		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define PA12203001_REG_CFG3		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define PA12203001_REG_ADL		0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define PA12203001_REG_PDH		0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define PA12203001_REG_POFS		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define PA12203001_REG_PSET		0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define PA12203001_ALS_EN_MASK		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define PA12203001_PX_EN_MASK		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define PA12203001_PX_NORMAL_MODE_MASK		GENMASK(7, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define PA12203001_AFSR_MASK		GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define PA12203001_AFSR_SHIFT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define PA12203001_PSCAN			0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /* als range 31000, ps, als disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define PA12203001_REG_CFG0_DEFAULT		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /* led current: 100 mA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define PA12203001_REG_CFG1_DEFAULT		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /* ps mode: normal, interrupts not active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define PA12203001_REG_CFG2_DEFAULT		0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define PA12203001_REG_CFG3_DEFAULT		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define PA12203001_SLEEP_DELAY_MS		3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define PA12203001_CHIP_ENABLE		0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define PA12203001_CHIP_DISABLE		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /* available scales: corresponding to [500, 4000, 7000, 31000]  lux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static const int pa12203001_scales[] = { 7629, 61036, 106813, 473029};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) struct pa12203001_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	/* protect device states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	bool als_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	bool px_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	bool als_needs_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	bool px_needs_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) } regvals[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	{PA12203001_REG_CFG0, PA12203001_REG_CFG0_DEFAULT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	{PA12203001_REG_CFG1, PA12203001_REG_CFG1_DEFAULT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	{PA12203001_REG_CFG2, PA12203001_REG_CFG2_DEFAULT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	{PA12203001_REG_CFG3, PA12203001_REG_CFG3_DEFAULT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	{PA12203001_REG_PSET, PA12203001_PSCAN},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static IIO_CONST_ATTR(in_illuminance_scale_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		      "0.007629 0.061036 0.106813 0.473029");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static struct attribute *pa12203001_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	&iio_const_attr_in_illuminance_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static const struct attribute_group pa12203001_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	.attrs = pa12203001_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static const struct iio_chan_spec pa12203001_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		.type = IIO_LIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 				      BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		.type = IIO_PROXIMITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const struct regmap_range pa12203001_volatile_regs_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	regmap_reg_range(PA12203001_REG_ADL, PA12203001_REG_ADL + 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	regmap_reg_range(PA12203001_REG_PDH, PA12203001_REG_PDH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const struct regmap_access_table pa12203001_volatile_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.yes_ranges = pa12203001_volatile_regs_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.n_yes_ranges = ARRAY_SIZE(pa12203001_volatile_regs_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct regmap_config pa12203001_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.max_register = PA12203001_REG_PSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	.volatile_table = &pa12203001_volatile_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static inline int pa12203001_als_enable(struct pa12203001_data *data, u8 enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	ret = regmap_update_bits(data->map, PA12203001_REG_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 				 PA12203001_ALS_EN_MASK, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	data->als_enabled = !!enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static inline int pa12203001_px_enable(struct pa12203001_data *data, u8 enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	ret = regmap_update_bits(data->map, PA12203001_REG_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 				 PA12203001_PX_EN_MASK, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	data->px_enabled = !!enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int pa12203001_set_power_state(struct pa12203001_data *data, bool on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 				      u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	if (on && (mask & PA12203001_ALS_EN_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		if (data->px_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			ret = pa12203001_als_enable(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 						    PA12203001_ALS_EN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 				goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			data->als_needs_enable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (on && (mask & PA12203001_PX_EN_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		if (data->als_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			ret = pa12203001_px_enable(data, PA12203001_PX_EN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 				goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			data->px_needs_enable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		ret = pm_runtime_get_sync(&data->client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			pm_runtime_put_noidle(&data->client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		pm_runtime_mark_last_busy(&data->client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		ret = pm_runtime_put_autosuspend(&data->client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int pa12203001_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			       struct iio_chan_spec const *chan, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			       int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	struct pa12203001_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	u8 dev_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	unsigned int reg_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	__le16 reg_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		case IIO_LIGHT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			dev_mask = PA12203001_ALS_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			ret = pa12203001_set_power_state(data, true, dev_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			 * ALS ADC value is stored in registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			 * PA12203001_REG_ADL and in PA12203001_REG_ADL + 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			ret = regmap_bulk_read(data->map, PA12203001_REG_ADL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 					       &reg_word, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 			if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 				goto reg_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			*val = le16_to_cpu(reg_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			ret = pa12203001_set_power_state(data, false, dev_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		case IIO_PROXIMITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			dev_mask = PA12203001_PX_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			ret = pa12203001_set_power_state(data, true, dev_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			ret = regmap_read(data->map, PA12203001_REG_PDH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 					  &reg_byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 				goto reg_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			*val = reg_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			ret = pa12203001_set_power_state(data, false, dev_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		ret = regmap_read(data->map, PA12203001_REG_CFG0, &reg_byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		*val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		reg_byte = (reg_byte & PA12203001_AFSR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		*val2 = pa12203001_scales[reg_byte >> 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) reg_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	pa12203001_set_power_state(data, false, dev_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int pa12203001_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 				struct iio_chan_spec const *chan, int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 				int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	struct pa12203001_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	int i, ret, new_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	unsigned int reg_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		ret = regmap_read(data->map, PA12203001_REG_CFG0, &reg_byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		if (val != 0 || ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		for (i = 0; i < ARRAY_SIZE(pa12203001_scales); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 			if (val2 == pa12203001_scales[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 				new_val = i << PA12203001_AFSR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 				return regmap_update_bits(data->map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 							  PA12203001_REG_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 							  PA12203001_AFSR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 							  new_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const struct iio_info pa12203001_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	.read_raw = pa12203001_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.write_raw = pa12203001_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	.attrs = &pa12203001_attr_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static int pa12203001_init(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	struct pa12203001_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	for (i = 0; i < ARRAY_SIZE(regvals); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		ret = regmap_write(data->map, regvals[i].reg, regvals[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int pa12203001_power_chip(struct iio_dev *indio_dev, u8 state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	struct pa12203001_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	ret = pa12203001_als_enable(data, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	ret = pa12203001_px_enable(data, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int pa12203001_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 			    const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	struct pa12203001_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	indio_dev = devm_iio_device_alloc(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 					  sizeof(struct pa12203001_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	data->map = devm_regmap_init_i2c(client, &pa12203001_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	if (IS_ERR(data->map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		return PTR_ERR(data->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	mutex_init(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	indio_dev->info = &pa12203001_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	indio_dev->name = PA12203001_DRIVER_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	indio_dev->channels = pa12203001_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	indio_dev->num_channels = ARRAY_SIZE(pa12203001_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	ret = pa12203001_init(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	ret = pa12203001_power_chip(indio_dev, PA12203001_CHIP_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	ret = pm_runtime_set_active(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	pm_runtime_enable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	pm_runtime_set_autosuspend_delay(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 					 PA12203001_SLEEP_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	pm_runtime_use_autosuspend(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	pa12203001_power_chip(indio_dev, PA12203001_CHIP_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static int pa12203001_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	struct iio_dev *indio_dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	return pa12203001_power_chip(indio_dev, PA12203001_CHIP_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #if defined(CONFIG_PM_SLEEP) || defined(CONFIG_PM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static int pa12203001_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	return pa12203001_power_chip(indio_dev, PA12203001_CHIP_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int pa12203001_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	return pa12203001_power_chip(indio_dev, PA12203001_CHIP_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static int pa12203001_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	struct pa12203001_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	data = iio_priv(i2c_get_clientdata(to_i2c_client(dev)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	if (data->als_needs_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 		pa12203001_als_enable(data, PA12203001_ALS_EN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		data->als_needs_enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	if (data->px_needs_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 		pa12203001_px_enable(data, PA12203001_PX_EN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		data->px_needs_enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static const struct dev_pm_ops pa12203001_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	SET_SYSTEM_SLEEP_PM_OPS(pa12203001_suspend, pa12203001_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	SET_RUNTIME_PM_OPS(pa12203001_suspend, pa12203001_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static const struct acpi_device_id pa12203001_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	{ "TXCPA122", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) MODULE_DEVICE_TABLE(acpi, pa12203001_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static const struct i2c_device_id pa12203001_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 		{"txcpa122", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) MODULE_DEVICE_TABLE(i2c, pa12203001_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static struct i2c_driver pa12203001_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 		.name = PA12203001_DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 		.pm = &pa12203001_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		.acpi_match_table = ACPI_PTR(pa12203001_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	.probe = pa12203001_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	.remove = pa12203001_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	.id_table = pa12203001_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) module_i2c_driver(pa12203001_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) MODULE_AUTHOR("Adriana Reus <adriana.reus@intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) MODULE_DESCRIPTION("Driver for TXC PA12203001 Proximity and Light Sensor");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) MODULE_LICENSE("GPL v2");