Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * opt3001.c - Texas Instruments OPT3001 Light Sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Andreas Dannenberg <dannenberg@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Based on previous work from: Felipe Balbi <balbi@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/iio/events.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define OPT3001_RESULT		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define OPT3001_CONFIGURATION	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define OPT3001_LOW_LIMIT	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define OPT3001_HIGH_LIMIT	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define OPT3001_MANUFACTURER_ID	0x7e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define OPT3001_DEVICE_ID	0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define OPT3001_CONFIGURATION_RN_MASK	(0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define OPT3001_CONFIGURATION_RN_AUTO	(0xc << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define OPT3001_CONFIGURATION_CT	BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define OPT3001_CONFIGURATION_M_MASK	(3 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define OPT3001_CONFIGURATION_M_SHUTDOWN (0 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define OPT3001_CONFIGURATION_M_SINGLE	(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define OPT3001_CONFIGURATION_M_CONTINUOUS (2 << 9) /* also 3 << 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define OPT3001_CONFIGURATION_OVF	BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define OPT3001_CONFIGURATION_CRF	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define OPT3001_CONFIGURATION_FH	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define OPT3001_CONFIGURATION_FL	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define OPT3001_CONFIGURATION_L		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define OPT3001_CONFIGURATION_POL	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define OPT3001_CONFIGURATION_ME	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define OPT3001_CONFIGURATION_FC_MASK	(3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /* The end-of-conversion enable is located in the low-limit register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define OPT3001_LOW_LIMIT_EOC_ENABLE	0xc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define OPT3001_REG_EXPONENT(n)		((n) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define OPT3001_REG_MANTISSA(n)		((n) & 0xfff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define OPT3001_INT_TIME_LONG		800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define OPT3001_INT_TIME_SHORT		100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * Time to wait for conversion result to be ready. The device datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  * sect. 6.5 states results are ready after total integration time plus 3ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  * This results in worst-case max values of 113ms or 883ms, respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  * Add some slack to be on the safe side.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define OPT3001_RESULT_READY_SHORT	150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define OPT3001_RESULT_READY_LONG	1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) struct opt3001 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct i2c_client	*client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	struct device		*dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct mutex		lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	bool			ok_to_ignore_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	bool			result_ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	wait_queue_head_t	result_ready_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u16			result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	u32			int_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	u32			mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	u16			high_thresh_mantissa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	u16			low_thresh_mantissa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	u8			high_thresh_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	u8			low_thresh_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	bool			use_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) struct opt3001_scale {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	int	val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	int	val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const struct opt3001_scale opt3001_scales[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		.val = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		.val2 = 950000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		.val = 81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		.val2 = 900000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		.val = 163,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		.val2 = 800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		.val = 327,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		.val2 = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		.val = 655,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		.val2 = 200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		.val = 1310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		.val2 = 400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		.val = 2620,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		.val2 = 800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		.val = 5241,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		.val2 = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		.val = 10483,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		.val2 = 200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		.val = 20966,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		.val2 = 400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		.val = 83865,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		.val2 = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int opt3001_find_scale(const struct opt3001 *opt, int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		int val2, u8 *exponent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	for (i = 0; i < ARRAY_SIZE(opt3001_scales); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		const struct opt3001_scale *scale = &opt3001_scales[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		 * Combine the integer and micro parts for comparison
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		 * purposes. Use milli lux precision to avoid 32-bit integer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		 * overflows.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		if ((val * 1000 + val2 / 1000) <=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 				(scale->val * 1000 + scale->val2 / 1000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			*exponent = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void opt3001_to_iio_ret(struct opt3001 *opt, u8 exponent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		u16 mantissa, int *val, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	int lux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	lux = 10 * (mantissa << exponent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	*val = lux / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	*val2 = (lux - (*val * 1000)) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static void opt3001_set_mode(struct opt3001 *opt, u16 *reg, u16 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	*reg &= ~OPT3001_CONFIGURATION_M_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	*reg |= mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	opt->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static IIO_CONST_ATTR_INT_TIME_AVAIL("0.1 0.8");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static struct attribute *opt3001_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	&iio_const_attr_integration_time_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct attribute_group opt3001_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.attrs = opt3001_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const struct iio_event_spec opt3001_event_spec[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		.type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		.dir = IIO_EV_DIR_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		.mask_separate = BIT(IIO_EV_INFO_VALUE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			BIT(IIO_EV_INFO_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		.type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		.dir = IIO_EV_DIR_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		.mask_separate = BIT(IIO_EV_INFO_VALUE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			BIT(IIO_EV_INFO_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static const struct iio_chan_spec opt3001_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		.type = IIO_LIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 				BIT(IIO_CHAN_INFO_INT_TIME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		.event_spec = opt3001_event_spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		.num_event_specs = ARRAY_SIZE(opt3001_event_spec),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	IIO_CHAN_SOFT_TIMESTAMP(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static int opt3001_get_lux(struct opt3001 *opt, int *val, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	u16 mantissa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	u8 exponent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	u16 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	if (opt->use_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		 * Enable the end-of-conversion interrupt mechanism. Note that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		 * doing so will overwrite the low-level limit value however we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		 * will restore this value later on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		ret = i2c_smbus_write_word_swapped(opt->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 					OPT3001_LOW_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 					OPT3001_LOW_LIMIT_EOC_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			dev_err(opt->dev, "failed to write register %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 					OPT3001_LOW_LIMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		/* Allow IRQ to access the device despite lock being set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		opt->ok_to_ignore_lock = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	/* Reset data-ready indicator flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	opt->result_ready = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	/* Configure for single-conversion mode and start a new conversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		dev_err(opt->dev, "failed to read register %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 				OPT3001_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	reg = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	opt3001_set_mode(opt, &reg, OPT3001_CONFIGURATION_M_SINGLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	ret = i2c_smbus_write_word_swapped(opt->client, OPT3001_CONFIGURATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		dev_err(opt->dev, "failed to write register %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 				OPT3001_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (opt->use_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		/* Wait for the IRQ to indicate the conversion is complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		ret = wait_event_timeout(opt->result_ready_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 				opt->result_ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 				msecs_to_jiffies(OPT3001_RESULT_READY_LONG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 			return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		/* Sleep for result ready time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		timeout = (opt->int_time == OPT3001_INT_TIME_SHORT) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 			OPT3001_RESULT_READY_SHORT : OPT3001_RESULT_READY_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		msleep(timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		/* Check result ready flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		ret = i2c_smbus_read_word_swapped(opt->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 						  OPT3001_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			dev_err(opt->dev, "failed to read register %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 				OPT3001_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		if (!(ret & OPT3001_CONFIGURATION_CRF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 			ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		/* Obtain value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_RESULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 			dev_err(opt->dev, "failed to read register %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 				OPT3001_RESULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		opt->result = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		opt->result_ready = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	if (opt->use_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		/* Disallow IRQ to access the device while lock is active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		opt->ok_to_ignore_lock = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	if (opt->use_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		 * Disable the end-of-conversion interrupt mechanism by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		 * restoring the low-level limit value (clearing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		 * OPT3001_LOW_LIMIT_EOC_ENABLE). Note that selectively clearing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		 * those enable bits would affect the actual limit value due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		 * bit-overlap and therefore can't be done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		value = (opt->low_thresh_exp << 12) | opt->low_thresh_mantissa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		ret = i2c_smbus_write_word_swapped(opt->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 						   OPT3001_LOW_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 						   value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			dev_err(opt->dev, "failed to write register %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 					OPT3001_LOW_LIMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	exponent = OPT3001_REG_EXPONENT(opt->result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	mantissa = OPT3001_REG_MANTISSA(opt->result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	opt3001_to_iio_ret(opt, exponent, mantissa, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int opt3001_get_int_time(struct opt3001 *opt, int *val, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	*val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	*val2 = opt->int_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int opt3001_set_int_time(struct opt3001 *opt, int time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		dev_err(opt->dev, "failed to read register %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 				OPT3001_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	reg = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	switch (time) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	case OPT3001_INT_TIME_SHORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		reg &= ~OPT3001_CONFIGURATION_CT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		opt->int_time = OPT3001_INT_TIME_SHORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	case OPT3001_INT_TIME_LONG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		reg |= OPT3001_CONFIGURATION_CT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		opt->int_time = OPT3001_INT_TIME_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	return i2c_smbus_write_word_swapped(opt->client, OPT3001_CONFIGURATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 			reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static int opt3001_read_raw(struct iio_dev *iio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		struct iio_chan_spec const *chan, int *val, int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	struct opt3001 *opt = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	if (opt->mode == OPT3001_CONFIGURATION_M_CONTINUOUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	if (chan->type != IIO_LIGHT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	mutex_lock(&opt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	case IIO_CHAN_INFO_PROCESSED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		ret = opt3001_get_lux(opt, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	case IIO_CHAN_INFO_INT_TIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		ret = opt3001_get_int_time(opt, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	mutex_unlock(&opt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static int opt3001_write_raw(struct iio_dev *iio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		struct iio_chan_spec const *chan, int val, int val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	struct opt3001 *opt = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	if (opt->mode == OPT3001_CONFIGURATION_M_CONTINUOUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	if (chan->type != IIO_LIGHT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	if (mask != IIO_CHAN_INFO_INT_TIME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	if (val != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	mutex_lock(&opt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	ret = opt3001_set_int_time(opt, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	mutex_unlock(&opt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int opt3001_read_event_value(struct iio_dev *iio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 		const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		enum iio_event_direction dir, enum iio_event_info info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		int *val, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	struct opt3001 *opt = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	int ret = IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	mutex_lock(&opt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	switch (dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	case IIO_EV_DIR_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		opt3001_to_iio_ret(opt, opt->high_thresh_exp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 				opt->high_thresh_mantissa, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	case IIO_EV_DIR_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		opt3001_to_iio_ret(opt, opt->low_thresh_exp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 				opt->low_thresh_mantissa, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	mutex_unlock(&opt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static int opt3001_write_event_value(struct iio_dev *iio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 		const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 		enum iio_event_direction dir, enum iio_event_info info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		int val, int val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	struct opt3001 *opt = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	u16 mantissa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	u16 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	u8 exponent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	mutex_lock(&opt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	ret = opt3001_find_scale(opt, val, val2, &exponent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 		dev_err(opt->dev, "can't find scale for %d.%06u\n", val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	mantissa = (((val * 1000) + (val2 / 1000)) / 10) >> exponent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	value = (exponent << 12) | mantissa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	switch (dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	case IIO_EV_DIR_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 		reg = OPT3001_HIGH_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 		opt->high_thresh_mantissa = mantissa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 		opt->high_thresh_exp = exponent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	case IIO_EV_DIR_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 		reg = OPT3001_LOW_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 		opt->low_thresh_mantissa = mantissa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 		opt->low_thresh_exp = exponent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	ret = i2c_smbus_write_word_swapped(opt->client, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 		dev_err(opt->dev, "failed to write register %02x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	mutex_unlock(&opt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static int opt3001_read_event_config(struct iio_dev *iio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 		const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 		enum iio_event_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	struct opt3001 *opt = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	return opt->mode == OPT3001_CONFIGURATION_M_CONTINUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static int opt3001_write_event_config(struct iio_dev *iio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 		const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 		enum iio_event_direction dir, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	struct opt3001 *opt = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	u16 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	if (state && opt->mode == OPT3001_CONFIGURATION_M_CONTINUOUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	if (!state && opt->mode == OPT3001_CONFIGURATION_M_SHUTDOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	mutex_lock(&opt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	mode = state ? OPT3001_CONFIGURATION_M_CONTINUOUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 		: OPT3001_CONFIGURATION_M_SHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 		dev_err(opt->dev, "failed to read register %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 				OPT3001_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 	reg = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 	opt3001_set_mode(opt, &reg, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	ret = i2c_smbus_write_word_swapped(opt->client, OPT3001_CONFIGURATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 			reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 		dev_err(opt->dev, "failed to write register %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 				OPT3001_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 	mutex_unlock(&opt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static const struct iio_info opt3001_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 	.attrs = &opt3001_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 	.read_raw = opt3001_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 	.write_raw = opt3001_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 	.read_event_value = opt3001_read_event_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 	.write_event_value = opt3001_write_event_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	.read_event_config = opt3001_read_event_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 	.write_event_config = opt3001_write_event_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static int opt3001_read_id(struct opt3001 *opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 	char manufacturer[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 	u16 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 	ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_MANUFACTURER_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 		dev_err(opt->dev, "failed to read register %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 				OPT3001_MANUFACTURER_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 	manufacturer[0] = ret >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 	manufacturer[1] = ret & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 	ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_DEVICE_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 		dev_err(opt->dev, "failed to read register %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 				OPT3001_DEVICE_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 	device_id = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 	dev_info(opt->dev, "Found %c%c OPT%04x\n", manufacturer[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 			manufacturer[1], device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static int opt3001_configure(struct opt3001 *opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 	u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 	ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 		dev_err(opt->dev, "failed to read register %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 				OPT3001_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 	reg = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 	/* Enable automatic full-scale setting mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 	reg &= ~OPT3001_CONFIGURATION_RN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 	reg |= OPT3001_CONFIGURATION_RN_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 	/* Reflect status of the device's integration time setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 	if (reg & OPT3001_CONFIGURATION_CT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 		opt->int_time = OPT3001_INT_TIME_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 		opt->int_time = OPT3001_INT_TIME_SHORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 	/* Ensure device is in shutdown initially */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 	opt3001_set_mode(opt, &reg, OPT3001_CONFIGURATION_M_SHUTDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 	/* Configure for latched window-style comparison operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 	reg |= OPT3001_CONFIGURATION_L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 	reg &= ~OPT3001_CONFIGURATION_POL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 	reg &= ~OPT3001_CONFIGURATION_ME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 	reg &= ~OPT3001_CONFIGURATION_FC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 	ret = i2c_smbus_write_word_swapped(opt->client, OPT3001_CONFIGURATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 			reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 		dev_err(opt->dev, "failed to write register %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 				OPT3001_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 	ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_LOW_LIMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 		dev_err(opt->dev, "failed to read register %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 				OPT3001_LOW_LIMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 	opt->low_thresh_mantissa = OPT3001_REG_MANTISSA(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 	opt->low_thresh_exp = OPT3001_REG_EXPONENT(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 	ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_HIGH_LIMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) 		dev_err(opt->dev, "failed to read register %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 				OPT3001_HIGH_LIMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 	opt->high_thresh_mantissa = OPT3001_REG_MANTISSA(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 	opt->high_thresh_exp = OPT3001_REG_EXPONENT(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static irqreturn_t opt3001_irq(int irq, void *_iio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 	struct iio_dev *iio = _iio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 	struct opt3001 *opt = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) 	bool wake_result_ready_queue = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) 	if (!opt->ok_to_ignore_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) 		mutex_lock(&opt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) 	ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 		dev_err(opt->dev, "failed to read register %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) 				OPT3001_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) 	if ((ret & OPT3001_CONFIGURATION_M_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 			OPT3001_CONFIGURATION_M_CONTINUOUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) 		if (ret & OPT3001_CONFIGURATION_FH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 			iio_push_event(iio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 					IIO_UNMOD_EVENT_CODE(IIO_LIGHT, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) 							IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) 							IIO_EV_DIR_RISING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) 					iio_get_time_ns(iio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) 		if (ret & OPT3001_CONFIGURATION_FL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) 			iio_push_event(iio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) 					IIO_UNMOD_EVENT_CODE(IIO_LIGHT, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) 							IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) 							IIO_EV_DIR_FALLING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) 					iio_get_time_ns(iio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) 	} else if (ret & OPT3001_CONFIGURATION_CRF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) 		ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_RESULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) 			dev_err(opt->dev, "failed to read register %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) 					OPT3001_RESULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) 		opt->result = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) 		opt->result_ready = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 		wake_result_ready_queue = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) 	if (!opt->ok_to_ignore_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) 		mutex_unlock(&opt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) 	if (wake_result_ready_queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) 		wake_up(&opt->result_ready_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static int opt3001_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 		const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) 	struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) 	struct iio_dev *iio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) 	struct opt3001 *opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) 	int irq = client->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) 	iio = devm_iio_device_alloc(dev, sizeof(*opt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) 	if (!iio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) 	opt = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) 	opt->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) 	opt->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) 	mutex_init(&opt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) 	init_waitqueue_head(&opt->result_ready_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) 	i2c_set_clientdata(client, iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) 	ret = opt3001_read_id(opt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) 	ret = opt3001_configure(opt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) 	iio->name = client->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) 	iio->channels = opt3001_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) 	iio->num_channels = ARRAY_SIZE(opt3001_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) 	iio->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) 	iio->info = &opt3001_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) 	ret = devm_iio_device_register(dev, iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) 		dev_err(dev, "failed to register IIO device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) 	/* Make use of INT pin only if valid IRQ no. is given */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) 	if (irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) 		ret = request_threaded_irq(irq, NULL, opt3001_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) 				IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) 				"opt3001", iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) 			dev_err(dev, "failed to request IRQ #%d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) 		opt->use_irq = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) 		dev_dbg(opt->dev, "enabling interrupt-less operation\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static int opt3001_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) 	struct iio_dev *iio = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) 	struct opt3001 *opt = iio_priv(iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) 	u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) 	if (opt->use_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) 		free_irq(client->irq, iio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) 	ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) 		dev_err(opt->dev, "failed to read register %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) 				OPT3001_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) 	reg = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) 	opt3001_set_mode(opt, &reg, OPT3001_CONFIGURATION_M_SHUTDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) 	ret = i2c_smbus_write_word_swapped(opt->client, OPT3001_CONFIGURATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) 			reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) 		dev_err(opt->dev, "failed to write register %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) 				OPT3001_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static const struct i2c_device_id opt3001_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) 	{ "opt3001", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) 	{ } /* Terminating Entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) MODULE_DEVICE_TABLE(i2c, opt3001_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static const struct of_device_id opt3001_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) 	{ .compatible = "ti,opt3001" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) MODULE_DEVICE_TABLE(of, opt3001_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static struct i2c_driver opt3001_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) 	.probe = opt3001_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) 	.remove = opt3001_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) 	.id_table = opt3001_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) 		.name = "opt3001",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) 		.of_match_table = opt3001_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) module_i2c_driver(opt3001_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) MODULE_AUTHOR("Andreas Dannenberg <dannenberg@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) MODULE_DESCRIPTION("Texas Instruments OPT3001 Light Sensor Driver");