^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * max44009.c - Support for MAX44009 Ambient Light Sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2019 Robert Eshleman <bobbyeshleman@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Datasheet: https://datasheets.maximintegrated.com/en/ds/MAX44009.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * TODO: Support continuous mode and configuring from manual mode to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * automatic mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Default I2C address: 0x4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iio/events.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/util_macros.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MAX44009_DRV_NAME "max44009"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Registers in datasheet order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MAX44009_REG_INT_STATUS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MAX44009_REG_INT_EN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MAX44009_REG_CFG 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MAX44009_REG_LUX_HI 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MAX44009_REG_LUX_LO 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MAX44009_REG_UPPER_THR 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MAX44009_REG_LOWER_THR 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MAX44009_REG_THR_TIMER 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MAX44009_CFG_TIM_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MAX44009_CFG_MAN_MODE_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* The maximum rising threshold for the max44009 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MAX44009_MAXIMUM_THRESHOLD 7520256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MAX44009_THRESH_EXP_MASK (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MAX44009_THRESH_EXP_RSHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MAX44009_THRESH_MANT_LSHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MAX44009_THRESH_MANT_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MAX44009_UPPER_THR_MINIMUM 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* The max44009 always scales raw readings by 0.045 and is non-configurable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MAX44009_SCALE_NUMERATOR 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MAX44009_SCALE_DENOMINATOR 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* The fixed-point fractional multiplier for de-scaling threshold values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MAX44009_FRACT_MULT 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static const u32 max44009_int_time_ns_array[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 400000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 100000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 50000000, /* Manual mode only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 25000000, /* Manual mode only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 12500000, /* Manual mode only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 6250000, /* Manual mode only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static const char max44009_int_time_str[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) "0.8 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) "0.4 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "0.2 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) "0.1 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "0.05 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "0.025 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) "0.0125 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) "0.00625";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct max44009_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static const struct iio_event_spec max44009_event_spec[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .dir = IIO_EV_DIR_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .mask_separate = BIT(IIO_EV_INFO_VALUE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) BIT(IIO_EV_INFO_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .dir = IIO_EV_DIR_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .mask_separate = BIT(IIO_EV_INFO_VALUE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) BIT(IIO_EV_INFO_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static const struct iio_chan_spec max44009_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .type = IIO_LIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) BIT(IIO_CHAN_INFO_INT_TIME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .event_spec = max44009_event_spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .num_event_specs = ARRAY_SIZE(max44009_event_spec),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int max44009_read_int_time(struct max44009_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int ret = i2c_smbus_read_byte_data(data->client, MAX44009_REG_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return max44009_int_time_ns_array[ret & MAX44009_CFG_TIM_MASK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int max44009_write_int_time(struct max44009_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int val, int val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int ret, int_time, config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) s64 ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ns = val * NSEC_PER_SEC + val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int_time = find_closest_descending(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ns,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) max44009_int_time_ns_array,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ARRAY_SIZE(max44009_int_time_ns_array));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ret = i2c_smbus_read_byte_data(client, MAX44009_REG_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) config = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) config &= int_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * To set the integration time, the device must also be in manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) config |= MAX44009_CFG_MAN_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return i2c_smbus_write_byte_data(client, MAX44009_REG_CFG, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int max44009_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct iio_chan_spec const *chan, int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct max44009_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (mask == IIO_CHAN_INFO_INT_TIME && chan->type == IIO_LIGHT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ret = max44009_write_int_time(data, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int max44009_write_raw_get_fmt(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return IIO_VAL_INT_PLUS_NANO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int max44009_lux_raw(u8 hi, u8 lo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int mantissa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int exponent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * The mantissa consists of the low nibble of the Lux High Byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * and the low nibble of the Lux Low Byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) mantissa = ((hi & 0xf) << 4) | (lo & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* The exponent byte is just the upper nibble of the Lux High Byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) exponent = (hi >> 4) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * The exponent value is base 2 to the power of the raw exponent byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) exponent = 1 << exponent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return exponent * mantissa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define MAX44009_READ_LUX_XFER_LEN (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int max44009_read_lux_raw(struct max44009_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u8 hireg = MAX44009_REG_LUX_HI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u8 loreg = MAX44009_REG_LUX_LO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u8 lo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u8 hi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct i2c_msg msgs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .addr = data->client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .len = sizeof(hireg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .buf = &hireg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .addr = data->client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .len = sizeof(hi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .buf = &hi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .addr = data->client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .len = sizeof(loreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .buf = &loreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .addr = data->client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .len = sizeof(lo),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .buf = &lo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * Use i2c_transfer instead of smbus read because i2c_transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * does NOT use a stop bit between address write and data read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * Using a stop bit causes disjoint upper/lower byte reads and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * reduces accuracy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ret = i2c_transfer(data->client->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) msgs, MAX44009_READ_LUX_XFER_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (ret != MAX44009_READ_LUX_XFER_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return max44009_lux_raw(hi, lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int max44009_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct iio_chan_spec const *chan, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct max44009_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int lux_raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) case IIO_CHAN_INFO_PROCESSED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case IIO_LIGHT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = max44009_read_lux_raw(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) lux_raw = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) *val = lux_raw * MAX44009_SCALE_NUMERATOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) *val2 = MAX44009_SCALE_DENOMINATOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return IIO_VAL_FRACTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) case IIO_CHAN_INFO_INT_TIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) case IIO_LIGHT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ret = max44009_read_int_time(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) *val2 = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return IIO_VAL_INT_PLUS_NANO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static IIO_CONST_ATTR(illuminance_integration_time_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) max44009_int_time_str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static struct attribute *max44009_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) &iio_const_attr_illuminance_integration_time_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static const struct attribute_group max44009_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .attrs = max44009_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static int max44009_threshold_byte_from_fraction(int integral, int fractional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int mantissa, exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if ((integral <= 0 && fractional <= 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) integral > MAX44009_MAXIMUM_THRESHOLD ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) (integral == MAX44009_MAXIMUM_THRESHOLD && fractional != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Reverse scaling of fixed-point integral */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) mantissa = integral * MAX44009_SCALE_DENOMINATOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) mantissa /= MAX44009_SCALE_NUMERATOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Reverse scaling of fixed-point fractional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) mantissa += fractional / MAX44009_FRACT_MULT *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) (MAX44009_SCALE_DENOMINATOR / MAX44009_SCALE_NUMERATOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) for (exp = 0; mantissa > 0xff; exp++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) mantissa >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) mantissa >>= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) mantissa &= 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) exp <<= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return exp | mantissa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int max44009_get_thr_reg(enum iio_event_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) switch (dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) case IIO_EV_DIR_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return MAX44009_REG_UPPER_THR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) case IIO_EV_DIR_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return MAX44009_REG_LOWER_THR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static int max44009_write_event_value(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) enum iio_event_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) enum iio_event_info info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int val, int val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct max44009_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int reg, threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (info != IIO_EV_INFO_VALUE || chan->type != IIO_LIGHT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) threshold = max44009_threshold_byte_from_fraction(val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (threshold < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) reg = max44009_get_thr_reg(dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return i2c_smbus_write_byte_data(data->client, reg, threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static int max44009_read_threshold(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) enum iio_event_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct max44009_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int byte, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int mantissa, exponent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) reg = max44009_get_thr_reg(dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) byte = i2c_smbus_read_byte_data(data->client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (byte < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) mantissa = byte & MAX44009_THRESH_MANT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) mantissa <<= MAX44009_THRESH_MANT_LSHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * To get the upper threshold, always adds the minimum upper threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * value to the shifted byte value (see datasheet).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (dir == IIO_EV_DIR_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) mantissa += MAX44009_UPPER_THR_MINIMUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * Exponent is base 2 to the power of the threshold exponent byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) exponent = byte & MAX44009_THRESH_EXP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) exponent >>= MAX44009_THRESH_EXP_RSHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return (1 << exponent) * mantissa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static int max44009_read_event_value(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) enum iio_event_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) enum iio_event_info info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int *val, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (chan->type != IIO_LIGHT || type != IIO_EV_TYPE_THRESH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ret = max44009_read_threshold(indio_dev, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) threshold = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) *val = threshold * MAX44009_SCALE_NUMERATOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) *val2 = MAX44009_SCALE_DENOMINATOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return IIO_VAL_FRACTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int max44009_write_event_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) enum iio_event_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct max44009_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (chan->type != IIO_LIGHT || type != IIO_EV_TYPE_THRESH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ret = i2c_smbus_write_byte_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) MAX44009_REG_INT_EN, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * Set device to trigger interrupt immediately upon exceeding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * the threshold limit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return i2c_smbus_write_byte_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) MAX44009_REG_THR_TIMER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static int max44009_read_event_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) enum iio_event_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct max44009_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (chan->type != IIO_LIGHT || type != IIO_EV_TYPE_THRESH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return i2c_smbus_read_byte_data(data->client, MAX44009_REG_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static const struct iio_info max44009_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .read_raw = max44009_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .write_raw = max44009_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .write_raw_get_fmt = max44009_write_raw_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .read_event_value = max44009_read_event_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .read_event_config = max44009_read_event_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .write_event_value = max44009_write_event_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .write_event_config = max44009_write_event_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .attrs = &max44009_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static irqreturn_t max44009_threaded_irq_handler(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct iio_dev *indio_dev = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct max44009_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ret = i2c_smbus_read_byte_data(data->client, MAX44009_REG_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) iio_push_event(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) IIO_UNMOD_EVENT_CODE(IIO_LIGHT, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) IIO_EV_DIR_EITHER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static int max44009_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct max44009_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) indio_dev->info = &max44009_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) indio_dev->name = MAX44009_DRV_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) indio_dev->channels = max44009_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) indio_dev->num_channels = ARRAY_SIZE(max44009_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) mutex_init(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* Clear any stale interrupt bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) ret = i2c_smbus_read_byte_data(client, MAX44009_REG_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (client->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ret = devm_request_threaded_irq(&client->dev, client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) max44009_threaded_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) IRQF_TRIGGER_FALLING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) IRQF_ONESHOT | IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) "max44009_event",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return devm_iio_device_register(&client->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static const struct i2c_device_id max44009_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) { "max44009", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) MODULE_DEVICE_TABLE(i2c, max44009_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static struct i2c_driver max44009_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .name = MAX44009_DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .probe = max44009_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .id_table = max44009_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) module_i2c_driver(max44009_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static const struct of_device_id max44009_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) { .compatible = "maxim,max44009" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) MODULE_DEVICE_TABLE(of, max44009_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) MODULE_AUTHOR("Robert Eshleman <bobbyeshleman@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) MODULE_DESCRIPTION("MAX44009 ambient light sensor driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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