Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * JSA1212 Ambient Light & Proximity Sensor Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2014, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * JSA1212 I2C slave address: 0x44(ADDR tied to GND), 0x45(ADDR tied to VDD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * TODO: Interrupt support, thresholds, range support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /* JSA1212 reg address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define JSA1212_CONF_REG		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define JSA1212_INT_REG			0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define JSA1212_PXS_LT_REG		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define JSA1212_PXS_HT_REG		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define JSA1212_ALS_TH1_REG		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define JSA1212_ALS_TH2_REG		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define JSA1212_ALS_TH3_REG		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define JSA1212_PXS_DATA_REG		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define JSA1212_ALS_DT1_REG		0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define JSA1212_ALS_DT2_REG		0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define JSA1212_ALS_RNG_REG		0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define JSA1212_MAX_REG			0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) /* JSA1212 reg masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define JSA1212_CONF_MASK		0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define JSA1212_INT_MASK		0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define JSA1212_PXS_LT_MASK		0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define JSA1212_PXS_HT_MASK		0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define JSA1212_ALS_TH1_MASK		0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define JSA1212_ALS_TH2_LT_MASK		0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define JSA1212_ALS_TH2_HT_MASK		0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define JSA1212_ALS_TH3_MASK		0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define JSA1212_PXS_DATA_MASK		0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define JSA1212_ALS_DATA_MASK		0x0FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define JSA1212_ALS_DT1_MASK		0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define JSA1212_ALS_DT2_MASK		0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define JSA1212_ALS_RNG_MASK		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) /* JSA1212 CONF REG bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define JSA1212_CONF_PXS_MASK		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define JSA1212_CONF_PXS_ENABLE		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define JSA1212_CONF_PXS_DISABLE	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define JSA1212_CONF_ALS_MASK		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define JSA1212_CONF_ALS_ENABLE		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define JSA1212_CONF_ALS_DISABLE	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define JSA1212_CONF_IRDR_MASK		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /* Proxmity sensing IRDR current sink settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define JSA1212_CONF_IRDR_200MA		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define JSA1212_CONF_IRDR_100MA		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define JSA1212_CONF_PXS_SLP_MASK	0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define JSA1212_CONF_PXS_SLP_0MS	0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define JSA1212_CONF_PXS_SLP_12MS	0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define JSA1212_CONF_PXS_SLP_50MS	0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define JSA1212_CONF_PXS_SLP_75MS	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define JSA1212_CONF_PXS_SLP_100MS	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define JSA1212_CONF_PXS_SLP_200MS	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define JSA1212_CONF_PXS_SLP_400MS	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define JSA1212_CONF_PXS_SLP_800MS	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /* JSA1212 INT REG bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define JSA1212_INT_CTRL_MASK		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define JSA1212_INT_CTRL_EITHER		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define JSA1212_INT_CTRL_BOTH		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define JSA1212_INT_ALS_PRST_MASK	0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define JSA1212_INT_ALS_PRST_1CONV	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define JSA1212_INT_ALS_PRST_4CONV	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define JSA1212_INT_ALS_PRST_8CONV	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define JSA1212_INT_ALS_PRST_16CONV	0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define JSA1212_INT_ALS_FLAG_MASK	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define JSA1212_INT_ALS_FLAG_CLR	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define JSA1212_INT_PXS_PRST_MASK	0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define JSA1212_INT_PXS_PRST_1CONV	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define JSA1212_INT_PXS_PRST_4CONV	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define JSA1212_INT_PXS_PRST_8CONV	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define JSA1212_INT_PXS_PRST_16CONV	0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define JSA1212_INT_PXS_FLAG_MASK	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define JSA1212_INT_PXS_FLAG_CLR	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /* JSA1212 ALS RNG REG bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define JSA1212_ALS_RNG_0_2048		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define JSA1212_ALS_RNG_0_1024		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define JSA1212_ALS_RNG_0_512		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define JSA1212_ALS_RNG_0_256		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define JSA1212_ALS_RNG_0_128		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) /* JSA1212 INT threshold range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define JSA1212_ALS_TH_MIN	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define JSA1212_ALS_TH_MAX	0x0FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define JSA1212_PXS_TH_MIN	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define JSA1212_PXS_TH_MAX	0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define JSA1212_ALS_DELAY_MS	200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define JSA1212_PXS_DELAY_MS	100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define JSA1212_DRIVER_NAME	"jsa1212"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define JSA1212_REGMAP_NAME	"jsa1212_regmap"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) enum jsa1212_op_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	JSA1212_OPMODE_ALS_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	JSA1212_OPMODE_PXS_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct jsa1212_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	u8 als_rng_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	bool als_en; /* ALS enable status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	bool pxs_en; /* proximity enable status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* ALS range idx to val mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const int jsa1212_als_range_val[] = {2048, 1024, 512, 256, 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 						128, 128, 128};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Enables or disables ALS function based on status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int jsa1212_als_enable(struct jsa1212_data *data, u8 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	ret = regmap_update_bits(data->regmap, JSA1212_CONF_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 				JSA1212_CONF_ALS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 				status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	data->als_en = !!status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Enables or disables PXS function based on status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int jsa1212_pxs_enable(struct jsa1212_data *data, u8 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	ret = regmap_update_bits(data->regmap, JSA1212_CONF_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 				JSA1212_CONF_PXS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 				status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	data->pxs_en = !!status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int jsa1212_read_als_data(struct jsa1212_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 				unsigned int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	__le16 als_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	ret = jsa1212_als_enable(data, JSA1212_CONF_ALS_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	/* Delay for data output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	msleep(JSA1212_ALS_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/* Read 12 bit data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	ret = regmap_bulk_read(data->regmap, JSA1212_ALS_DT1_REG, &als_data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		dev_err(&data->client->dev, "als data read err\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		goto als_data_read_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	*val = le16_to_cpu(als_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) als_data_read_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	return jsa1212_als_enable(data, JSA1212_CONF_ALS_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int jsa1212_read_pxs_data(struct jsa1212_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 				unsigned int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	unsigned int pxs_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	ret = jsa1212_pxs_enable(data, JSA1212_CONF_PXS_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	/* Delay for data output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	msleep(JSA1212_PXS_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	/* Read out all data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	ret = regmap_read(data->regmap, JSA1212_PXS_DATA_REG, &pxs_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		dev_err(&data->client->dev, "pxs data read err\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		goto pxs_data_read_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	*val = pxs_data & JSA1212_PXS_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) pxs_data_read_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	return jsa1212_pxs_enable(data, JSA1212_CONF_PXS_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int jsa1212_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 				struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 				int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	struct jsa1212_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		case IIO_LIGHT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			ret = jsa1212_read_als_data(data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		case IIO_PROXIMITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			ret = jsa1212_read_pxs_data(data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 			ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		return ret < 0 ? ret : IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		case IIO_LIGHT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			*val = jsa1212_als_range_val[data->als_rng_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			*val2 = BIT(12); /* Max 12 bit value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			return IIO_VAL_FRACTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static const struct iio_chan_spec jsa1212_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		.type = IIO_LIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		.type = IIO_PROXIMITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const struct iio_info jsa1212_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	.read_raw		= &jsa1212_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int jsa1212_chip_init(struct jsa1212_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	ret = regmap_write(data->regmap, JSA1212_CONF_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 				(JSA1212_CONF_PXS_SLP_50MS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 				JSA1212_CONF_IRDR_200MA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	ret = regmap_write(data->regmap, JSA1212_INT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 				JSA1212_INT_ALS_PRST_4CONV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	data->als_rng_idx = JSA1212_ALS_RNG_0_2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static bool jsa1212_is_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	case JSA1212_PXS_DATA_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	case JSA1212_ALS_DT1_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	case JSA1212_ALS_DT2_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	case JSA1212_INT_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const struct regmap_config jsa1212_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	.name =  JSA1212_REGMAP_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	.max_register = JSA1212_MAX_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	.cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.volatile_reg = jsa1212_is_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int jsa1212_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			 const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	struct jsa1212_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	regmap = devm_regmap_init_i2c(client, &jsa1212_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		dev_err(&client->dev, "Regmap initialization failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	data->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	mutex_init(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	ret = jsa1212_chip_init(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	indio_dev->channels = jsa1212_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	indio_dev->num_channels = ARRAY_SIZE(jsa1212_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	indio_dev->name = JSA1212_DRIVER_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	indio_dev->info = &jsa1212_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		dev_err(&client->dev, "%s: register device failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)  /* power off the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int jsa1212_power_off(struct jsa1212_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	ret = regmap_update_bits(data->regmap, JSA1212_CONF_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 				JSA1212_CONF_ALS_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 				JSA1212_CONF_PXS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 				JSA1212_CONF_ALS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 				JSA1212_CONF_PXS_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		dev_err(&data->client->dev, "power off cmd failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static int jsa1212_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	struct iio_dev *indio_dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	struct jsa1212_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	return jsa1212_power_off(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int jsa1212_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	struct jsa1212_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	data = iio_priv(i2c_get_clientdata(to_i2c_client(dev)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	return jsa1212_power_off(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static int jsa1212_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	struct jsa1212_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	data = iio_priv(i2c_get_clientdata(to_i2c_client(dev)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	if (data->als_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		ret = jsa1212_als_enable(data, JSA1212_CONF_ALS_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 			dev_err(dev, "als resume failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 			goto unlock_and_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	if (data->pxs_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		ret = jsa1212_pxs_enable(data, JSA1212_CONF_PXS_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 			dev_err(dev, "pxs resume failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) unlock_and_ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static SIMPLE_DEV_PM_OPS(jsa1212_pm_ops, jsa1212_suspend, jsa1212_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define JSA1212_PM_OPS (&jsa1212_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define JSA1212_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static const struct acpi_device_id jsa1212_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	{"JSA1212", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MODULE_DEVICE_TABLE(acpi, jsa1212_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static const struct i2c_device_id jsa1212_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	{ JSA1212_DRIVER_NAME, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MODULE_DEVICE_TABLE(i2c, jsa1212_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static struct i2c_driver jsa1212_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		.name	= JSA1212_DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		.pm	= JSA1212_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 		.acpi_match_table = ACPI_PTR(jsa1212_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	.probe		= jsa1212_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	.remove		= jsa1212_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	.id_table	= jsa1212_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) module_i2c_driver(jsa1212_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MODULE_AUTHOR("Sathya Kuppuswamy <sathyanarayanan.kuppuswamy@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) MODULE_DESCRIPTION("JSA1212 proximity/ambient light sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) MODULE_LICENSE("GPL v2");