^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Beomho Seo <beomho.seo@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/iio/events.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* Slave address 0x19 for PS of 7 bit addressing protocol for I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CM36651_I2C_ADDR_PS 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Alert Response Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CM36651_ARA 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Ambient light sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CM36651_CS_CONF1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CM36651_CS_CONF2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CM36651_ALS_WH_M 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CM36651_ALS_WH_L 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CM36651_ALS_WL_M 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CM36651_ALS_WL_L 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CM36651_CS_CONF3 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CM36651_CS_CONF_REG_NUM 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Proximity sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CM36651_PS_CONF1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CM36651_PS_THD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CM36651_PS_CANC 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CM36651_PS_CONF2 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CM36651_PS_REG_NUM 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* CS_CONF1 command code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CM36651_ALS_ENABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CM36651_ALS_DISABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CM36651_ALS_INT_EN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CM36651_ALS_THRES 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* CS_CONF2 command code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CM36651_CS_CONF2_DEFAULT_BIT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* CS_CONF3 channel integration time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CM36651_CS_IT1 0x00 /* Integration time 80 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CM36651_CS_IT2 0x40 /* Integration time 160 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CM36651_CS_IT3 0x80 /* Integration time 320 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CM36651_CS_IT4 0xC0 /* Integration time 640 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* PS_CONF1 command code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CM36651_PS_ENABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CM36651_PS_DISABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CM36651_PS_INT_EN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CM36651_PS_PERS2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CM36651_PS_PERS3 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CM36651_PS_PERS4 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* PS_CONF1 command code: integration time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CM36651_PS_IT1 0x00 /* Integration time 0.32 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CM36651_PS_IT2 0x10 /* Integration time 0.42 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CM36651_PS_IT3 0x20 /* Integration time 0.52 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CM36651_PS_IT4 0x30 /* Integration time 0.64 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* PS_CONF1 command code: duty ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CM36651_PS_DR1 0x00 /* Duty ratio 1/80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CM36651_PS_DR2 0x40 /* Duty ratio 1/160 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CM36651_PS_DR3 0x80 /* Duty ratio 1/320 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CM36651_PS_DR4 0xC0 /* Duty ratio 1/640 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* PS_THD command code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CM36651_PS_INITIAL_THD 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* PS_CANC command code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CM36651_PS_CANC_DEFAULT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* PS_CONF2 command code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CM36651_PS_HYS1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CM36651_PS_HYS2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CM36651_PS_SMART_PERS_EN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CM36651_PS_DIR_INT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CM36651_PS_MS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CM36651_CS_COLOR_NUM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CM36651_CLOSE_PROXIMITY 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CM36651_FAR_PROXIMITY 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CM36651_CS_INT_TIME_AVAIL "0.08 0.16 0.32 0.64"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CM36651_PS_INT_TIME_AVAIL "0.000320 0.000420 0.000520 0.000640"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) enum cm36651_operation_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) CM36651_LIGHT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) CM36651_PROXIMITY_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) CM36651_PROXIMITY_EV_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) enum cm36651_light_channel_idx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) CM36651_LIGHT_CHANNEL_IDX_RED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) CM36651_LIGHT_CHANNEL_IDX_GREEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) CM36651_LIGHT_CHANNEL_IDX_BLUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) CM36651_LIGHT_CHANNEL_IDX_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) enum cm36651_command {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) CM36651_CMD_READ_RAW_LIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) CM36651_CMD_READ_RAW_PROXIMITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) CM36651_CMD_PROX_EV_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) CM36651_CMD_PROX_EV_DIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const u8 cm36651_cs_reg[CM36651_CS_CONF_REG_NUM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) CM36651_CS_CONF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) CM36651_CS_CONF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const u8 cm36651_ps_reg[CM36651_PS_REG_NUM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) CM36651_PS_CONF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) CM36651_PS_THD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) CM36651_PS_CANC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) CM36651_PS_CONF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct cm36651_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) const struct cm36651_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct i2c_client *ps_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct i2c_client *ara_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct regulator *vled_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int cs_int_time[CM36651_CS_COLOR_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int ps_int_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u8 cs_ctrl_regs[CM36651_CS_CONF_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u8 ps_ctrl_regs[CM36651_PS_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u16 color[CM36651_CS_COLOR_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int cm36651_setup_reg(struct cm36651_data *cm36651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct i2c_client *client = cm36651->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct i2c_client *ps_client = cm36651->ps_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* CS initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) cm36651->cs_ctrl_regs[CM36651_CS_CONF1] = CM36651_ALS_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) CM36651_ALS_THRES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) cm36651->cs_ctrl_regs[CM36651_CS_CONF2] = CM36651_CS_CONF2_DEFAULT_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) for (i = 0; i < CM36651_CS_CONF_REG_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ret = i2c_smbus_write_byte_data(client, cm36651_cs_reg[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) cm36651->cs_ctrl_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* PS initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) cm36651->ps_ctrl_regs[CM36651_PS_CONF1] = CM36651_PS_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) CM36651_PS_IT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) cm36651->ps_ctrl_regs[CM36651_PS_THD] = CM36651_PS_INITIAL_THD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) cm36651->ps_ctrl_regs[CM36651_PS_CANC] = CM36651_PS_CANC_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) cm36651->ps_ctrl_regs[CM36651_PS_CONF2] = CM36651_PS_HYS2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) CM36651_PS_DIR_INT | CM36651_PS_SMART_PERS_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) for (i = 0; i < CM36651_PS_REG_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ret = i2c_smbus_write_byte_data(ps_client, cm36651_ps_reg[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) cm36651->ps_ctrl_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Set shutdown mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ret = i2c_smbus_write_byte_data(client, CM36651_CS_CONF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) CM36651_ALS_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ret = i2c_smbus_write_byte_data(cm36651->ps_client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) CM36651_PS_CONF1, CM36651_PS_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int cm36651_read_output(struct cm36651_data *cm36651,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct iio_chan_spec const *chan, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct i2c_client *client = cm36651->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) case IIO_LIGHT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) *val = i2c_smbus_read_word_data(client, chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (*val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ret = i2c_smbus_write_byte_data(client, CM36651_CS_CONF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) CM36651_ALS_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) case IIO_PROXIMITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) *val = i2c_smbus_read_byte(cm36651->ps_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (*val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (!test_bit(CM36651_PROXIMITY_EV_EN, &cm36651->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ret = i2c_smbus_write_byte_data(cm36651->ps_client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) CM36651_PS_CONF1, CM36651_PS_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static irqreturn_t cm36651_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct iio_dev *indio_dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct cm36651_data *cm36651 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct i2c_client *client = cm36651->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int ev_dir, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u64 ev_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * The PS INT pin is an active low signal that PS INT move logic low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * when the object is detect. Once the MCU host received the PS INT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * "LOW" signal, the Host needs to read the data at Alert Response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * Address(ARA) to clear the PS INT signal. After clearing the PS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * INT pin, the PS INT signal toggles from low to high.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ret = i2c_smbus_read_byte(cm36651->ara_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "%s: Data read failed: %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) switch (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) case CM36651_CLOSE_PROXIMITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ev_dir = IIO_EV_DIR_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) case CM36651_FAR_PROXIMITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ev_dir = IIO_EV_DIR_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) "%s: Data read wrong: %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ev_code = IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) CM36651_CMD_READ_RAW_PROXIMITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) IIO_EV_TYPE_THRESH, ev_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) iio_push_event(indio_dev, ev_code, iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int cm36651_set_operation_mode(struct cm36651_data *cm36651, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct i2c_client *client = cm36651->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct i2c_client *ps_client = cm36651->ps_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) case CM36651_CMD_READ_RAW_LIGHT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ret = i2c_smbus_write_byte_data(client, CM36651_CS_CONF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) cm36651->cs_ctrl_regs[CM36651_CS_CONF1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) case CM36651_CMD_READ_RAW_PROXIMITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (test_bit(CM36651_PROXIMITY_EV_EN, &cm36651->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return CM36651_PROXIMITY_EV_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ret = i2c_smbus_write_byte_data(ps_client, CM36651_PS_CONF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) cm36651->ps_ctrl_regs[CM36651_PS_CONF1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) case CM36651_CMD_PROX_EV_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (test_bit(CM36651_PROXIMITY_EV_EN, &cm36651->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) "Already proximity event enable state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) set_bit(CM36651_PROXIMITY_EV_EN, &cm36651->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ret = i2c_smbus_write_byte_data(ps_client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) cm36651_ps_reg[CM36651_PS_CONF1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) CM36651_PS_INT_EN | CM36651_PS_PERS2 | CM36651_PS_IT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) dev_err(&client->dev, "Proximity enable event failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) case CM36651_CMD_PROX_EV_DIS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (!test_bit(CM36651_PROXIMITY_EV_EN, &cm36651->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) "Already proximity event disable state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) clear_bit(CM36651_PROXIMITY_EV_EN, &cm36651->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret = i2c_smbus_write_byte_data(ps_client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) CM36651_PS_CONF1, CM36651_PS_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dev_err(&client->dev, "Write register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int cm36651_read_channel(struct cm36651_data *cm36651,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct iio_chan_spec const *chan, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct i2c_client *client = cm36651->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int cmd, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (chan->type == IIO_LIGHT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) cmd = CM36651_CMD_READ_RAW_LIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) else if (chan->type == IIO_PROXIMITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) cmd = CM36651_CMD_READ_RAW_PROXIMITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ret = cm36651_set_operation_mode(cm36651, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dev_err(&client->dev, "CM36651 set operation mode failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Delay for work after enable operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ret = cm36651_read_output(cm36651, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dev_err(&client->dev, "CM36651 read output failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int cm36651_read_int_time(struct cm36651_data *cm36651,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct iio_chan_spec const *chan, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) case IIO_LIGHT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (cm36651->cs_int_time[chan->address] == CM36651_CS_IT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) *val2 = 80000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) else if (cm36651->cs_int_time[chan->address] == CM36651_CS_IT2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) *val2 = 160000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) else if (cm36651->cs_int_time[chan->address] == CM36651_CS_IT3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) *val2 = 320000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) else if (cm36651->cs_int_time[chan->address] == CM36651_CS_IT4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) *val2 = 640000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) case IIO_PROXIMITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (cm36651->ps_int_time == CM36651_PS_IT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) *val2 = 320;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) else if (cm36651->ps_int_time == CM36651_PS_IT2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) *val2 = 420;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) else if (cm36651->ps_int_time == CM36651_PS_IT3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) *val2 = 520;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) else if (cm36651->ps_int_time == CM36651_PS_IT4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) *val2 = 640;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static int cm36651_write_int_time(struct cm36651_data *cm36651,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct iio_chan_spec const *chan, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct i2c_client *client = cm36651->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct i2c_client *ps_client = cm36651->ps_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) int int_time, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) case IIO_LIGHT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (val == 80000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int_time = CM36651_CS_IT1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) else if (val == 160000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int_time = CM36651_CS_IT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) else if (val == 320000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int_time = CM36651_CS_IT3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) else if (val == 640000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int_time = CM36651_CS_IT4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ret = i2c_smbus_write_byte_data(client, CM36651_CS_CONF3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int_time >> 2 * (chan->address));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) dev_err(&client->dev, "CS integration time write failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) cm36651->cs_int_time[chan->address] = int_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) case IIO_PROXIMITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (val == 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) int_time = CM36651_PS_IT1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) else if (val == 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int_time = CM36651_PS_IT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) else if (val == 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) int_time = CM36651_PS_IT3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) else if (val == 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) int_time = CM36651_PS_IT4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ret = i2c_smbus_write_byte_data(ps_client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) CM36651_PS_CONF1, int_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dev_err(&client->dev, "PS integration time write failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) cm36651->ps_int_time = int_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static int cm36651_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct cm36651_data *cm36651 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) mutex_lock(&cm36651->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ret = cm36651_read_channel(cm36651, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) case IIO_CHAN_INFO_INT_TIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ret = cm36651_read_int_time(cm36651, chan, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) mutex_unlock(&cm36651->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static int cm36651_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct cm36651_data *cm36651 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct i2c_client *client = cm36651->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (mask == IIO_CHAN_INFO_INT_TIME) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ret = cm36651_write_int_time(cm36651, chan, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dev_err(&client->dev, "Integration time write failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static int cm36651_read_prox_thresh(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) enum iio_event_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) enum iio_event_info info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int *val, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct cm36651_data *cm36651 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) *val = cm36651->ps_ctrl_regs[CM36651_PS_THD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static int cm36651_write_prox_thresh(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) enum iio_event_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) enum iio_event_info info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) int val, int val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct cm36651_data *cm36651 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct i2c_client *client = cm36651->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (val < 3 || val > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) cm36651->ps_ctrl_regs[CM36651_PS_THD] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ret = i2c_smbus_write_byte_data(cm36651->ps_client, CM36651_PS_THD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) cm36651->ps_ctrl_regs[CM36651_PS_THD]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) dev_err(&client->dev, "PS threshold write failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static int cm36651_write_prox_event_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) enum iio_event_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct cm36651_data *cm36651 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) int cmd, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) mutex_lock(&cm36651->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) cmd = state ? CM36651_CMD_PROX_EV_EN : CM36651_CMD_PROX_EV_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ret = cm36651_set_operation_mode(cm36651, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) mutex_unlock(&cm36651->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static int cm36651_read_prox_event_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) enum iio_event_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct cm36651_data *cm36651 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int event_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) mutex_lock(&cm36651->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) event_en = test_bit(CM36651_PROXIMITY_EV_EN, &cm36651->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) mutex_unlock(&cm36651->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return event_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define CM36651_LIGHT_CHANNEL(_color, _idx) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .type = IIO_LIGHT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) BIT(IIO_CHAN_INFO_INT_TIME), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .address = _idx, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .modified = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .channel2 = IIO_MOD_LIGHT_##_color, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static const struct iio_event_spec cm36651_event_spec[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .dir = IIO_EV_DIR_EITHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .mask_separate = BIT(IIO_EV_INFO_VALUE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) BIT(IIO_EV_INFO_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static const struct iio_chan_spec cm36651_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .type = IIO_PROXIMITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) BIT(IIO_CHAN_INFO_INT_TIME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .event_spec = cm36651_event_spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .num_event_specs = ARRAY_SIZE(cm36651_event_spec),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) CM36651_LIGHT_CHANNEL(RED, CM36651_LIGHT_CHANNEL_IDX_RED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) CM36651_LIGHT_CHANNEL(GREEN, CM36651_LIGHT_CHANNEL_IDX_GREEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) CM36651_LIGHT_CHANNEL(BLUE, CM36651_LIGHT_CHANNEL_IDX_BLUE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) CM36651_LIGHT_CHANNEL(CLEAR, CM36651_LIGHT_CHANNEL_IDX_CLEAR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static IIO_CONST_ATTR(in_illuminance_integration_time_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) CM36651_CS_INT_TIME_AVAIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static IIO_CONST_ATTR(in_proximity_integration_time_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) CM36651_PS_INT_TIME_AVAIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static struct attribute *cm36651_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) &iio_const_attr_in_illuminance_integration_time_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) &iio_const_attr_in_proximity_integration_time_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static const struct attribute_group cm36651_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .attrs = cm36651_attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static const struct iio_info cm36651_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .read_raw = &cm36651_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .write_raw = &cm36651_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .read_event_value = &cm36651_read_prox_thresh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .write_event_value = &cm36651_write_prox_thresh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .read_event_config = &cm36651_read_prox_event_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .write_event_config = &cm36651_write_prox_event_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .attrs = &cm36651_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static int cm36651_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct cm36651_data *cm36651;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*cm36651));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) cm36651 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) cm36651->vled_reg = devm_regulator_get(&client->dev, "vled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (IS_ERR(cm36651->vled_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) dev_err(&client->dev, "get regulator vled failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return PTR_ERR(cm36651->vled_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ret = regulator_enable(cm36651->vled_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) dev_err(&client->dev, "enable regulator vled failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) cm36651->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) cm36651->ps_client = i2c_new_dummy_device(client->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) CM36651_I2C_ADDR_PS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (IS_ERR(cm36651->ps_client)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) dev_err(&client->dev, "%s: new i2c device failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ret = PTR_ERR(cm36651->ps_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) cm36651->ara_client = i2c_new_dummy_device(client->adapter, CM36651_ARA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (IS_ERR(cm36651->ara_client)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) dev_err(&client->dev, "%s: new i2c device failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ret = PTR_ERR(cm36651->ara_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) goto error_i2c_unregister_ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) mutex_init(&cm36651->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) indio_dev->channels = cm36651_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) indio_dev->num_channels = ARRAY_SIZE(cm36651_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) indio_dev->info = &cm36651_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) indio_dev->name = id->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ret = cm36651_setup_reg(cm36651);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) dev_err(&client->dev, "%s: register setup failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) goto error_i2c_unregister_ara;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ret = request_threaded_irq(client->irq, NULL, cm36651_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) "cm36651", indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) dev_err(&client->dev, "%s: request irq failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) goto error_i2c_unregister_ara;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) dev_err(&client->dev, "%s: regist device failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) goto error_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) error_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) free_irq(client->irq, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) error_i2c_unregister_ara:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) i2c_unregister_device(cm36651->ara_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) error_i2c_unregister_ps:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) i2c_unregister_device(cm36651->ps_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) error_disable_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) regulator_disable(cm36651->vled_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static int cm36651_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct iio_dev *indio_dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct cm36651_data *cm36651 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) regulator_disable(cm36651->vled_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) free_irq(client->irq, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) i2c_unregister_device(cm36651->ps_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) i2c_unregister_device(cm36651->ara_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static const struct i2c_device_id cm36651_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) { "cm36651", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) MODULE_DEVICE_TABLE(i2c, cm36651_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static const struct of_device_id cm36651_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) { .compatible = "capella,cm36651" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) MODULE_DEVICE_TABLE(of, cm36651_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static struct i2c_driver cm36651_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .name = "cm36651",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .of_match_table = cm36651_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .probe = cm36651_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .remove = cm36651_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .id_table = cm36651_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) module_i2c_driver(cm36651_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) MODULE_AUTHOR("Beomho Seo <beomho.seo@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) MODULE_DESCRIPTION("CM36651 proximity/ambient light sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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