Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * CM3323 - Capella Color Light Sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2015, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * IIO driver for CM3323 (7-bit I2C slave address 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * TODO: calibscale to correct the lens factor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define CM3323_DRV_NAME "cm3323"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define CM3323_CMD_CONF		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CM3323_CMD_RED_DATA	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CM3323_CMD_GREEN_DATA	0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CM3323_CMD_BLUE_DATA	0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CM3323_CMD_CLEAR_DATA	0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CM3323_CONF_SD_BIT	BIT(0) /* sensor disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CM3323_CONF_AF_BIT	BIT(1) /* auto/manual force mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CM3323_CONF_IT_MASK	GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define CM3323_CONF_IT_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CM3323_INT_TIME_AVAILABLE "0.04 0.08 0.16 0.32 0.64 1.28"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	int val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) } cm3323_int_time[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	{0, 40000},  /* 40 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	{0, 80000},  /* 80 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	{0, 160000}, /* 160 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	{0, 320000}, /* 320 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	{0, 640000}, /* 640 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	{1, 280000}, /* 1280 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) struct cm3323_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	u16 reg_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define CM3323_COLOR_CHANNEL(_color, _addr) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	.type = IIO_INTENSITY, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	.modified = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	.channel2 = IIO_MOD_LIGHT_##_color, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	.address = _addr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static const struct iio_chan_spec cm3323_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	CM3323_COLOR_CHANNEL(RED, CM3323_CMD_RED_DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	CM3323_COLOR_CHANNEL(GREEN, CM3323_CMD_GREEN_DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	CM3323_COLOR_CHANNEL(BLUE, CM3323_CMD_BLUE_DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	CM3323_COLOR_CHANNEL(CLEAR, CM3323_CMD_CLEAR_DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static IIO_CONST_ATTR_INT_TIME_AVAIL(CM3323_INT_TIME_AVAILABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static struct attribute *cm3323_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	&iio_const_attr_integration_time_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static const struct attribute_group cm3323_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	.attrs = cm3323_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static int cm3323_init(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct cm3323_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	ret = i2c_smbus_read_word_data(data->client, CM3323_CMD_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		dev_err(&data->client->dev, "Error reading reg_conf\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	/* enable sensor and set auto force mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	ret &= ~(CM3323_CONF_SD_BIT | CM3323_CONF_AF_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	ret = i2c_smbus_write_word_data(data->client, CM3323_CMD_CONF, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		dev_err(&data->client->dev, "Error writing reg_conf\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	data->reg_conf = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void cm3323_disable(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	struct iio_dev *indio_dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct cm3323_data *cm_data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	ret = i2c_smbus_write_word_data(cm_data->client, CM3323_CMD_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 					CM3323_CONF_SD_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		dev_err(&cm_data->client->dev, "Error writing reg_conf\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int cm3323_set_it_bits(struct cm3323_data *data, int val, int val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	u16 reg_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	for (i = 0; i < ARRAY_SIZE(cm3323_int_time); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		if (val == cm3323_int_time[i].val &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		    val2 == cm3323_int_time[i].val2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			reg_conf = data->reg_conf & ~CM3323_CONF_IT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			reg_conf |= i << CM3323_CONF_IT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			ret = i2c_smbus_write_word_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 							CM3323_CMD_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 							reg_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			data->reg_conf = reg_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int cm3323_get_it_bits(struct cm3323_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	int bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	bits = (data->reg_conf & CM3323_CONF_IT_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		CM3323_CONF_IT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	if (bits >= ARRAY_SIZE(cm3323_int_time))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	return bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int cm3323_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			   struct iio_chan_spec const *chan, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			   int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	struct cm3323_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		ret = i2c_smbus_read_word_data(data->client, chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		*val = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	case IIO_CHAN_INFO_INT_TIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		ret = cm3323_get_it_bits(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		*val = cm3323_int_time[ret].val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		*val2 = cm3323_int_time[ret].val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int cm3323_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			    struct iio_chan_spec const *chan, int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			    int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct cm3323_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	case IIO_CHAN_INFO_INT_TIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		ret = cm3323_set_it_bits(data, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const struct iio_info cm3323_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.read_raw	= cm3323_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.write_raw	= cm3323_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.attrs		= &cm3323_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int cm3323_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	struct cm3323_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	mutex_init(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	indio_dev->info = &cm3323_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	indio_dev->name = CM3323_DRV_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	indio_dev->channels = cm3323_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	indio_dev->num_channels = ARRAY_SIZE(cm3323_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	ret = cm3323_init(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		dev_err(&client->dev, "cm3323 chip init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	ret = devm_add_action_or_reset(&client->dev, cm3323_disable, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	return devm_iio_device_register(&client->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static const struct i2c_device_id cm3323_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	{"cm3323", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MODULE_DEVICE_TABLE(i2c, cm3323_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static struct i2c_driver cm3323_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		.name = CM3323_DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.probe		= cm3323_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	.id_table	= cm3323_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) module_i2c_driver(cm3323_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MODULE_DESCRIPTION("Capella CM3323 Color Light Sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MODULE_LICENSE("GPL v2");