^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013 Capella Microsystems Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Kevin Tsai <ktsai@capellamicro.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/iio/events.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Registers Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CM32181_REG_ADDR_CMD 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CM32181_REG_ADDR_WH 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CM32181_REG_ADDR_WL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CM32181_REG_ADDR_TEST 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CM32181_REG_ADDR_ALS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CM32181_REG_ADDR_STATUS 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CM32181_REG_ADDR_ID 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Number of Configurable Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CM32181_CONF_REG_NUM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* CMD register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CM32181_CMD_ALS_DISABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CM32181_CMD_ALS_INT_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CM32181_CMD_ALS_THRES_WINDOW BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CM32181_CMD_ALS_PERS_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CM32181_CMD_ALS_PERS_MASK (0x03 << CM32181_CMD_ALS_PERS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CM32181_CMD_ALS_PERS_DEFAULT (0x01 << CM32181_CMD_ALS_PERS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CM32181_CMD_ALS_IT_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CM32181_CMD_ALS_IT_MASK (0x0F << CM32181_CMD_ALS_IT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CM32181_CMD_ALS_IT_DEFAULT (0x00 << CM32181_CMD_ALS_IT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CM32181_CMD_ALS_SM_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CM32181_CMD_ALS_SM_MASK (0x03 << CM32181_CMD_ALS_SM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CM32181_CMD_ALS_SM_DEFAULT (0x01 << CM32181_CMD_ALS_SM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CM32181_LUX_PER_BIT 500 /* ALS_SM=01 IT=800ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CM32181_LUX_PER_BIT_RESOLUTION 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CM32181_LUX_PER_BIT_BASE_IT 800000 /* Based on IT=800ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CM32181_CALIBSCALE_DEFAULT 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CM32181_CALIBSCALE_RESOLUTION 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SMBUS_ALERT_RESPONSE_ADDRESS 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* CPM0 Index 0: device-id (3218 or 32181), 1: Unknown, 2: init_regs_bitmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CPM0_REGS_BITMAP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CPM0_HEADER_SIZE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* CPM1 Index 0: lux_per_bit, 1: calibscale, 2: resolution (100000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CPM1_LUX_PER_BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CPM1_CALIBSCALE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CPM1_SIZE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* CM3218 Family */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static const int cm3218_als_it_bits[] = { 0, 1, 2, 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static const int cm3218_als_it_values[] = { 100000, 200000, 400000, 800000 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* CM32181 Family */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const int cm32181_als_it_bits[] = { 12, 8, 0, 1, 2, 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static const int cm32181_als_it_values[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 25000, 50000, 100000, 200000, 400000, 800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct cm32181_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u16 conf_regs[CM32181_CONF_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned long init_regs_bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int calibscale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int lux_per_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int lux_per_bit_base_it;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int num_als_it;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) const int *als_it_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) const int *als_it_values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int cm32181_read_als_it(struct cm32181_chip *cm32181, int *val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * cm32181_acpi_get_cpm() - Get CPM object from ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @dev: pointer of struct device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @obj_name: pointer of ACPI object name.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @values: pointer of array for return elements.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @count: maximum size of return array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * Convert ACPI CPM table to array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Return: -ENODEV for fail. Otherwise is number of elements.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int cm32181_acpi_get_cpm(struct device *dev, char *obj_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u64 *values, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) union acpi_object *cpm, *elem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) acpi_handle handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) acpi_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) handle = ACPI_HANDLE(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (!handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) status = acpi_evaluate_object(handle, obj_name, NULL, &buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (ACPI_FAILURE(status)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dev_err(dev, "object %s not found\n", obj_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) cpm = buffer.pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (cpm->package.count > count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) dev_warn(dev, "%s table contains %u values, only using first %d values\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) obj_name, cpm->package.count, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) count = min_t(int, cpm->package.count, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) elem = &(cpm->package.elements[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) values[i] = elem->integer.value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) kfree(buffer.pointer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static void cm32181_acpi_parse_cpm_tables(struct cm32181_chip *cm32181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u64 vals[CPM0_HEADER_SIZE + CM32181_CONF_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct device *dev = cm32181->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int i, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) count = cm32181_acpi_get_cpm(dev, "CPM0", vals, ARRAY_SIZE(vals));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (count <= CPM0_HEADER_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) count -= CPM0_HEADER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) cm32181->init_regs_bitmap = vals[CPM0_REGS_BITMAP];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) cm32181->init_regs_bitmap &= GENMASK(count - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) for_each_set_bit(i, &cm32181->init_regs_bitmap, count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) cm32181->conf_regs[i] = vals[CPM0_HEADER_SIZE + i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) count = cm32181_acpi_get_cpm(dev, "CPM1", vals, ARRAY_SIZE(vals));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (count != CPM1_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) cm32181->lux_per_bit = vals[CPM1_LUX_PER_BIT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Check for uncalibrated devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (vals[CPM1_CALIBSCALE] == CM32181_CALIBSCALE_DEFAULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) cm32181->calibscale = vals[CPM1_CALIBSCALE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* CPM1 lux_per_bit is for the current it value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) cm32181_read_als_it(cm32181, &cm32181->lux_per_bit_base_it);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static void cm32181_acpi_parse_cpm_tables(struct cm32181_chip *cm32181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #endif /* CONFIG_ACPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * cm32181_reg_init() - Initialize CM32181 registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * @cm32181: pointer of struct cm32181.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * Initialize CM32181 ambient light sensor register to default values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * Return: 0 for success; otherwise for error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int cm32181_reg_init(struct cm32181_chip *cm32181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct i2c_client *client = cm32181->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) s32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ret = i2c_smbus_read_word_data(client, CM32181_REG_ADDR_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* check device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) switch (ret & 0xFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) case 0x18: /* CM3218 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) cm32181->num_als_it = ARRAY_SIZE(cm3218_als_it_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) cm32181->als_it_bits = cm3218_als_it_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) cm32181->als_it_values = cm3218_als_it_values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) case 0x81: /* CM32181 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) case 0x82: /* CM32182, fully compat. with CM32181 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) cm32181->num_als_it = ARRAY_SIZE(cm32181_als_it_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) cm32181->als_it_bits = cm32181_als_it_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) cm32181->als_it_values = cm32181_als_it_values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Default Values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) cm32181->conf_regs[CM32181_REG_ADDR_CMD] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) CM32181_CMD_ALS_IT_DEFAULT | CM32181_CMD_ALS_SM_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) cm32181->init_regs_bitmap = BIT(CM32181_REG_ADDR_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) cm32181->calibscale = CM32181_CALIBSCALE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) cm32181->lux_per_bit = CM32181_LUX_PER_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) cm32181->lux_per_bit_base_it = CM32181_LUX_PER_BIT_BASE_IT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (ACPI_HANDLE(cm32181->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) cm32181_acpi_parse_cpm_tables(cm32181);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* Initialize registers*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) for_each_set_bit(i, &cm32181->init_regs_bitmap, CM32181_CONF_REG_NUM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ret = i2c_smbus_write_word_data(client, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) cm32181->conf_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * cm32181_read_als_it() - Get sensor integration time (ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * @cm32181: pointer of struct cm32181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * @val2: pointer of int to load the als_it value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * Report the current integration time in milliseconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * Return: IIO_VAL_INT_PLUS_MICRO for success, otherwise -EINVAL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int cm32181_read_als_it(struct cm32181_chip *cm32181, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u16 als_it;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) als_it = cm32181->conf_regs[CM32181_REG_ADDR_CMD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) als_it &= CM32181_CMD_ALS_IT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) als_it >>= CM32181_CMD_ALS_IT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) for (i = 0; i < cm32181->num_als_it; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (als_it == cm32181->als_it_bits[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) *val2 = cm32181->als_it_values[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * cm32181_write_als_it() - Write sensor integration time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * @cm32181: pointer of struct cm32181.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * @val: integration time by millisecond.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * Convert integration time (ms) to sensor value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * Return: i2c_smbus_write_word_data command return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int cm32181_write_als_it(struct cm32181_chip *cm32181, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct i2c_client *client = cm32181->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u16 als_it;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int ret, i, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) n = cm32181->num_als_it;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) for (i = 0; i < n; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (val <= cm32181->als_it_values[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (i >= n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) i = n - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) als_it = cm32181->als_it_bits[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) als_it <<= CM32181_CMD_ALS_IT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) mutex_lock(&cm32181->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) cm32181->conf_regs[CM32181_REG_ADDR_CMD] &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ~CM32181_CMD_ALS_IT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) cm32181->conf_regs[CM32181_REG_ADDR_CMD] |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) als_it;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ret = i2c_smbus_write_word_data(client, CM32181_REG_ADDR_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) cm32181->conf_regs[CM32181_REG_ADDR_CMD]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) mutex_unlock(&cm32181->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * cm32181_get_lux() - report current lux value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * @cm32181: pointer of struct cm32181.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * Convert sensor raw data to lux. It depends on integration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * time and calibscale variable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * Return: Positive value is lux, otherwise is error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int cm32181_get_lux(struct cm32181_chip *cm32181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct i2c_client *client = cm32181->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int als_it;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u64 lux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ret = cm32181_read_als_it(cm32181, &als_it);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) lux = cm32181->lux_per_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) lux *= cm32181->lux_per_bit_base_it;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) lux = div_u64(lux, als_it);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ret = i2c_smbus_read_word_data(client, CM32181_REG_ADDR_ALS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) lux *= ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) lux *= cm32181->calibscale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) lux = div_u64(lux, CM32181_CALIBSCALE_RESOLUTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) lux = div_u64(lux, CM32181_LUX_PER_BIT_RESOLUTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (lux > 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) lux = 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return lux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int cm32181_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct cm32181_chip *cm32181 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) case IIO_CHAN_INFO_PROCESSED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ret = cm32181_get_lux(cm32181);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) *val = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) case IIO_CHAN_INFO_CALIBSCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) *val = cm32181->calibscale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) case IIO_CHAN_INFO_INT_TIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ret = cm32181_read_als_it(cm32181, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int cm32181_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct cm32181_chip *cm32181 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) case IIO_CHAN_INFO_CALIBSCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) cm32181->calibscale = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) case IIO_CHAN_INFO_INT_TIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = cm32181_write_als_it(cm32181, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * cm32181_get_it_available() - Get available ALS IT value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * @dev: pointer of struct device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * @attr: pointer of struct device_attribute.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * @buf: pointer of return string buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * Display the available integration time values by millisecond.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * Return: string length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static ssize_t cm32181_get_it_available(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct cm32181_chip *cm32181 = iio_priv(dev_to_iio_dev(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int i, n, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) n = cm32181->num_als_it;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) for (i = 0, len = 0; i < n; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) len += sprintf(buf + len, "0.%06u ", cm32181->als_it_values[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return len + sprintf(buf + len, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const struct iio_chan_spec cm32181_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .type = IIO_LIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .info_mask_separate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) BIT(IIO_CHAN_INFO_PROCESSED) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) BIT(IIO_CHAN_INFO_CALIBSCALE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) BIT(IIO_CHAN_INFO_INT_TIME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static IIO_DEVICE_ATTR(in_illuminance_integration_time_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) S_IRUGO, cm32181_get_it_available, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static struct attribute *cm32181_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) &iio_dev_attr_in_illuminance_integration_time_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static const struct attribute_group cm32181_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .attrs = cm32181_attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static const struct iio_info cm32181_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .read_raw = &cm32181_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .write_raw = &cm32181_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .attrs = &cm32181_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static int cm32181_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct cm32181_chip *cm32181;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) indio_dev = devm_iio_device_alloc(dev, sizeof(*cm32181));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * Some ACPI systems list 2 I2C resources for the CM3218 sensor, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * SMBus Alert Response Address (ARA, 0x0c) and the actual I2C address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * Detect this and take the following step to deal with it:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * 1. When a SMBus Alert capable sensor has an Alert asserted, it will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * not respond on its actual I2C address. Read a byte from the ARA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * to clear any pending Alerts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * 2. Create a "dummy" client for the actual I2C address and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * use that client to communicate with the sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (ACPI_HANDLE(dev) && client->addr == SMBUS_ALERT_RESPONSE_ADDRESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct i2c_board_info board_info = { .type = "dummy" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) i2c_smbus_read_byte(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) client = i2c_acpi_new_device(dev, 1, &board_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (IS_ERR(client))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return PTR_ERR(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) cm32181 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) cm32181->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) cm32181->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) mutex_init(&cm32181->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) indio_dev->channels = cm32181_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) indio_dev->num_channels = ARRAY_SIZE(cm32181_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) indio_dev->info = &cm32181_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) indio_dev->name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ret = cm32181_reg_init(cm32181);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dev_err(dev, "%s: register init failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ret = devm_iio_device_register(dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dev_err(dev, "%s: regist device failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static const struct of_device_id cm32181_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) { .compatible = "capella,cm3218" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) { .compatible = "capella,cm32181" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) MODULE_DEVICE_TABLE(of, cm32181_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static const struct acpi_device_id cm32181_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) { "CPLM3218", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) MODULE_DEVICE_TABLE(acpi, cm32181_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static struct i2c_driver cm32181_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .name = "cm32181",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .acpi_match_table = ACPI_PTR(cm32181_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .of_match_table = cm32181_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .probe_new = cm32181_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) module_i2c_driver(cm32181_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) MODULE_AUTHOR("Kevin Tsai <ktsai@capellamicro.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) MODULE_DESCRIPTION("CM32181 ambient light sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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