Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * ROHM BH1710/BH1715/BH1721/BH1750/BH1751 ambient light sensor driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) Tomasz Duszynski <tduszyns@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Data sheets:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  http://rohmfs.rohm.com/en/products/databook/datasheet/ic/sensor/light/bh1710fvc-e.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *  http://rohmfs.rohm.com/en/products/databook/datasheet/ic/sensor/light/bh1715fvc-e.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *  http://rohmfs.rohm.com/en/products/databook/datasheet/ic/sensor/light/bh1721fvc-e.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *  http://rohmfs.rohm.com/en/products/databook/datasheet/ic/sensor/light/bh1750fvi-e.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *  http://rohmfs.rohm.com/en/products/databook/datasheet/ic/sensor/light/bh1751fvi-e.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * 7-bit I2C slave addresses:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *  0x23 (ADDR pin low)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *  0x5C (ADDR pin high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define BH1750_POWER_DOWN		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define BH1750_ONE_TIME_H_RES_MODE	0x20 /* auto-mode for BH1721 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define BH1750_CHANGE_INT_TIME_H_BIT	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define BH1750_CHANGE_INT_TIME_L_BIT	0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	BH1710,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	BH1721,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	BH1750,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) struct bh1750_chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) struct bh1750_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	const struct bh1750_chip_info *chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	u16 mtreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) struct bh1750_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	u16 mtreg_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	u16 mtreg_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	u16 mtreg_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	int mtreg_to_usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	int mtreg_to_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	 * For BH1710/BH1721 all possible integration time values won't fit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	 * into one page so displaying is limited to every second one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	 * Note, that user can still write proper values which were not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	 * listed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	int inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	u16 int_time_low_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	u16 int_time_high_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static const struct bh1750_chip_info bh1750_chip_info_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	[BH1710] = { 140, 1022, 300, 400,  250000000, 2, 0x001F, 0x03E0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	[BH1721] = { 140, 1020, 300, 400,  250000000, 2, 0x0010, 0x03E0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	[BH1750] = { 31,  254,  69,  1740, 57500000,  1, 0x001F, 0x00E0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static int bh1750_change_int_time(struct bh1750_data *data, int usec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	u8 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	const struct bh1750_chip_info *chip_info = data->chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	if ((usec % chip_info->mtreg_to_usec) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	val = usec / chip_info->mtreg_to_usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	if (val < chip_info->mtreg_min || val > chip_info->mtreg_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	ret = i2c_smbus_write_byte(data->client, BH1750_POWER_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	regval = (val & chip_info->int_time_high_mask) >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	ret = i2c_smbus_write_byte(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 				   BH1750_CHANGE_INT_TIME_H_BIT | regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	regval = val & chip_info->int_time_low_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	ret = i2c_smbus_write_byte(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 				   BH1750_CHANGE_INT_TIME_L_BIT | regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	data->mtreg = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int bh1750_read(struct bh1750_data *data, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	__be16 result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	const struct bh1750_chip_info *chip_info = data->chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	unsigned long delay = chip_info->mtreg_to_usec * data->mtreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	 * BH1721 will enter continuous mode on receiving this command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	 * Note, that this eliminates need for bh1750_resume().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	ret = i2c_smbus_write_byte(data->client, BH1750_ONE_TIME_H_RES_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	usleep_range(delay + 15000, delay + 40000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	ret = i2c_master_recv(data->client, (char *)&result, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	*val = be16_to_cpu(result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int bh1750_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			   struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			   int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	int ret, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct bh1750_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	const struct bh1750_chip_info *chip_info = data->chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		case IIO_LIGHT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			ret = bh1750_read(data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		tmp = chip_info->mtreg_to_scale / data->mtreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		*val = tmp / 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		*val2 = tmp % 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	case IIO_CHAN_INFO_INT_TIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		*val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		*val2 = chip_info->mtreg_to_usec * data->mtreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int bh1750_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			    struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			    int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	struct bh1750_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	case IIO_CHAN_INFO_INT_TIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		if (val != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		ret = bh1750_change_int_time(data, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static ssize_t bh1750_show_int_time_available(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	size_t len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct bh1750_data *data = iio_priv(dev_to_iio_dev(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	const struct bh1750_chip_info *chip_info = data->chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	for (i = chip_info->mtreg_min; i <= chip_info->mtreg_max; i += chip_info->inc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		len += scnprintf(buf + len, PAGE_SIZE - len, "0.%06d ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 				 chip_info->mtreg_to_usec * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	buf[len - 1] = '\n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static IIO_DEV_ATTR_INT_TIME_AVAIL(bh1750_show_int_time_available);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static struct attribute *bh1750_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	&iio_dev_attr_integration_time_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const struct attribute_group bh1750_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.attrs = bh1750_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const struct iio_info bh1750_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	.attrs = &bh1750_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	.read_raw = bh1750_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	.write_raw = bh1750_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const struct iio_chan_spec bh1750_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		.type = IIO_LIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 				      BIT(IIO_CHAN_INFO_SCALE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 				      BIT(IIO_CHAN_INFO_INT_TIME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int bh1750_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 			const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	int ret, usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	struct bh1750_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 				I2C_FUNC_SMBUS_WRITE_BYTE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	data->chip_info = &bh1750_chip_info_tbl[id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	usec = data->chip_info->mtreg_to_usec * data->chip_info->mtreg_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	ret = bh1750_change_int_time(data, usec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	mutex_init(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	indio_dev->info = &bh1750_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	indio_dev->name = id->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	indio_dev->channels = bh1750_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	indio_dev->num_channels = ARRAY_SIZE(bh1750_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	return iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int bh1750_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	struct iio_dev *indio_dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	struct bh1750_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	i2c_smbus_write_byte(client, BH1750_POWER_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int __maybe_unused bh1750_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	struct bh1750_data *data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		iio_priv(i2c_get_clientdata(to_i2c_client(dev)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	 * This is mainly for BH1721 which doesn't enter power down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	 * mode automatically.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	ret = i2c_smbus_write_byte(data->client, BH1750_POWER_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static SIMPLE_DEV_PM_OPS(bh1750_pm_ops, bh1750_suspend, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const struct i2c_device_id bh1750_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	{ "bh1710", BH1710 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	{ "bh1715", BH1750 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	{ "bh1721", BH1721 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	{ "bh1750", BH1750 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	{ "bh1751", BH1750 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MODULE_DEVICE_TABLE(i2c, bh1750_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static const struct of_device_id bh1750_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	{ .compatible = "rohm,bh1710", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	{ .compatible = "rohm,bh1715", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	{ .compatible = "rohm,bh1721", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	{ .compatible = "rohm,bh1750", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	{ .compatible = "rohm,bh1751", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MODULE_DEVICE_TABLE(of, bh1750_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static struct i2c_driver bh1750_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		.name = "bh1750",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		.of_match_table = bh1750_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		.pm = &bh1750_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	.probe = bh1750_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	.remove = bh1750_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	.id_table = bh1750_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) module_i2c_driver(bh1750_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) MODULE_AUTHOR("Tomasz Duszynski <tduszyns@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) MODULE_DESCRIPTION("ROHM BH1710/BH1715/BH1721/BH1750/BH1751 als driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) MODULE_LICENSE("GPL v2");