Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * apds9300.c - IIO driver for Avago APDS9300 ambient light sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2013 Oleksandr Kravchenko <o.v.kravchenko@globallogic.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/iio/events.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define APDS9300_DRV_NAME "apds9300"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define APDS9300_IRQ_NAME "apds9300_event"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* Command register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define APDS9300_CMD	BIT(7) /* Select command register. Must write as 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define APDS9300_WORD	BIT(5) /* I2C write/read: if 1 word, if 0 byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define APDS9300_CLEAR	BIT(6) /* Interrupt clear. Clears pending interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* Register set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define APDS9300_CONTROL	0x00 /* Control of basic functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define APDS9300_THRESHLOWLOW	0x02 /* Low byte of low interrupt threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define APDS9300_THRESHHIGHLOW	0x04 /* Low byte of high interrupt threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define APDS9300_INTERRUPT	0x06 /* Interrupt control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define APDS9300_DATA0LOW	0x0c /* Low byte of ADC channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define APDS9300_DATA1LOW	0x0e /* Low byte of ADC channel 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* Power on/off value for APDS9300_CONTROL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define APDS9300_POWER_ON	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define APDS9300_POWER_OFF	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /* Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define APDS9300_INTR_ENABLE	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /* Interrupt Persist Function: Any value outside of threshold range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define APDS9300_THRESH_INTR	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define APDS9300_THRESH_MAX	0xffff /* Max threshold value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) struct apds9300_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	int power_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	int thresh_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	int thresh_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	int intr_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /* Lux calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) /* Calculated values 1000 * (CH1/CH0)^1.4 for CH1/CH0 from 0 to 0.52 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static const u16 apds9300_lux_ratio[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	0, 2, 4, 7, 11, 15, 19, 24, 29, 34, 40, 45, 51, 57, 64, 70, 77, 84, 91,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	98, 105, 112, 120, 128, 136, 144, 152, 160, 168, 177, 185, 194, 203,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	212, 221, 230, 239, 249, 258, 268, 277, 287, 297, 307, 317, 327, 337,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	347, 358, 368, 379, 390, 400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static unsigned long apds9300_calculate_lux(u16 ch0, u16 ch1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	unsigned long lux, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	/* avoid division by zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	if (ch0 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	tmp = DIV_ROUND_UP(ch1 * 100, ch0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	if (tmp <= 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		lux = 3150 * ch0 - (unsigned long)DIV_ROUND_UP_ULL(ch0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 				* apds9300_lux_ratio[tmp] * 5930ull, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	} else if (tmp <= 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		lux = 2290 * ch0 - 2910 * ch1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	} else if (tmp <= 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		lux = 1570 * ch0 - 1800 * ch1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	} else if (tmp <= 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		lux = 338 * ch0 - 260 * ch1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		lux = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	return lux / 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static int apds9300_get_adc_val(struct apds9300_data *data, int adc_number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	u8 flags = APDS9300_CMD | APDS9300_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	if (!data->power_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	/* Select ADC0 or ADC1 data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	flags |= adc_number ? APDS9300_DATA1LOW : APDS9300_DATA0LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	ret = i2c_smbus_read_word_data(data->client, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		dev_err(&data->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			"failed to read ADC%d value\n", adc_number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int apds9300_set_thresh_low(struct apds9300_data *data, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	if (!data->power_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (value > APDS9300_THRESH_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	ret = i2c_smbus_write_word_data(data->client, APDS9300_THRESHLOWLOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			| APDS9300_CMD | APDS9300_WORD, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		dev_err(&data->client->dev, "failed to set thresh_low\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	data->thresh_low = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int apds9300_set_thresh_hi(struct apds9300_data *data, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	if (!data->power_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (value > APDS9300_THRESH_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	ret = i2c_smbus_write_word_data(data->client, APDS9300_THRESHHIGHLOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			| APDS9300_CMD | APDS9300_WORD, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		dev_err(&data->client->dev, "failed to set thresh_hi\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	data->thresh_hi = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int apds9300_set_intr_state(struct apds9300_data *data, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	u8 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (!data->power_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	cmd = state ? APDS9300_INTR_ENABLE | APDS9300_THRESH_INTR : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	ret = i2c_smbus_write_byte_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			APDS9300_INTERRUPT | APDS9300_CMD, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		dev_err(&data->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			"failed to set interrupt state %d\n", state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	data->intr_en = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int apds9300_set_power_state(struct apds9300_data *data, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	u8 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	cmd = state ? APDS9300_POWER_ON : APDS9300_POWER_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	ret = i2c_smbus_write_byte_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			APDS9300_CONTROL | APDS9300_CMD, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		dev_err(&data->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			"failed to set power state %d\n", state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	data->power_state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static void apds9300_clear_intr(struct apds9300_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	ret = i2c_smbus_write_byte(data->client, APDS9300_CLEAR | APDS9300_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		dev_err(&data->client->dev, "failed to clear interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int apds9300_chip_init(struct apds9300_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	/* Need to set power off to ensure that the chip is off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	ret = apds9300_set_power_state(data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	 * Probe the chip. To do so we try to power up the device and then to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	 * read back the 0x03 code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	ret = apds9300_set_power_state(data, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	ret = i2c_smbus_read_byte_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			APDS9300_CONTROL | APDS9300_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	if (ret != APDS9300_POWER_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	 * Disable interrupt to ensure thai it is doesn't enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	 * i.e. after device soft reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	ret = apds9300_set_intr_state(data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	dev_err(&data->client->dev, "failed to init the chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int apds9300_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		struct iio_chan_spec const *chan, int *val, int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	int ch0, ch1, ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	struct apds9300_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	case IIO_LIGHT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		ch0 = apds9300_get_adc_val(data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		if (ch0 < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			ret = ch0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		ch1 = apds9300_get_adc_val(data, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		if (ch1 < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			ret = ch1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		*val = apds9300_calculate_lux(ch0, ch1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	case IIO_INTENSITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		ret = apds9300_get_adc_val(data, chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		*val = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int apds9300_read_thresh(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		enum iio_event_direction dir, enum iio_event_info info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		int *val, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	struct apds9300_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	switch (dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	case IIO_EV_DIR_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		*val = data->thresh_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	case IIO_EV_DIR_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		*val = data->thresh_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int apds9300_write_thresh(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		enum iio_event_direction dir, enum iio_event_info info, int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		int val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	struct apds9300_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	if (dir == IIO_EV_DIR_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		ret = apds9300_set_thresh_hi(data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		ret = apds9300_set_thresh_low(data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static int apds9300_read_interrupt_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		enum iio_event_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	struct apds9300_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	return data->intr_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int apds9300_write_interrupt_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		const struct iio_chan_spec *chan, enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		enum iio_event_direction dir, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	struct apds9300_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	ret = apds9300_set_intr_state(data, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const struct iio_info apds9300_info_no_irq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	.read_raw	= apds9300_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const struct iio_info apds9300_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	.read_raw		= apds9300_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	.read_event_value	= apds9300_read_thresh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	.write_event_value	= apds9300_write_thresh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	.read_event_config	= apds9300_read_interrupt_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	.write_event_config	= apds9300_write_interrupt_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const struct iio_event_spec apds9300_event_spec[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		.type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		.dir = IIO_EV_DIR_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		.mask_separate = BIT(IIO_EV_INFO_VALUE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 			BIT(IIO_EV_INFO_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		.type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		.dir = IIO_EV_DIR_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		.mask_separate = BIT(IIO_EV_INFO_VALUE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 			BIT(IIO_EV_INFO_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static const struct iio_chan_spec apds9300_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		.type = IIO_LIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		.channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		.indexed = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		.type = IIO_INTENSITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		.channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		.channel2 = IIO_MOD_LIGHT_BOTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		.indexed = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		.event_spec = apds9300_event_spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		.num_event_specs = ARRAY_SIZE(apds9300_event_spec),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		.type = IIO_INTENSITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		.channel = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		.channel2 = IIO_MOD_LIGHT_IR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		.indexed = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static irqreturn_t apds9300_interrupt_handler(int irq, void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	struct iio_dev *dev_info = private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	struct apds9300_data *data = iio_priv(dev_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	iio_push_event(dev_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		       IIO_UNMOD_EVENT_CODE(IIO_INTENSITY, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 					    IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 					    IIO_EV_DIR_EITHER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		       iio_get_time_ns(dev_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	apds9300_clear_intr(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int apds9300_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	struct apds9300_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	ret = apds9300_chip_init(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	mutex_init(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	indio_dev->channels = apds9300_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	indio_dev->num_channels = ARRAY_SIZE(apds9300_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	indio_dev->name = APDS9300_DRV_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	if (client->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		indio_dev->info = &apds9300_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		indio_dev->info = &apds9300_info_no_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	if (client->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		ret = devm_request_threaded_irq(&client->dev, client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 				NULL, apds9300_interrupt_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 				IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 				APDS9300_IRQ_NAME, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 			dev_err(&client->dev, "irq request error %d\n", -ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	/* Ensure that power off in case of error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	apds9300_set_power_state(data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static int apds9300_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	struct iio_dev *indio_dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	struct apds9300_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	/* Ensure that power off and interrupts are disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	apds9300_set_intr_state(data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	apds9300_set_power_state(data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static int apds9300_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	struct apds9300_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	ret = apds9300_set_power_state(data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static int apds9300_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	struct apds9300_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	ret = apds9300_set_power_state(data, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static SIMPLE_DEV_PM_OPS(apds9300_pm_ops, apds9300_suspend, apds9300_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define APDS9300_PM_OPS (&apds9300_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define APDS9300_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static const struct i2c_device_id apds9300_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	{ APDS9300_DRV_NAME, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) MODULE_DEVICE_TABLE(i2c, apds9300_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static struct i2c_driver apds9300_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 		.name	= APDS9300_DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 		.pm	= APDS9300_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	.probe		= apds9300_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	.remove		= apds9300_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	.id_table	= apds9300_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) module_i2c_driver(apds9300_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) MODULE_AUTHOR("Kravchenko Oleksandr <o.v.kravchenko@globallogic.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) MODULE_AUTHOR("GlobalLogic inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) MODULE_DESCRIPTION("APDS9300 ambient light photo sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) MODULE_LICENSE("GPL");