Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * adux1020.c - Support for Analog Devices ADUX1020 photometric sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2019 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * TODO: Triggered buffer support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/iio/events.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define ADUX1020_REGMAP_NAME		"adux1020_regmap"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define ADUX1020_DRV_NAME		"adux1020"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /* System registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define ADUX1020_REG_CHIP_ID		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define ADUX1020_REG_SLAVE_ADDRESS	0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define ADUX1020_REG_SW_RESET		0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define ADUX1020_REG_INT_ENABLE		0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define ADUX1020_REG_INT_POLARITY	0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define ADUX1020_REG_PROX_TH_ON1	0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define ADUX1020_REG_PROX_TH_OFF1	0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define	ADUX1020_REG_PROX_TYPE		0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define	ADUX1020_REG_TEST_MODES_3	0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define	ADUX1020_REG_FORCE_MODE		0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define	ADUX1020_REG_FREQUENCY		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define ADUX1020_REG_LED_CURRENT	0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define	ADUX1020_REG_OP_MODE		0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define	ADUX1020_REG_INT_MASK		0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define	ADUX1020_REG_INT_STATUS		0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define	ADUX1020_REG_DATA_BUFFER	0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /* Chip ID bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define ADUX1020_CHIP_ID_MASK		GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define ADUX1020_CHIP_ID		0x03fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define ADUX1020_SW_RESET		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define ADUX1020_FIFO_FLUSH		BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define ADUX1020_OP_MODE_MASK		GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define ADUX1020_DATA_OUT_MODE_MASK	GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define ADUX1020_DATA_OUT_PROX_I	FIELD_PREP(ADUX1020_DATA_OUT_MODE_MASK, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define ADUX1020_MODE_INT_MASK		GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define ADUX1020_INT_ENABLE		0x2094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define ADUX1020_INT_DISABLE		0x2090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define ADUX1020_PROX_INT_ENABLE	0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define ADUX1020_PROX_ON1_INT		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define ADUX1020_PROX_OFF1_INT		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define ADUX1020_FIFO_INT_ENABLE	0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define ADUX1020_MODE_INT_DISABLE	0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define ADUX1020_MODE_INT_STATUS_MASK	GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define ADUX1020_FIFO_STATUS_MASK	GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define ADUX1020_INT_CLEAR		0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define ADUX1020_PROX_TYPE		BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define ADUX1020_INT_PROX_ON1		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define ADUX1020_INT_PROX_OFF1		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define ADUX1020_FORCE_CLOCK_ON		0x0f4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define ADUX1020_FORCE_CLOCK_RESET	0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define ADUX1020_ACTIVE_4_STATE		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define ADUX1020_PROX_FREQ_MASK		GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define ADUX1020_PROX_FREQ(x)		FIELD_PREP(ADUX1020_PROX_FREQ_MASK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define ADUX1020_LED_CURRENT_MASK	GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define ADUX1020_LED_PIREF_EN		BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) /* Operating modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) enum adux1020_op_modes {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	ADUX1020_MODE_STANDBY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	ADUX1020_MODE_PROX_I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	ADUX1020_MODE_PROX_XY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	ADUX1020_MODE_GEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	ADUX1020_MODE_SAMPLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	ADUX1020_MODE_FORCE = 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	ADUX1020_MODE_IDLE = 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) struct adux1020_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct adux1020_mode_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	u8 bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	u8 buf_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	u16 int_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static const struct adux1020_mode_data adux1020_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	[ADUX1020_MODE_PROX_I] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		.bytes = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		.buf_len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		.int_en = ADUX1020_PROX_INT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const struct regmap_config adux1020_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.name = ADUX1020_REGMAP_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	.val_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	.max_register = 0x6F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	.cache_type = REGCACHE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const struct reg_sequence adux1020_def_conf[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	{ 0x000c, 0x000f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	{ 0x0010, 0x1010 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	{ 0x0011, 0x004c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	{ 0x0012, 0x5f0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	{ 0x0013, 0xada5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	{ 0x0014, 0x0080 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	{ 0x0015, 0x0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	{ 0x0016, 0x0600 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	{ 0x0017, 0x0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	{ 0x0018, 0x2693 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	{ 0x0019, 0x0004 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	{ 0x001a, 0x4280 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	{ 0x001b, 0x0060 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	{ 0x001c, 0x2094 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	{ 0x001d, 0x0020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	{ 0x001e, 0x0001 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	{ 0x001f, 0x0100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	{ 0x0020, 0x0320 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	{ 0x0021, 0x0A13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	{ 0x0022, 0x0320 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	{ 0x0023, 0x0113 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	{ 0x0024, 0x0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	{ 0x0025, 0x2412 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	{ 0x0026, 0x2412 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	{ 0x0027, 0x0022 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	{ 0x0028, 0x0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	{ 0x0029, 0x0300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	{ 0x002a, 0x0700 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	{ 0x002b, 0x0600 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	{ 0x002c, 0x6000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	{ 0x002d, 0x4000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	{ 0x002e, 0x0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	{ 0x002f, 0x0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	{ 0x0030, 0x0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	{ 0x0031, 0x0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	{ 0x0032, 0x0040 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	{ 0x0033, 0x0008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	{ 0x0034, 0xE400 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	{ 0x0038, 0x8080 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	{ 0x0039, 0x8080 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	{ 0x003a, 0x2000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	{ 0x003b, 0x1f00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	{ 0x003c, 0x2000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	{ 0x003d, 0x2000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	{ 0x003e, 0x0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	{ 0x0040, 0x8069 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	{ 0x0041, 0x1f2f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	{ 0x0042, 0x4000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	{ 0x0043, 0x0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	{ 0x0044, 0x0008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	{ 0x0046, 0x0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	{ 0x0048, 0x00ef },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	{ 0x0049, 0x0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	{ 0x0045, 0x0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static const int adux1020_rates[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	{ 0, 100000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	{ 0, 200000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	{ 0, 500000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	{ 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	{ 2, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	{ 5, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	{ 10, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	{ 20, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	{ 50, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	{ 100, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	{ 190, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	{ 450, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	{ 820, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	{ 1400, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const int adux1020_led_currents[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	{ 0, 25000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	{ 0, 40000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	{ 0, 55000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	{ 0, 70000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	{ 0, 85000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	{ 0, 100000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	{ 0, 115000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	{ 0, 130000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	{ 0, 145000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	{ 0, 160000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	{ 0, 175000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	{ 0, 190000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	{ 0, 205000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	{ 0, 220000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	{ 0, 235000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	{ 0, 250000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int adux1020_flush_fifo(struct adux1020_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	/* Force Idle mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	ret = regmap_write(data->regmap, ADUX1020_REG_FORCE_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			   ADUX1020_ACTIVE_4_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	ret = regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 				 ADUX1020_OP_MODE_MASK, ADUX1020_MODE_FORCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	ret = regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 				 ADUX1020_OP_MODE_MASK, ADUX1020_MODE_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	/* Flush FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	ret = regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			   ADUX1020_FORCE_CLOCK_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	ret = regmap_write(data->regmap, ADUX1020_REG_INT_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			   ADUX1020_FIFO_FLUSH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	return regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			    ADUX1020_FORCE_CLOCK_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int adux1020_read_fifo(struct adux1020_data *data, u16 *buf, u8 buf_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	/* Enable 32MHz clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	ret = regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			   ADUX1020_FORCE_CLOCK_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	for (i = 0; i < buf_len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		ret = regmap_read(data->regmap, ADUX1020_REG_DATA_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 				  &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		buf[i] = regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	/* Set 32MHz clock to be controlled by internal state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	return regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			    ADUX1020_FORCE_CLOCK_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int adux1020_set_mode(struct adux1020_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			     enum adux1020_op_modes mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	/* Switch to standby mode before changing the mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	ret = regmap_write(data->regmap, ADUX1020_REG_OP_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 			   ADUX1020_MODE_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	/* Set data out and switch to the desired mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	case ADUX1020_MODE_PROX_I:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		ret = regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 					 ADUX1020_DATA_OUT_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 					 ADUX1020_DATA_OUT_PROX_I);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		ret = regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 					 ADUX1020_OP_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 					 ADUX1020_MODE_PROX_I);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int adux1020_measure(struct adux1020_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			    enum adux1020_op_modes mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			    u16 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	int ret, tries = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	/* Disable INT pin as polling is going to be used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	ret = regmap_write(data->regmap, ADUX1020_REG_INT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			   ADUX1020_INT_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	/* Enable mode interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	ret = regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 				 ADUX1020_MODE_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 				 adux1020_modes[mode].int_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	while (tries--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		ret = regmap_read(data->regmap, ADUX1020_REG_INT_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 				  &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		status &= ADUX1020_FIFO_STATUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		if (status >= adux1020_modes[mode].bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	if (tries < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	ret = adux1020_read_fifo(data, val, adux1020_modes[mode].buf_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	/* Clear mode interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	ret = regmap_write(data->regmap, ADUX1020_REG_INT_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 			   (~adux1020_modes[mode].int_en));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	/* Disable mode interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	return regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 				  ADUX1020_MODE_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 				  ADUX1020_MODE_INT_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int adux1020_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 			     struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 			     int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	struct adux1020_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	u16 buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		case IIO_PROXIMITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 			ret = adux1020_set_mode(data, ADUX1020_MODE_PROX_I);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 			if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 				goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 			ret = adux1020_measure(data, ADUX1020_MODE_PROX_I, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 			if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 				goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 			*val = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 			ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	case IIO_CHAN_INFO_PROCESSED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		case IIO_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 			ret = regmap_read(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 					  ADUX1020_REG_LED_CURRENT, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 			if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 				goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 			regval = regval & ADUX1020_LED_CURRENT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 			*val = adux1020_led_currents[regval][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 			*val2 = adux1020_led_currents[regval][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 			ret = IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		case IIO_PROXIMITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 			ret = regmap_read(data->regmap, ADUX1020_REG_FREQUENCY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 					  &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 			if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 				goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 			regval = FIELD_GET(ADUX1020_PROX_FREQ_MASK, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 			*val = adux1020_rates[regval][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 			*val2 = adux1020_rates[regval][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 			ret = IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static inline int adux1020_find_index(const int array[][2], int count, int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 				      int val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	for (i = 0; i < count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		if (val == array[i][0] && val2 == array[i][1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 			return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static int adux1020_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 			      struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 			      int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	struct adux1020_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	int i, ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		if (chan->type == IIO_PROXIMITY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 			i = adux1020_find_index(adux1020_rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 						ARRAY_SIZE(adux1020_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 						val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 			if (i < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 				ret = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 				goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 			ret = regmap_update_bits(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 						 ADUX1020_REG_FREQUENCY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 						 ADUX1020_PROX_FREQ_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 						 ADUX1020_PROX_FREQ(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	case IIO_CHAN_INFO_PROCESSED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 		if (chan->type == IIO_CURRENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 			i = adux1020_find_index(adux1020_led_currents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 					ARRAY_SIZE(adux1020_led_currents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 					val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 			if (i < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 				ret = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 				goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 			ret = regmap_update_bits(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 						 ADUX1020_REG_LED_CURRENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 						 ADUX1020_LED_CURRENT_MASK, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static int adux1020_write_event_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 				       const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 				       enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 				       enum iio_event_direction dir, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	struct adux1020_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	int ret, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	ret = regmap_write(data->regmap, ADUX1020_REG_INT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 			   ADUX1020_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 		goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	ret = regmap_write(data->regmap, ADUX1020_REG_INT_POLARITY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 		goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	case IIO_PROXIMITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 		if (dir == IIO_EV_DIR_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 			mask = ADUX1020_PROX_ON1_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 			mask = ADUX1020_PROX_OFF1_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 		if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 			state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 			state = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 		ret = regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 					 mask, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 			goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 		 * Trigger proximity interrupt when the intensity is above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 		 * or below threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 		ret = regmap_update_bits(data->regmap, ADUX1020_REG_PROX_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 					 ADUX1020_PROX_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 					 ADUX1020_PROX_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 			goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 		/* Set proximity mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 		ret = adux1020_set_mode(data, ADUX1020_MODE_PROX_I);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 	mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static int adux1020_read_event_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 				      const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 				      enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 				      enum iio_event_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 	struct adux1020_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 	int ret, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 	unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 	switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 	case IIO_PROXIMITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 		if (dir == IIO_EV_DIR_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 			mask = ADUX1020_PROX_ON1_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 			mask = ADUX1020_PROX_OFF1_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 	ret = regmap_read(data->regmap, ADUX1020_REG_INT_MASK, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	return !(regval & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static int adux1020_read_thresh(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 				const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 				enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 				enum iio_event_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 				enum iio_event_info info, int *val, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 	struct adux1020_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 	u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 	unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 	switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 	case IIO_PROXIMITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 		if (dir == IIO_EV_DIR_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 			reg = ADUX1020_REG_PROX_TH_ON1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 			reg = ADUX1020_REG_PROX_TH_OFF1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 	ret = regmap_read(data->regmap, reg, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 	*val = regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 	return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static int adux1020_write_thresh(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 				 const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 				 enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 				 enum iio_event_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 				 enum iio_event_info info, int val, int val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 	struct adux1020_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 	u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 	switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 	case IIO_PROXIMITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 		if (dir == IIO_EV_DIR_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 			reg = ADUX1020_REG_PROX_TH_ON1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 			reg = ADUX1020_REG_PROX_TH_OFF1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 	/* Full scale threshold value is 0-65535  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 	if (val < 0 || val > 65535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 	return regmap_write(data->regmap, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static const struct iio_event_spec adux1020_proximity_event[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 		.type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 		.dir = IIO_EV_DIR_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 		.mask_separate = BIT(IIO_EV_INFO_VALUE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 			BIT(IIO_EV_INFO_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 		.type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 		.dir = IIO_EV_DIR_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 		.mask_separate = BIT(IIO_EV_INFO_VALUE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 			BIT(IIO_EV_INFO_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static const struct iio_chan_spec adux1020_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 		.type = IIO_PROXIMITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 				      BIT(IIO_CHAN_INFO_SAMP_FREQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) 		.event_spec = adux1020_proximity_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 		.num_event_specs = ARRAY_SIZE(adux1020_proximity_event),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 		.type = IIO_CURRENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 		.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) 		.extend_name = "led",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) 		.output = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 		      "0.1 0.2 0.5 1 2 5 10 20 50 100 190 450 820 1400");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static struct attribute *adux1020_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) 	&iio_const_attr_sampling_frequency_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) 	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static const struct attribute_group adux1020_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 	.attrs = adux1020_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static const struct iio_info adux1020_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) 	.attrs = &adux1020_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) 	.read_raw = adux1020_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) 	.write_raw = adux1020_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) 	.read_event_config = adux1020_read_event_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) 	.write_event_config = adux1020_write_event_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) 	.read_event_value = adux1020_read_thresh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 	.write_event_value = adux1020_write_thresh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static irqreturn_t adux1020_interrupt_handler(int irq, void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) 	struct iio_dev *indio_dev = private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 	struct adux1020_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) 	int ret, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 	ret = regmap_read(data->regmap, ADUX1020_REG_INT_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) 		return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) 	status &= ADUX1020_MODE_INT_STATUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) 	if (status & ADUX1020_INT_PROX_ON1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) 		iio_push_event(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) 			       IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) 						    IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) 						    IIO_EV_DIR_RISING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) 			       iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) 	if (status & ADUX1020_INT_PROX_OFF1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) 		iio_push_event(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) 			       IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) 						    IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) 						    IIO_EV_DIR_FALLING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 			       iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) 	regmap_update_bits(data->regmap, ADUX1020_REG_INT_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) 			   ADUX1020_MODE_INT_MASK, ADUX1020_INT_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static int adux1020_chip_init(struct adux1020_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) 	struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) 	ret = regmap_read(data->regmap, ADUX1020_REG_CHIP_ID, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) 	if ((val & ADUX1020_CHIP_ID_MASK) != ADUX1020_CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) 		dev_err(&client->dev, "invalid chip id 0x%04x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) 	dev_dbg(&client->dev, "Detected ADUX1020 with chip id: 0x%04x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) 	ret = regmap_update_bits(data->regmap, ADUX1020_REG_SW_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) 				 ADUX1020_SW_RESET, ADUX1020_SW_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) 	/* Load default configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) 	ret = regmap_multi_reg_write(data->regmap, adux1020_def_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) 				     ARRAY_SIZE(adux1020_def_conf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) 	ret = adux1020_flush_fifo(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) 	/* Use LED_IREF for proximity mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) 	ret = regmap_update_bits(data->regmap, ADUX1020_REG_LED_CURRENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) 				 ADUX1020_LED_PIREF_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) 	/* Mask all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) 	return regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) 			   ADUX1020_MODE_INT_MASK, ADUX1020_MODE_INT_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static int adux1020_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) 			  const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) 	struct adux1020_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) 	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) 	indio_dev->info = &adux1020_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) 	indio_dev->name = ADUX1020_DRV_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) 	indio_dev->channels = adux1020_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) 	indio_dev->num_channels = ARRAY_SIZE(adux1020_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) 	data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) 	data->regmap = devm_regmap_init_i2c(client, &adux1020_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) 	if (IS_ERR(data->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) 		dev_err(&client->dev, "regmap initialization failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) 		return PTR_ERR(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) 	data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) 	data->indio_dev = indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) 	mutex_init(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) 	ret = adux1020_chip_init(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) 	if (client->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) 		ret = devm_request_threaded_irq(&client->dev, client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) 					NULL, adux1020_interrupt_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) 					IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) 					ADUX1020_DRV_NAME, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) 			dev_err(&client->dev, "irq request error %d\n", -ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) 	return devm_iio_device_register(&client->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static const struct i2c_device_id adux1020_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) 	{ "adux1020", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) MODULE_DEVICE_TABLE(i2c, adux1020_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static const struct of_device_id adux1020_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) 	{ .compatible = "adi,adux1020" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) MODULE_DEVICE_TABLE(of, adux1020_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static struct i2c_driver adux1020_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) 		.name	= ADUX1020_DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) 		.of_match_table = adux1020_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) 	.probe		= adux1020_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) 	.id_table	= adux1020_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) module_i2c_driver(adux1020_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) MODULE_DESCRIPTION("ADUX1020 photometric sensor");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) MODULE_LICENSE("GPL");