^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ADIS16480 and similar IMUs driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2012 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/iio/imu/adis.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ADIS16480_PAGE_SIZE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ADIS16480_REG(page, reg) ((page) * ADIS16480_PAGE_SIZE + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ADIS16480_REG_PAGE_ID 0x00 /* Same address on each page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ADIS16480_REG_SEQ_CNT ADIS16480_REG(0x00, 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ADIS16480_REG_SYS_E_FLA ADIS16480_REG(0x00, 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ADIS16480_REG_DIAG_STS ADIS16480_REG(0x00, 0x0A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ADIS16480_REG_ALM_STS ADIS16480_REG(0x00, 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ADIS16480_REG_TEMP_OUT ADIS16480_REG(0x00, 0x0E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ADIS16480_REG_X_GYRO_OUT ADIS16480_REG(0x00, 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ADIS16480_REG_Y_GYRO_OUT ADIS16480_REG(0x00, 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ADIS16480_REG_Z_GYRO_OUT ADIS16480_REG(0x00, 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ADIS16480_REG_X_ACCEL_OUT ADIS16480_REG(0x00, 0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ADIS16480_REG_Y_ACCEL_OUT ADIS16480_REG(0x00, 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ADIS16480_REG_Z_ACCEL_OUT ADIS16480_REG(0x00, 0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ADIS16480_REG_X_MAGN_OUT ADIS16480_REG(0x00, 0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ADIS16480_REG_Y_MAGN_OUT ADIS16480_REG(0x00, 0x2A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ADIS16480_REG_Z_MAGN_OUT ADIS16480_REG(0x00, 0x2C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ADIS16480_REG_BAROM_OUT ADIS16480_REG(0x00, 0x2E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ADIS16480_REG_X_DELTAANG_OUT ADIS16480_REG(0x00, 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ADIS16480_REG_Y_DELTAANG_OUT ADIS16480_REG(0x00, 0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ADIS16480_REG_Z_DELTAANG_OUT ADIS16480_REG(0x00, 0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ADIS16480_REG_X_DELTAVEL_OUT ADIS16480_REG(0x00, 0x4C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ADIS16480_REG_Y_DELTAVEL_OUT ADIS16480_REG(0x00, 0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ADIS16480_REG_Z_DELTAVEL_OUT ADIS16480_REG(0x00, 0x54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ADIS16480_REG_PROD_ID ADIS16480_REG(0x00, 0x7E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ADIS16480_REG_X_GYRO_SCALE ADIS16480_REG(0x02, 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ADIS16480_REG_Y_GYRO_SCALE ADIS16480_REG(0x02, 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ADIS16480_REG_Z_GYRO_SCALE ADIS16480_REG(0x02, 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ADIS16480_REG_X_ACCEL_SCALE ADIS16480_REG(0x02, 0x0A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ADIS16480_REG_Y_ACCEL_SCALE ADIS16480_REG(0x02, 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ADIS16480_REG_Z_ACCEL_SCALE ADIS16480_REG(0x02, 0x0E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ADIS16480_REG_X_GYRO_BIAS ADIS16480_REG(0x02, 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ADIS16480_REG_Y_GYRO_BIAS ADIS16480_REG(0x02, 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ADIS16480_REG_Z_GYRO_BIAS ADIS16480_REG(0x02, 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ADIS16480_REG_X_ACCEL_BIAS ADIS16480_REG(0x02, 0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ADIS16480_REG_Y_ACCEL_BIAS ADIS16480_REG(0x02, 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ADIS16480_REG_Z_ACCEL_BIAS ADIS16480_REG(0x02, 0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ADIS16480_REG_X_HARD_IRON ADIS16480_REG(0x02, 0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ADIS16480_REG_Y_HARD_IRON ADIS16480_REG(0x02, 0x2A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ADIS16480_REG_Z_HARD_IRON ADIS16480_REG(0x02, 0x2C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ADIS16480_REG_BAROM_BIAS ADIS16480_REG(0x02, 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ADIS16480_REG_FLASH_CNT ADIS16480_REG(0x02, 0x7C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ADIS16480_REG_GLOB_CMD ADIS16480_REG(0x03, 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ADIS16480_REG_FNCTIO_CTRL ADIS16480_REG(0x03, 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ADIS16480_REG_GPIO_CTRL ADIS16480_REG(0x03, 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ADIS16480_REG_CONFIG ADIS16480_REG(0x03, 0x0A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ADIS16480_REG_DEC_RATE ADIS16480_REG(0x03, 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ADIS16480_REG_SLP_CNT ADIS16480_REG(0x03, 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ADIS16480_REG_FILTER_BNK0 ADIS16480_REG(0x03, 0x16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ADIS16480_REG_FILTER_BNK1 ADIS16480_REG(0x03, 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ADIS16480_REG_ALM_CNFG0 ADIS16480_REG(0x03, 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ADIS16480_REG_ALM_CNFG1 ADIS16480_REG(0x03, 0x22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ADIS16480_REG_ALM_CNFG2 ADIS16480_REG(0x03, 0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ADIS16480_REG_XG_ALM_MAGN ADIS16480_REG(0x03, 0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ADIS16480_REG_YG_ALM_MAGN ADIS16480_REG(0x03, 0x2A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ADIS16480_REG_ZG_ALM_MAGN ADIS16480_REG(0x03, 0x2C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ADIS16480_REG_XA_ALM_MAGN ADIS16480_REG(0x03, 0x2E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ADIS16480_REG_YA_ALM_MAGN ADIS16480_REG(0x03, 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ADIS16480_REG_ZA_ALM_MAGN ADIS16480_REG(0x03, 0x32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ADIS16480_REG_XM_ALM_MAGN ADIS16480_REG(0x03, 0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ADIS16480_REG_YM_ALM_MAGN ADIS16480_REG(0x03, 0x36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ADIS16480_REG_ZM_ALM_MAGN ADIS16480_REG(0x03, 0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ADIS16480_REG_BR_ALM_MAGN ADIS16480_REG(0x03, 0x3A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ADIS16480_REG_FIRM_REV ADIS16480_REG(0x03, 0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ADIS16480_REG_FIRM_DM ADIS16480_REG(0x03, 0x7A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ADIS16480_REG_FIRM_Y ADIS16480_REG(0x03, 0x7C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * External clock scaling in PPS mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * Available only for ADIS1649x devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ADIS16495_REG_SYNC_SCALE ADIS16480_REG(0x03, 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ADIS16480_REG_SERIAL_NUM ADIS16480_REG(0x04, 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Each filter coefficent bank spans two pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ADIS16480_FIR_COEF(page) (x < 60 ? ADIS16480_REG(page, (x) + 8) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ADIS16480_REG((page) + 1, (x) - 60 + 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ADIS16480_FIR_COEF_A(x) ADIS16480_FIR_COEF(0x05, (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ADIS16480_FIR_COEF_B(x) ADIS16480_FIR_COEF(0x07, (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ADIS16480_FIR_COEF_C(x) ADIS16480_FIR_COEF(0x09, (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ADIS16480_FIR_COEF_D(x) ADIS16480_FIR_COEF(0x0B, (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* ADIS16480_REG_FNCTIO_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ADIS16480_DRDY_SEL_MSK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ADIS16480_DRDY_SEL(x) FIELD_PREP(ADIS16480_DRDY_SEL_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ADIS16480_DRDY_POL_MSK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ADIS16480_DRDY_POL(x) FIELD_PREP(ADIS16480_DRDY_POL_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ADIS16480_DRDY_EN_MSK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ADIS16480_DRDY_EN(x) FIELD_PREP(ADIS16480_DRDY_EN_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ADIS16480_SYNC_SEL_MSK GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ADIS16480_SYNC_SEL(x) FIELD_PREP(ADIS16480_SYNC_SEL_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define ADIS16480_SYNC_EN_MSK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ADIS16480_SYNC_EN(x) FIELD_PREP(ADIS16480_SYNC_EN_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ADIS16480_SYNC_MODE_MSK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ADIS16480_SYNC_MODE(x) FIELD_PREP(ADIS16480_SYNC_MODE_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct adis16480_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) const struct iio_chan_spec *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int gyro_max_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned int gyro_max_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned int accel_max_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int accel_max_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned int temp_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned int int_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned int max_dec_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) const unsigned int *filter_freqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) bool has_pps_clk_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) const struct adis_data adis_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) enum adis16480_int_pin {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ADIS16480_PIN_DIO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ADIS16480_PIN_DIO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ADIS16480_PIN_DIO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ADIS16480_PIN_DIO4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) enum adis16480_clock_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ADIS16480_CLK_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ADIS16480_CLK_PPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ADIS16480_CLK_INT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct adis16480 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) const struct adis16480_chip_info *chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct adis adis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct clk *ext_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) enum adis16480_clock_mode clk_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned int clk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const char * const adis16480_int_pin_names[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) [ADIS16480_PIN_DIO1] = "DIO1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) [ADIS16480_PIN_DIO2] = "DIO2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) [ADIS16480_PIN_DIO3] = "DIO3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) [ADIS16480_PIN_DIO4] = "DIO4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static ssize_t adis16480_show_firmware_revision(struct file *file,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) char __user *userbuf, size_t count, loff_t *ppos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct adis16480 *adis16480 = file->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) char buf[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u16 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_REV, &rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return simple_read_from_buffer(userbuf, count, ppos, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static const struct file_operations adis16480_firmware_revision_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .open = simple_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .read = adis16480_show_firmware_revision,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .llseek = default_llseek,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static ssize_t adis16480_show_firmware_date(struct file *file,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) char __user *userbuf, size_t count, loff_t *ppos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct adis16480 *adis16480 = file->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u16 md, year;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) char buf[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_Y, &year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_DM, &md);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) md >> 8, md & 0xff, year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return simple_read_from_buffer(userbuf, count, ppos, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const struct file_operations adis16480_firmware_date_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .open = simple_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .read = adis16480_show_firmware_date,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .llseek = default_llseek,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int adis16480_show_serial_number(void *arg, u64 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct adis16480 *adis16480 = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u16 serial;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_SERIAL_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) &serial);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) *val = serial;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) DEFINE_DEBUGFS_ATTRIBUTE(adis16480_serial_number_fops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) adis16480_show_serial_number, NULL, "0x%.4llx\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int adis16480_show_product_id(void *arg, u64 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct adis16480 *adis16480 = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u16 prod_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_PROD_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) &prod_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) *val = prod_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) DEFINE_DEBUGFS_ATTRIBUTE(adis16480_product_id_fops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) adis16480_show_product_id, NULL, "%llu\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int adis16480_show_flash_count(void *arg, u64 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct adis16480 *adis16480 = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u32 flash_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ret = adis_read_reg_32(&adis16480->adis, ADIS16480_REG_FLASH_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) &flash_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) *val = flash_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) DEFINE_DEBUGFS_ATTRIBUTE(adis16480_flash_count_fops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) adis16480_show_flash_count, NULL, "%lld\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int adis16480_debugfs_init(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct adis16480 *adis16480 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct dentry *d = iio_get_debugfs_dentry(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) debugfs_create_file_unsafe("firmware_revision", 0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) d, adis16480, &adis16480_firmware_revision_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) debugfs_create_file_unsafe("firmware_date", 0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) d, adis16480, &adis16480_firmware_date_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) debugfs_create_file_unsafe("serial_number", 0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) d, adis16480, &adis16480_serial_number_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) debugfs_create_file_unsafe("product_id", 0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) d, adis16480, &adis16480_product_id_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) debugfs_create_file_unsafe("flash_count", 0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) d, adis16480, &adis16480_flash_count_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int adis16480_debugfs_init(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static int adis16480_set_freq(struct iio_dev *indio_dev, int val, int val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct adis16480 *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned int t, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (val < 0 || val2 < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) t = val * 1000 + val2 / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (t == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * When using PPS mode, the rate of data collection is equal to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * product of the external clock frequency and the scale factor in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * SYNC_SCALE register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * When using sync mode, or internal clock, the output data rate is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * equal with the clock frequency divided by DEC_RATE + 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (st->clk_mode == ADIS16480_CLK_PPS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) t = t / st->clk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) reg = ADIS16495_REG_SYNC_SCALE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) t = st->clk_freq / t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) reg = ADIS16480_REG_DEC_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (t > st->chip_info->max_dec_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) t = st->chip_info->max_dec_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if ((t != 0) && (st->clk_mode != ADIS16480_CLK_PPS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) t--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return adis_write_reg_16(&st->adis, reg, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static int adis16480_get_freq(struct iio_dev *indio_dev, int *val, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct adis16480 *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) uint16_t t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned int freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (st->clk_mode == ADIS16480_CLK_PPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) reg = ADIS16495_REG_SYNC_SCALE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) reg = ADIS16480_REG_DEC_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ret = adis_read_reg_16(&st->adis, reg, &t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * When using PPS mode, the rate of data collection is equal to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * product of the external clock frequency and the scale factor in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * SYNC_SCALE register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * When using sync mode, or internal clock, the output data rate is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * equal with the clock frequency divided by DEC_RATE + 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (st->clk_mode == ADIS16480_CLK_PPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) freq = st->clk_freq * t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) freq = st->clk_freq / (t + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) *val = freq / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) *val2 = (freq % 1000) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ADIS16480_SCAN_GYRO_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ADIS16480_SCAN_GYRO_Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ADIS16480_SCAN_GYRO_Z,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ADIS16480_SCAN_ACCEL_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ADIS16480_SCAN_ACCEL_Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ADIS16480_SCAN_ACCEL_Z,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ADIS16480_SCAN_MAGN_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ADIS16480_SCAN_MAGN_Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ADIS16480_SCAN_MAGN_Z,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ADIS16480_SCAN_BARO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ADIS16480_SCAN_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static const unsigned int adis16480_calibbias_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_BIAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_BIAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_BIAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_BIAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_BIAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_BIAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) [ADIS16480_SCAN_MAGN_X] = ADIS16480_REG_X_HARD_IRON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) [ADIS16480_SCAN_MAGN_Y] = ADIS16480_REG_Y_HARD_IRON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) [ADIS16480_SCAN_MAGN_Z] = ADIS16480_REG_Z_HARD_IRON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) [ADIS16480_SCAN_BARO] = ADIS16480_REG_BAROM_BIAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static const unsigned int adis16480_calibscale_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_SCALE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_SCALE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_SCALE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_SCALE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_SCALE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_SCALE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static int adis16480_set_calibbias(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) const struct iio_chan_spec *chan, int bias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned int reg = adis16480_calibbias_regs[chan->scan_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct adis16480 *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) case IIO_MAGN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) case IIO_PRESSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (bias < -0x8000 || bias >= 0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return adis_write_reg_16(&st->adis, reg, bias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) case IIO_ANGL_VEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) case IIO_ACCEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return adis_write_reg_32(&st->adis, reg, bias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int adis16480_get_calibbias(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) const struct iio_chan_spec *chan, int *bias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned int reg = adis16480_calibbias_regs[chan->scan_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct adis16480 *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) uint16_t val16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) uint32_t val32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) case IIO_MAGN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) case IIO_PRESSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ret = adis_read_reg_16(&st->adis, reg, &val16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) *bias = sign_extend32(val16, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) case IIO_ANGL_VEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) case IIO_ACCEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ret = adis_read_reg_32(&st->adis, reg, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) *bias = sign_extend32(val32, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static int adis16480_set_calibscale(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) const struct iio_chan_spec *chan, int scale)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) unsigned int reg = adis16480_calibscale_regs[chan->scan_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct adis16480 *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (scale < -0x8000 || scale >= 0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return adis_write_reg_16(&st->adis, reg, scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int adis16480_get_calibscale(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) const struct iio_chan_spec *chan, int *scale)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) unsigned int reg = adis16480_calibscale_regs[chan->scan_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct adis16480 *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) uint16_t val16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ret = adis_read_reg_16(&st->adis, reg, &val16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) *scale = sign_extend32(val16, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static const unsigned int adis16480_def_filter_freqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 275,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static const unsigned int adis16495_def_filter_freqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static const unsigned int ad16480_filter_data[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) [ADIS16480_SCAN_GYRO_X] = { ADIS16480_REG_FILTER_BNK0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) [ADIS16480_SCAN_GYRO_Y] = { ADIS16480_REG_FILTER_BNK0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) [ADIS16480_SCAN_GYRO_Z] = { ADIS16480_REG_FILTER_BNK0, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) [ADIS16480_SCAN_ACCEL_X] = { ADIS16480_REG_FILTER_BNK0, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) [ADIS16480_SCAN_ACCEL_Y] = { ADIS16480_REG_FILTER_BNK0, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) [ADIS16480_SCAN_ACCEL_Z] = { ADIS16480_REG_FILTER_BNK1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) [ADIS16480_SCAN_MAGN_X] = { ADIS16480_REG_FILTER_BNK1, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) [ADIS16480_SCAN_MAGN_Y] = { ADIS16480_REG_FILTER_BNK1, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) [ADIS16480_SCAN_MAGN_Z] = { ADIS16480_REG_FILTER_BNK1, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static int adis16480_get_filter_freq(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) const struct iio_chan_spec *chan, int *freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct adis16480 *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) unsigned int enable_mask, offset, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) uint16_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) reg = ad16480_filter_data[chan->scan_index][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) offset = ad16480_filter_data[chan->scan_index][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) enable_mask = BIT(offset + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ret = adis_read_reg_16(&st->adis, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (!(val & enable_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) *freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) *freq = st->chip_info->filter_freqs[(val >> offset) & 0x3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static int adis16480_set_filter_freq(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) const struct iio_chan_spec *chan, unsigned int freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct adis16480 *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct mutex *slock = &st->adis.state_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) unsigned int enable_mask, offset, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) unsigned int diff, best_diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) unsigned int i, best_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) uint16_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) reg = ad16480_filter_data[chan->scan_index][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) offset = ad16480_filter_data[chan->scan_index][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) enable_mask = BIT(offset + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) mutex_lock(slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ret = __adis_read_reg_16(&st->adis, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (freq == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) val &= ~enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) best_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) best_diff = st->chip_info->filter_freqs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) for (i = 0; i < ARRAY_SIZE(adis16480_def_filter_freqs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (st->chip_info->filter_freqs[i] >= freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) diff = st->chip_info->filter_freqs[i] - freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (diff < best_diff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) best_diff = diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) best_freq = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) val &= ~(0x3 << offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) val |= best_freq << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) val |= enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ret = __adis_write_reg_16(&st->adis, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) mutex_unlock(slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static int adis16480_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) const struct iio_chan_spec *chan, int *val, int *val2, long info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct adis16480 *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) unsigned int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return adis_single_conversion(indio_dev, chan, 0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) case IIO_ANGL_VEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) *val = st->chip_info->gyro_max_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) *val2 = st->chip_info->gyro_max_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return IIO_VAL_FRACTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) case IIO_ACCEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) *val = st->chip_info->accel_max_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) *val2 = st->chip_info->accel_max_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return IIO_VAL_FRACTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) case IIO_MAGN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) *val2 = 100; /* 0.0001 gauss */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * +85 degrees Celsius = temp_max_scale
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * +25 degrees Celsius = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * LSB, 25 degrees Celsius = 60 / temp_max_scale
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) *val = st->chip_info->temp_scale / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) *val2 = (st->chip_info->temp_scale % 1000) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) case IIO_PRESSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * max scale is 1310 mbar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * max raw value is 32767 shifted for 32bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) *val = 131; /* 1310mbar = 131 kPa */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) *val2 = 32767 << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return IIO_VAL_FRACTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /* Only the temperature channel has a offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) temp = 25 * 1000000LL; /* 25 degree Celsius = 0x0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) *val = DIV_ROUND_CLOSEST_ULL(temp, st->chip_info->temp_scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) case IIO_CHAN_INFO_CALIBBIAS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return adis16480_get_calibbias(indio_dev, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) case IIO_CHAN_INFO_CALIBSCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return adis16480_get_calibscale(indio_dev, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return adis16480_get_filter_freq(indio_dev, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return adis16480_get_freq(indio_dev, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static int adis16480_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) const struct iio_chan_spec *chan, int val, int val2, long info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) case IIO_CHAN_INFO_CALIBBIAS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return adis16480_set_calibbias(indio_dev, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) case IIO_CHAN_INFO_CALIBSCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return adis16480_set_calibscale(indio_dev, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return adis16480_set_filter_freq(indio_dev, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return adis16480_set_freq(indio_dev, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define ADIS16480_MOD_CHANNEL(_type, _mod, _address, _si, _info_sep, _bits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .type = (_type), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .modified = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .channel2 = (_mod), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) BIT(IIO_CHAN_INFO_CALIBBIAS) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) _info_sep, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .address = (_address), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .scan_index = (_si), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .sign = 's', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .realbits = (_bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .storagebits = (_bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .endianness = IIO_BE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define ADIS16480_GYRO_CHANNEL(_mod) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ADIS16480_MOD_CHANNEL(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ADIS16480_REG_ ## _mod ## _GYRO_OUT, ADIS16480_SCAN_GYRO_ ## _mod, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) BIT(IIO_CHAN_INFO_CALIBSCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define ADIS16480_ACCEL_CHANNEL(_mod) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ADIS16480_MOD_CHANNEL(IIO_ACCEL, IIO_MOD_ ## _mod, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) ADIS16480_REG_ ## _mod ## _ACCEL_OUT, ADIS16480_SCAN_ACCEL_ ## _mod, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) BIT(IIO_CHAN_INFO_CALIBSCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define ADIS16480_MAGN_CHANNEL(_mod) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ADIS16480_MOD_CHANNEL(IIO_MAGN, IIO_MOD_ ## _mod, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ADIS16480_REG_ ## _mod ## _MAGN_OUT, ADIS16480_SCAN_MAGN_ ## _mod, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define ADIS16480_PRESSURE_CHANNEL() \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .type = IIO_PRESSURE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .channel = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) BIT(IIO_CHAN_INFO_CALIBBIAS) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .address = ADIS16480_REG_BAROM_OUT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .scan_index = ADIS16480_SCAN_BARO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .sign = 's', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .realbits = 32, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .storagebits = 32, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .endianness = IIO_BE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define ADIS16480_TEMP_CHANNEL() { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .type = IIO_TEMP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .channel = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) BIT(IIO_CHAN_INFO_SCALE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) BIT(IIO_CHAN_INFO_OFFSET), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .address = ADIS16480_REG_TEMP_OUT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .scan_index = ADIS16480_SCAN_TEMP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .sign = 's', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .realbits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .endianness = IIO_BE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static const struct iio_chan_spec adis16480_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) ADIS16480_GYRO_CHANNEL(X),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) ADIS16480_GYRO_CHANNEL(Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ADIS16480_GYRO_CHANNEL(Z),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ADIS16480_ACCEL_CHANNEL(X),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ADIS16480_ACCEL_CHANNEL(Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) ADIS16480_ACCEL_CHANNEL(Z),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ADIS16480_MAGN_CHANNEL(X),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ADIS16480_MAGN_CHANNEL(Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) ADIS16480_MAGN_CHANNEL(Z),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ADIS16480_PRESSURE_CHANNEL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ADIS16480_TEMP_CHANNEL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) IIO_CHAN_SOFT_TIMESTAMP(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static const struct iio_chan_spec adis16485_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) ADIS16480_GYRO_CHANNEL(X),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) ADIS16480_GYRO_CHANNEL(Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ADIS16480_GYRO_CHANNEL(Z),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ADIS16480_ACCEL_CHANNEL(X),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) ADIS16480_ACCEL_CHANNEL(Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) ADIS16480_ACCEL_CHANNEL(Z),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ADIS16480_TEMP_CHANNEL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) IIO_CHAN_SOFT_TIMESTAMP(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) enum adis16480_variant {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) ADIS16375,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) ADIS16480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) ADIS16485,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) ADIS16488,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) ADIS16490,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) ADIS16495_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) ADIS16495_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) ADIS16495_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ADIS16497_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) ADIS16497_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ADIS16497_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define ADIS16480_DIAG_STAT_XGYRO_FAIL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define ADIS16480_DIAG_STAT_YGYRO_FAIL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define ADIS16480_DIAG_STAT_ZGYRO_FAIL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define ADIS16480_DIAG_STAT_XACCL_FAIL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define ADIS16480_DIAG_STAT_YACCL_FAIL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define ADIS16480_DIAG_STAT_ZACCL_FAIL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define ADIS16480_DIAG_STAT_XMAGN_FAIL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define ADIS16480_DIAG_STAT_YMAGN_FAIL 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define ADIS16480_DIAG_STAT_ZMAGN_FAIL 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define ADIS16480_DIAG_STAT_BARO_FAIL 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static const char * const adis16480_status_error_msgs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) [ADIS16480_DIAG_STAT_XGYRO_FAIL] = "X-axis gyroscope self-test failure",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) [ADIS16480_DIAG_STAT_YGYRO_FAIL] = "Y-axis gyroscope self-test failure",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) [ADIS16480_DIAG_STAT_ZGYRO_FAIL] = "Z-axis gyroscope self-test failure",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) [ADIS16480_DIAG_STAT_XACCL_FAIL] = "X-axis accelerometer self-test failure",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) [ADIS16480_DIAG_STAT_YACCL_FAIL] = "Y-axis accelerometer self-test failure",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) [ADIS16480_DIAG_STAT_ZACCL_FAIL] = "Z-axis accelerometer self-test failure",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) [ADIS16480_DIAG_STAT_XMAGN_FAIL] = "X-axis magnetometer self-test failure",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) [ADIS16480_DIAG_STAT_YMAGN_FAIL] = "Y-axis magnetometer self-test failure",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) [ADIS16480_DIAG_STAT_ZMAGN_FAIL] = "Z-axis magnetometer self-test failure",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) [ADIS16480_DIAG_STAT_BARO_FAIL] = "Barometer self-test failure",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static int adis16480_enable_irq(struct adis *adis, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define ADIS16480_DATA(_prod_id, _timeouts) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .diag_stat_reg = ADIS16480_REG_DIAG_STS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .glob_cmd_reg = ADIS16480_REG_GLOB_CMD, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .prod_id_reg = ADIS16480_REG_PROD_ID, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .prod_id = (_prod_id), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .has_paging = true, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .read_delay = 5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .write_delay = 5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .self_test_mask = BIT(1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .self_test_reg = ADIS16480_REG_GLOB_CMD, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .status_error_msgs = adis16480_status_error_msgs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .status_error_mask = BIT(ADIS16480_DIAG_STAT_XGYRO_FAIL) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) BIT(ADIS16480_DIAG_STAT_YGYRO_FAIL) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) BIT(ADIS16480_DIAG_STAT_ZGYRO_FAIL) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) BIT(ADIS16480_DIAG_STAT_XACCL_FAIL) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) BIT(ADIS16480_DIAG_STAT_YACCL_FAIL) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) BIT(ADIS16480_DIAG_STAT_ZACCL_FAIL) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) BIT(ADIS16480_DIAG_STAT_XMAGN_FAIL) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) BIT(ADIS16480_DIAG_STAT_YMAGN_FAIL) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) BIT(ADIS16480_DIAG_STAT_ZMAGN_FAIL) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) BIT(ADIS16480_DIAG_STAT_BARO_FAIL), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .enable_irq = adis16480_enable_irq, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .timeouts = (_timeouts), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static const struct adis_timeout adis16485_timeouts = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .reset_ms = 560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .sw_reset_ms = 120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .self_test_ms = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) static const struct adis_timeout adis16480_timeouts = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .reset_ms = 560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .sw_reset_ms = 560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .self_test_ms = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static const struct adis_timeout adis16495_timeouts = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .reset_ms = 170,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .sw_reset_ms = 130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .self_test_ms = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static const struct adis_timeout adis16495_1_timeouts = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .reset_ms = 250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .sw_reset_ms = 210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .self_test_ms = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static const struct adis16480_chip_info adis16480_chip_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) [ADIS16375] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .channels = adis16485_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .num_channels = ARRAY_SIZE(adis16485_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * Typically we do IIO_RAD_TO_DEGREE in the denominator, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) * is exactly the same as IIO_DEGREE_TO_RAD in numerator, since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) * it gives better approximation. However, in this case we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) * cannot do it since it would not fit in a 32bit variable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .gyro_max_val = 22887 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .gyro_max_scale = IIO_DEGREE_TO_RAD(300),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .accel_max_val = IIO_M_S_2_TO_G(21973 << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .accel_max_scale = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .temp_scale = 5650, /* 5.65 milli degree Celsius */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .int_clk = 2460000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .max_dec_rate = 2048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .filter_freqs = adis16480_def_filter_freqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .adis_data = ADIS16480_DATA(16375, &adis16485_timeouts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) [ADIS16480] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .channels = adis16480_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .num_channels = ARRAY_SIZE(adis16480_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .gyro_max_val = 22500 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .accel_max_val = IIO_M_S_2_TO_G(12500 << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .accel_max_scale = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .temp_scale = 5650, /* 5.65 milli degree Celsius */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .int_clk = 2460000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .max_dec_rate = 2048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .filter_freqs = adis16480_def_filter_freqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .adis_data = ADIS16480_DATA(16480, &adis16480_timeouts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) [ADIS16485] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .channels = adis16485_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .num_channels = ARRAY_SIZE(adis16485_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .gyro_max_val = 22500 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .accel_max_val = IIO_M_S_2_TO_G(20000 << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .accel_max_scale = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .temp_scale = 5650, /* 5.65 milli degree Celsius */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .int_clk = 2460000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .max_dec_rate = 2048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .filter_freqs = adis16480_def_filter_freqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .adis_data = ADIS16480_DATA(16485, &adis16485_timeouts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) [ADIS16488] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .channels = adis16480_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .num_channels = ARRAY_SIZE(adis16480_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .gyro_max_val = 22500 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .accel_max_val = IIO_M_S_2_TO_G(22500 << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .accel_max_scale = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .temp_scale = 5650, /* 5.65 milli degree Celsius */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .int_clk = 2460000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .max_dec_rate = 2048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .filter_freqs = adis16480_def_filter_freqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .adis_data = ADIS16480_DATA(16488, &adis16485_timeouts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) [ADIS16490] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .channels = adis16485_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .num_channels = ARRAY_SIZE(adis16485_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .gyro_max_val = 20000 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .gyro_max_scale = IIO_DEGREE_TO_RAD(100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .accel_max_val = IIO_M_S_2_TO_G(16000 << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .accel_max_scale = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .temp_scale = 14285, /* 14.285 milli degree Celsius */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .int_clk = 4250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .max_dec_rate = 4250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .filter_freqs = adis16495_def_filter_freqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .has_pps_clk_mode = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .adis_data = ADIS16480_DATA(16490, &adis16495_timeouts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) [ADIS16495_1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .channels = adis16485_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .num_channels = ARRAY_SIZE(adis16485_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .gyro_max_val = 20000 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .gyro_max_scale = IIO_DEGREE_TO_RAD(125),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .accel_max_scale = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .temp_scale = 12500, /* 12.5 milli degree Celsius */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .int_clk = 4250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .max_dec_rate = 4250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .filter_freqs = adis16495_def_filter_freqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .has_pps_clk_mode = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) [ADIS16495_2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .channels = adis16485_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .num_channels = ARRAY_SIZE(adis16485_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .gyro_max_val = 18000 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .accel_max_scale = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .temp_scale = 12500, /* 12.5 milli degree Celsius */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .int_clk = 4250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .max_dec_rate = 4250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .filter_freqs = adis16495_def_filter_freqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .has_pps_clk_mode = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) [ADIS16495_3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .channels = adis16485_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .num_channels = ARRAY_SIZE(adis16485_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .gyro_max_val = 20000 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .gyro_max_scale = IIO_DEGREE_TO_RAD(2000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .accel_max_scale = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .temp_scale = 12500, /* 12.5 milli degree Celsius */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .int_clk = 4250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .max_dec_rate = 4250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .filter_freqs = adis16495_def_filter_freqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .has_pps_clk_mode = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) [ADIS16497_1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .channels = adis16485_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .num_channels = ARRAY_SIZE(adis16485_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .gyro_max_val = 20000 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .gyro_max_scale = IIO_DEGREE_TO_RAD(125),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .accel_max_scale = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .temp_scale = 12500, /* 12.5 milli degree Celsius */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .int_clk = 4250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .max_dec_rate = 4250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .filter_freqs = adis16495_def_filter_freqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .has_pps_clk_mode = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) [ADIS16497_2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .channels = adis16485_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .num_channels = ARRAY_SIZE(adis16485_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .gyro_max_val = 18000 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .accel_max_scale = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .temp_scale = 12500, /* 12.5 milli degree Celsius */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .int_clk = 4250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .max_dec_rate = 4250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .filter_freqs = adis16495_def_filter_freqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .has_pps_clk_mode = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) [ADIS16497_3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .channels = adis16485_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .num_channels = ARRAY_SIZE(adis16485_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .gyro_max_val = 20000 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .gyro_max_scale = IIO_DEGREE_TO_RAD(2000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .accel_max_scale = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .temp_scale = 12500, /* 12.5 milli degree Celsius */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .int_clk = 4250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .max_dec_rate = 4250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .filter_freqs = adis16495_def_filter_freqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .has_pps_clk_mode = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) static const struct iio_info adis16480_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .read_raw = &adis16480_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .write_raw = &adis16480_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .update_scan_mode = adis_update_scan_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .debugfs_reg_access = adis_debugfs_reg_access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) static int adis16480_stop_device(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) struct adis16480 *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) ret = adis_write_reg_16(&st->adis, ADIS16480_REG_SLP_CNT, BIT(9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) dev_err(&indio_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) "Could not power down device: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) static int adis16480_enable_irq(struct adis *adis, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) uint16_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) ret = __adis_read_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) val &= ~ADIS16480_DRDY_EN_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) val |= ADIS16480_DRDY_EN(enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return __adis_write_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static int adis16480_config_irq_pin(struct device_node *of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) struct adis16480 *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) struct irq_data *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) enum adis16480_int_pin pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) unsigned int irq_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) uint16_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) int i, irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) desc = irq_get_irq_data(st->adis.spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) dev_err(&st->adis.spi->dev, "Could not find IRQ %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) /* Disable data ready since the default after reset is on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) val = ADIS16480_DRDY_EN(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) * Get the interrupt from the devicetre by reading the interrupt-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) * property. If it is not specified, use DIO1 pin as default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) * According to the datasheet, the factory default assigns DIO2 as data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) * ready signal. However, in the previous versions of the driver, DIO1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) * pin was used. So, we should leave it as is since some devices might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) * be expecting the interrupt on the wrong physical pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) pin = ADIS16480_PIN_DIO1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) irq = of_irq_get_byname(of_node, adis16480_int_pin_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) pin = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) val |= ADIS16480_DRDY_SEL(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) * Get the interrupt line behaviour. The data ready polarity can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) * configured as positive or negative, corresponding to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) * IRQ_TYPE_EDGE_RISING or IRQ_TYPE_EDGE_FALLING respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) irq_type = irqd_get_trigger_type(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (irq_type == IRQ_TYPE_EDGE_RISING) { /* Default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) val |= ADIS16480_DRDY_POL(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) } else if (irq_type == IRQ_TYPE_EDGE_FALLING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) val |= ADIS16480_DRDY_POL(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) dev_err(&st->adis.spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) "Invalid interrupt type 0x%x specified\n", irq_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) /* Write the data ready configuration to the FNCTIO_CTRL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) static int adis16480_of_get_ext_clk_pin(struct adis16480 *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) struct device_node *of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) const char *ext_clk_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) enum adis16480_int_pin pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) pin = ADIS16480_PIN_DIO2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (of_property_read_string(of_node, "adi,ext-clk-pin", &ext_clk_pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) goto clk_input_not_found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (strcasecmp(ext_clk_pin, adis16480_int_pin_names[i]) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) clk_input_not_found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) dev_info(&st->adis.spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) "clk input line not specified, using DIO2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) return pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) static int adis16480_ext_clk_config(struct adis16480 *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) struct device_node *of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) unsigned int mode, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) enum adis16480_int_pin pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) uint16_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) ret = adis_read_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) pin = adis16480_of_get_ext_clk_pin(st, of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) * Each DIOx pin supports only one function at a time. When a single pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) * has two assignments, the enable bit for a lower priority function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) * automatically resets to zero (disabling the lower priority function).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (pin == ADIS16480_DRDY_SEL(val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) dev_warn(&st->adis.spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) "DIO%x pin supports only one function at a time\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) pin + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) mode = ADIS16480_SYNC_EN(enable) | ADIS16480_SYNC_SEL(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) mask = ADIS16480_SYNC_EN_MSK | ADIS16480_SYNC_SEL_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) /* Only ADIS1649x devices support pps ext clock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (st->chip_info->has_pps_clk_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) mode |= ADIS16480_SYNC_MODE(st->clk_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) mask |= ADIS16480_SYNC_MODE_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) val |= mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) ret = adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) return clk_prepare_enable(st->ext_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) static int adis16480_get_ext_clocks(struct adis16480 *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) st->clk_mode = ADIS16480_CLK_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) st->ext_clk = devm_clk_get(&st->adis.spi->dev, "sync");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (!IS_ERR_OR_NULL(st->ext_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) st->clk_mode = ADIS16480_CLK_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (PTR_ERR(st->ext_clk) != -ENOENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) dev_err(&st->adis.spi->dev, "failed to get ext clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) return PTR_ERR(st->ext_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (st->chip_info->has_pps_clk_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) st->ext_clk = devm_clk_get(&st->adis.spi->dev, "pps");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (!IS_ERR_OR_NULL(st->ext_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) st->clk_mode = ADIS16480_CLK_PPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (PTR_ERR(st->ext_clk) != -ENOENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) dev_err(&st->adis.spi->dev, "failed to get ext clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) return PTR_ERR(st->ext_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) static void adis16480_stop(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) adis16480_stop_device(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static void adis16480_clk_disable(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) clk_disable_unprepare(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) static int adis16480_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) const struct spi_device_id *id = spi_get_device_id(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) const struct adis_data *adis16480_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) struct adis16480 *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (indio_dev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) st->chip_info = &adis16480_chip_info[id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) indio_dev->channels = st->chip_info->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) indio_dev->num_channels = st->chip_info->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) indio_dev->info = &adis16480_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) adis16480_data = &st->chip_info->adis_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) ret = adis_init(&st->adis, indio_dev, spi, adis16480_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) ret = __adis_initial_startup(&st->adis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) ret = devm_add_action_or_reset(&spi->dev, adis16480_stop, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) ret = adis16480_config_irq_pin(spi->dev.of_node, st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) ret = adis16480_get_ext_clocks(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (!IS_ERR_OR_NULL(st->ext_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) ret = adis16480_ext_clk_config(st, spi->dev.of_node, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) ret = devm_add_action_or_reset(&spi->dev, adis16480_clk_disable, st->ext_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) st->clk_freq = clk_get_rate(st->ext_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) st->clk_freq *= 1000; /* micro */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) st->clk_freq = st->chip_info->int_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) ret = devm_iio_device_register(&spi->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) adis16480_debugfs_init(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) static const struct spi_device_id adis16480_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) { "adis16375", ADIS16375 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) { "adis16480", ADIS16480 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) { "adis16485", ADIS16485 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) { "adis16488", ADIS16488 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) { "adis16490", ADIS16490 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) { "adis16495-1", ADIS16495_1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) { "adis16495-2", ADIS16495_2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) { "adis16495-3", ADIS16495_3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) { "adis16497-1", ADIS16497_1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) { "adis16497-2", ADIS16497_2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) { "adis16497-3", ADIS16497_3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) MODULE_DEVICE_TABLE(spi, adis16480_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) static const struct of_device_id adis16480_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) { .compatible = "adi,adis16375" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) { .compatible = "adi,adis16480" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) { .compatible = "adi,adis16485" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) { .compatible = "adi,adis16488" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) { .compatible = "adi,adis16490" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) { .compatible = "adi,adis16495-1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) { .compatible = "adi,adis16495-2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) { .compatible = "adi,adis16495-3" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) { .compatible = "adi,adis16497-1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) { .compatible = "adi,adis16497-2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) { .compatible = "adi,adis16497-3" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) MODULE_DEVICE_TABLE(of, adis16480_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) static struct spi_driver adis16480_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .name = "adis16480",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .of_match_table = adis16480_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .id_table = adis16480_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .probe = adis16480_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) module_spi_driver(adis16480_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) MODULE_DESCRIPTION("Analog Devices ADIS16480 IMU driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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