Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * max30102.c - Support for MAX30102 heart rate and pulse oximeter sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2017 Matt Ranostay <matt.ranostay@konsulko.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Support for MAX30105 optical particle sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2017 Peter Meerwald-Stadler <pmeerw@pmeerw.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * 7-bit I2C chip address: 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * TODO: proximity power saving feature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/iio/kfifo_buf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MAX30102_REGMAP_NAME	"max30102_regmap"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MAX30102_DRV_NAME	"max30102"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MAX30102_PART_NUMBER	0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) enum max30102_chip_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	max30102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	max30105,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) enum max3012_led_idx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	MAX30102_LED_RED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	MAX30102_LED_IR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	MAX30105_LED_GREEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define MAX30102_REG_INT_STATUS			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MAX30102_REG_INT_STATUS_PWR_RDY		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define MAX30102_REG_INT_STATUS_PROX_INT	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define MAX30102_REG_INT_STATUS_ALC_OVF		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define MAX30102_REG_INT_STATUS_PPG_RDY		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MAX30102_REG_INT_STATUS_FIFO_RDY	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define MAX30102_REG_INT_ENABLE			0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define MAX30102_REG_INT_ENABLE_PROX_INT_EN	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define MAX30102_REG_INT_ENABLE_ALC_OVF_EN	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define MAX30102_REG_INT_ENABLE_PPG_EN		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define MAX30102_REG_INT_ENABLE_FIFO_EN		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define MAX30102_REG_INT_ENABLE_MASK		0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define MAX30102_REG_INT_ENABLE_MASK_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define MAX30102_REG_FIFO_WR_PTR		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define MAX30102_REG_FIFO_OVR_CTR		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define MAX30102_REG_FIFO_RD_PTR		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define MAX30102_REG_FIFO_DATA			0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define MAX30102_REG_FIFO_DATA_BYTES		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define MAX30102_REG_FIFO_CONFIG		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define MAX30102_REG_FIFO_CONFIG_AVG_4SAMPLES	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define MAX30102_REG_FIFO_CONFIG_AVG_SHIFT	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define MAX30102_REG_FIFO_CONFIG_AFULL		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define MAX30102_REG_MODE_CONFIG		0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define MAX30102_REG_MODE_CONFIG_MODE_NONE	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define MAX30102_REG_MODE_CONFIG_MODE_HR	0x02 /* red LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define MAX30102_REG_MODE_CONFIG_MODE_HR_SPO2	0x03 /* red + IR LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define MAX30102_REG_MODE_CONFIG_MODE_MULTI	0x07 /* multi-LED mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define MAX30102_REG_MODE_CONFIG_MODE_MASK	GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define MAX30102_REG_MODE_CONFIG_PWR		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define MAX30102_REG_MODE_CONTROL_SLOT21	0x11 /* multi-LED control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define MAX30102_REG_MODE_CONTROL_SLOT43	0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define MAX30102_REG_MODE_CONTROL_SLOT_MASK	(GENMASK(6, 4) | GENMASK(2, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define MAX30102_REG_MODE_CONTROL_SLOT_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define MAX30102_REG_SPO2_CONFIG		0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define MAX30102_REG_SPO2_CONFIG_PULSE_411_US	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define MAX30102_REG_SPO2_CONFIG_SR_400HZ	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define MAX30102_REG_SPO2_CONFIG_SR_MASK	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define MAX30102_REG_SPO2_CONFIG_SR_MASK_SHIFT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define MAX30102_REG_SPO2_CONFIG_ADC_4096_STEPS	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define MAX30102_REG_SPO2_CONFIG_ADC_MASK_SHIFT	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define MAX30102_REG_RED_LED_CONFIG		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define MAX30102_REG_IR_LED_CONFIG		0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define MAX30105_REG_GREEN_LED_CONFIG		0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define MAX30102_REG_TEMP_CONFIG		0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define MAX30102_REG_TEMP_CONFIG_TEMP_EN	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define MAX30102_REG_TEMP_INTEGER		0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define MAX30102_REG_TEMP_FRACTION		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MAX30102_REG_REV_ID			0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MAX30102_REG_PART_ID			0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct max30102_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	enum max30102_chip_id chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	u8 buffer[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	__be32 processed_buffer[3]; /* 3 x 18-bit (padded to 32-bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const struct regmap_config max30102_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.name = MAX30102_REGMAP_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const unsigned long max30102_scan_masks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const unsigned long max30105_scan_masks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		BIT(MAX30105_LED_GREEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MAX30102_INTENSITY_CHANNEL(_si, _mod) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		.type = IIO_INTENSITY, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		.channel2 = _mod, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		.modified = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		.scan_index = _si, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		.scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			.sign = 'u', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			.shift = 8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			.realbits = 18, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			.storagebits = 32, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			.endianness = IIO_BE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const struct iio_chan_spec max30102_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	MAX30102_INTENSITY_CHANNEL(MAX30102_LED_RED, IIO_MOD_LIGHT_RED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	MAX30102_INTENSITY_CHANNEL(MAX30102_LED_IR, IIO_MOD_LIGHT_IR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		.type = IIO_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		.info_mask_separate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		.scan_index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const struct iio_chan_spec max30105_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	MAX30102_INTENSITY_CHANNEL(MAX30102_LED_RED, IIO_MOD_LIGHT_RED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	MAX30102_INTENSITY_CHANNEL(MAX30102_LED_IR, IIO_MOD_LIGHT_IR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	MAX30102_INTENSITY_CHANNEL(MAX30105_LED_GREEN, IIO_MOD_LIGHT_GREEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		.type = IIO_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		.info_mask_separate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		.scan_index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int max30102_set_power(struct max30102_data *data, bool en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	return regmap_update_bits(data->regmap, MAX30102_REG_MODE_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 				  MAX30102_REG_MODE_CONFIG_PWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 				  en ? 0 : MAX30102_REG_MODE_CONFIG_PWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int max30102_set_powermode(struct max30102_data *data, u8 mode, bool en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	u8 reg = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (!en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		reg |= MAX30102_REG_MODE_CONFIG_PWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	return regmap_update_bits(data->regmap, MAX30102_REG_MODE_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 				  MAX30102_REG_MODE_CONFIG_PWR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 				  MAX30102_REG_MODE_CONFIG_MODE_MASK, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MAX30102_MODE_CONTROL_LED_SLOTS(slot2, slot1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	((slot2 << MAX30102_REG_MODE_CONTROL_SLOT_SHIFT) | slot1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int max30102_buffer_postenable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	struct max30102_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	switch (*indio_dev->active_scan_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	case BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		reg = MAX30102_REG_MODE_CONFIG_MODE_HR_SPO2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	case BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	     BIT(MAX30105_LED_GREEN):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		ret = regmap_update_bits(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 					 MAX30102_REG_MODE_CONTROL_SLOT21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 					 MAX30102_REG_MODE_CONTROL_SLOT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 					 MAX30102_MODE_CONTROL_LED_SLOTS(2, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		ret = regmap_update_bits(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 					 MAX30102_REG_MODE_CONTROL_SLOT43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 					 MAX30102_REG_MODE_CONTROL_SLOT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 					 MAX30102_MODE_CONTROL_LED_SLOTS(0, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		reg = MAX30102_REG_MODE_CONFIG_MODE_MULTI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	return max30102_set_powermode(data, reg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int max30102_buffer_predisable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	struct max30102_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	return max30102_set_powermode(data, MAX30102_REG_MODE_CONFIG_MODE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 				      false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const struct iio_buffer_setup_ops max30102_buffer_setup_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	.postenable = max30102_buffer_postenable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	.predisable = max30102_buffer_predisable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static inline int max30102_fifo_count(struct max30102_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	ret = regmap_read(data->regmap, MAX30102_REG_INT_STATUS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	/* FIFO has one sample slot left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (val & MAX30102_REG_INT_STATUS_FIFO_RDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define MAX30102_COPY_DATA(i) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	memcpy(&data->processed_buffer[(i)], \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	       &buffer[(i) * MAX30102_REG_FIFO_DATA_BYTES], \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	       MAX30102_REG_FIFO_DATA_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int max30102_read_measurement(struct max30102_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 				     unsigned int measurements)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	u8 *buffer = (u8 *) &data->buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	ret = i2c_smbus_read_i2c_block_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 					    MAX30102_REG_FIFO_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 					    measurements *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 					    MAX30102_REG_FIFO_DATA_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 					    buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	switch (measurements) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		MAX30102_COPY_DATA(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		MAX30102_COPY_DATA(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		MAX30102_COPY_DATA(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	return (ret == measurements * MAX30102_REG_FIFO_DATA_BYTES) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	       0 : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static irqreturn_t max30102_interrupt_handler(int irq, void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	struct iio_dev *indio_dev = private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	struct max30102_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	unsigned int measurements = bitmap_weight(indio_dev->active_scan_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 						  indio_dev->masklength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	int ret, cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	while (cnt || (cnt = max30102_fifo_count(data)) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		ret = max30102_read_measurement(data, measurements);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		iio_push_to_buffers(data->indio_dev, data->processed_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		cnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int max30102_get_current_idx(unsigned int val, int *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	/* each step is 0.200 mA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	*reg = val / 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	return *reg > 0xff ? -EINVAL : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static int max30102_led_init(struct max30102_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	struct device *dev = &data->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	int reg, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	ret = device_property_read_u32(dev, "maxim,red-led-current-microamp", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		dev_info(dev, "no red-led-current-microamp set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		/* Default to 7 mA RED LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		val = 7000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	ret = max30102_get_current_idx(val, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		dev_err(dev, "invalid RED LED current setting %d\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	ret = regmap_write(data->regmap, MAX30102_REG_RED_LED_CONFIG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	if (data->chip_id == max30105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		ret = device_property_read_u32(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 			"maxim,green-led-current-microamp", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 			dev_info(dev, "no green-led-current-microamp set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 			/* Default to 7 mA green LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 			val = 7000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		ret = max30102_get_current_idx(val, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 			dev_err(dev, "invalid green LED current setting %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 				val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		ret = regmap_write(data->regmap, MAX30105_REG_GREEN_LED_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 				   reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	ret = device_property_read_u32(dev, "maxim,ir-led-current-microamp", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		dev_info(dev, "no ir-led-current-microamp set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		/* Default to 7 mA IR LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		val = 7000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	ret = max30102_get_current_idx(val, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		dev_err(dev, "invalid IR LED current setting %d\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	return regmap_write(data->regmap, MAX30102_REG_IR_LED_CONFIG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int max30102_chip_init(struct max30102_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	/* setup LED current settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	ret = max30102_led_init(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	/* configure 18-bit HR + SpO2 readings at 400Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	ret = regmap_write(data->regmap, MAX30102_REG_SPO2_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 				(MAX30102_REG_SPO2_CONFIG_ADC_4096_STEPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 				 << MAX30102_REG_SPO2_CONFIG_ADC_MASK_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 				(MAX30102_REG_SPO2_CONFIG_SR_400HZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 				 << MAX30102_REG_SPO2_CONFIG_SR_MASK_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 				 MAX30102_REG_SPO2_CONFIG_PULSE_411_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	/* average 4 samples + generate FIFO interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	ret = regmap_write(data->regmap, MAX30102_REG_FIFO_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 				(MAX30102_REG_FIFO_CONFIG_AVG_4SAMPLES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 				 << MAX30102_REG_FIFO_CONFIG_AVG_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 				 MAX30102_REG_FIFO_CONFIG_AFULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	/* enable FIFO interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	return regmap_update_bits(data->regmap, MAX30102_REG_INT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 				 MAX30102_REG_INT_ENABLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 				 MAX30102_REG_INT_ENABLE_FIFO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int max30102_read_temp(struct max30102_data *data, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	ret = regmap_read(data->regmap, MAX30102_REG_TEMP_INTEGER, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	*val = reg << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	ret = regmap_read(data->regmap, MAX30102_REG_TEMP_FRACTION, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	*val |= reg & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	*val = sign_extend32(*val, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int max30102_get_temp(struct max30102_data *data, int *val, bool en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	if (en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		ret = max30102_set_power(data, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	/* start acquisition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	ret = regmap_update_bits(data->regmap, MAX30102_REG_TEMP_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 				 MAX30102_REG_TEMP_CONFIG_TEMP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 				 MAX30102_REG_TEMP_CONFIG_TEMP_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	msleep(35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	ret = max30102_read_temp(data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	if (en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		max30102_set_power(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static int max30102_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 			     struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 			     int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	struct max30102_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 		 * Temperature reading can only be acquired when not in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 		 * shutdown; leave shutdown briefly when buffer not running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 		mutex_lock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 		if (!iio_buffer_enabled(indio_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 			ret = max30102_get_temp(data, val, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 			ret = max30102_get_temp(data, val, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 		mutex_unlock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 		ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 		*val = 1000;  /* 62.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 		*val2 = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 		ret = IIO_VAL_FRACTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static const struct iio_info max30102_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	.read_raw = max30102_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static int max30102_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 			  const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	struct max30102_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	struct iio_buffer *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	buffer = devm_iio_kfifo_allocate(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	if (!buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	iio_device_attach_buffer(indio_dev, buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	indio_dev->name = MAX30102_DRV_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	indio_dev->info = &max30102_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	indio_dev->modes = (INDIO_BUFFER_SOFTWARE | INDIO_DIRECT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	indio_dev->setup_ops = &max30102_buffer_setup_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	data->indio_dev = indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	data->chip_id = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	mutex_init(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	switch (data->chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	case max30105:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 		indio_dev->channels = max30105_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 		indio_dev->num_channels = ARRAY_SIZE(max30105_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 		indio_dev->available_scan_masks = max30105_scan_masks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	case max30102:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 		indio_dev->channels = max30102_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 		indio_dev->num_channels = ARRAY_SIZE(max30102_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 		indio_dev->available_scan_masks = max30102_scan_masks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	data->regmap = devm_regmap_init_i2c(client, &max30102_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	if (IS_ERR(data->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 		dev_err(&client->dev, "regmap initialization failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 		return PTR_ERR(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	/* check part ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 	ret = regmap_read(data->regmap, MAX30102_REG_PART_ID, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	if (reg != MAX30102_PART_NUMBER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 	/* show revision ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	ret = regmap_read(data->regmap, MAX30102_REG_REV_ID, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 	dev_dbg(&client->dev, "max3010x revision %02x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 	/* clear mode setting, chip shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 	ret = max30102_set_powermode(data, MAX30102_REG_MODE_CONFIG_MODE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 				     false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 	ret = max30102_chip_init(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 	if (client->irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 		dev_err(&client->dev, "no valid irq defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	ret = devm_request_threaded_irq(&client->dev, client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 					NULL, max30102_interrupt_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 					IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 					"max30102_irq", indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 		dev_err(&client->dev, "request irq (%d) failed\n", client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 	return iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static int max30102_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 	struct iio_dev *indio_dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 	struct max30102_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 	max30102_set_power(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static const struct i2c_device_id max30102_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 	{ "max30102", max30102 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 	{ "max30105", max30105 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) MODULE_DEVICE_TABLE(i2c, max30102_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static const struct of_device_id max30102_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 	{ .compatible = "maxim,max30102" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 	{ .compatible = "maxim,max30105" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) MODULE_DEVICE_TABLE(of, max30102_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static struct i2c_driver max30102_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 		.name	= MAX30102_DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 		.of_match_table	= max30102_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 	.probe		= max30102_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 	.remove		= max30102_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 	.id_table	= max30102_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) module_i2c_driver(max30102_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) MODULE_AUTHOR("Matt Ranostay <matt.ranostay@konsulko.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) MODULE_DESCRIPTION("MAX30102 heart rate/pulse oximeter and MAX30105 particle sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) MODULE_LICENSE("GPL");