Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * max30100.c - Support for MAX30100 heart rate and pulse oximeter sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2015, 2018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Matt Ranostay <matt.ranostay@konsulko.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * TODO: enable pulse length controls via device tree properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/iio/kfifo_buf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MAX30100_REGMAP_NAME	"max30100_regmap"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MAX30100_DRV_NAME	"max30100"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MAX30100_REG_INT_STATUS			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MAX30100_REG_INT_STATUS_PWR_RDY		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MAX30100_REG_INT_STATUS_SPO2_RDY	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MAX30100_REG_INT_STATUS_HR_RDY		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define MAX30100_REG_INT_STATUS_FIFO_RDY	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define MAX30100_REG_INT_ENABLE			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MAX30100_REG_INT_ENABLE_SPO2_EN		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MAX30100_REG_INT_ENABLE_HR_EN		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MAX30100_REG_INT_ENABLE_FIFO_EN		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MAX30100_REG_INT_ENABLE_MASK		0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MAX30100_REG_INT_ENABLE_MASK_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MAX30100_REG_FIFO_WR_PTR		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MAX30100_REG_FIFO_OVR_CTR		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define MAX30100_REG_FIFO_RD_PTR		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MAX30100_REG_FIFO_DATA			0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define MAX30100_REG_FIFO_DATA_ENTRY_COUNT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define MAX30100_REG_FIFO_DATA_ENTRY_LEN	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MAX30100_REG_MODE_CONFIG		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define MAX30100_REG_MODE_CONFIG_MODE_SPO2_EN	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define MAX30100_REG_MODE_CONFIG_MODE_HR_EN	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define MAX30100_REG_MODE_CONFIG_MODE_MASK	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define MAX30100_REG_MODE_CONFIG_TEMP_EN	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define MAX30100_REG_MODE_CONFIG_PWR		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define MAX30100_REG_SPO2_CONFIG		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define MAX30100_REG_SPO2_CONFIG_100HZ		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define MAX30100_REG_SPO2_CONFIG_HI_RES_EN	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define MAX30100_REG_SPO2_CONFIG_1600US		0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define MAX30100_REG_LED_CONFIG			0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define MAX30100_REG_LED_CONFIG_LED_MASK	0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define MAX30100_REG_LED_CONFIG_RED_LED_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define MAX30100_REG_LED_CONFIG_24MA		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define MAX30100_REG_LED_CONFIG_50MA		0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define MAX30100_REG_TEMP_INTEGER		0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define MAX30100_REG_TEMP_FRACTION		0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) struct max30100_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	__be16 buffer[2]; /* 2 16-bit channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static bool max30100_is_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	case MAX30100_REG_INT_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	case MAX30100_REG_MODE_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	case MAX30100_REG_FIFO_WR_PTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	case MAX30100_REG_FIFO_OVR_CTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	case MAX30100_REG_FIFO_RD_PTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	case MAX30100_REG_FIFO_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	case MAX30100_REG_TEMP_INTEGER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	case MAX30100_REG_TEMP_FRACTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static const struct regmap_config max30100_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	.name = MAX30100_REGMAP_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	.max_register = MAX30100_REG_TEMP_FRACTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	.cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.volatile_reg = max30100_is_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static const unsigned int max30100_led_current_mapping[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	4400, 7600, 11000, 14200, 17400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	20800, 24000, 27100, 30600, 33800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	37000, 40200, 43600, 46800, 50000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const unsigned long max30100_scan_masks[] = {0x3, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const struct iio_chan_spec max30100_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		.type = IIO_INTENSITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		.channel2 = IIO_MOD_LIGHT_IR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		.modified = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		.scan_index = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		.scan_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			.sign = 'u',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			.realbits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			.storagebits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			.endianness = IIO_BE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		.type = IIO_INTENSITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		.channel2 = IIO_MOD_LIGHT_RED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		.modified = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		.scan_index = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		.scan_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			.sign = 'u',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			.realbits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			.storagebits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			.endianness = IIO_BE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		.type = IIO_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		.info_mask_separate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		.scan_index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int max30100_set_powermode(struct max30100_data *data, bool state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	return regmap_update_bits(data->regmap, MAX30100_REG_MODE_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 				  MAX30100_REG_MODE_CONFIG_PWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 				  state ? 0 : MAX30100_REG_MODE_CONFIG_PWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int max30100_clear_fifo(struct max30100_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	ret = regmap_write(data->regmap, MAX30100_REG_FIFO_WR_PTR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	ret = regmap_write(data->regmap, MAX30100_REG_FIFO_OVR_CTR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	return regmap_write(data->regmap, MAX30100_REG_FIFO_RD_PTR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int max30100_buffer_postenable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	struct max30100_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	ret = max30100_set_powermode(data, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	return max30100_clear_fifo(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int max30100_buffer_predisable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	struct max30100_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	return max30100_set_powermode(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const struct iio_buffer_setup_ops max30100_buffer_setup_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.postenable = max30100_buffer_postenable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.predisable = max30100_buffer_predisable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static inline int max30100_fifo_count(struct max30100_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	ret = regmap_read(data->regmap, MAX30100_REG_INT_STATUS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	/* FIFO is almost full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if (val & MAX30100_REG_INT_STATUS_FIFO_RDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		return MAX30100_REG_FIFO_DATA_ENTRY_COUNT - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int max30100_read_measurement(struct max30100_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	ret = i2c_smbus_read_i2c_block_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 					    MAX30100_REG_FIFO_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 					    MAX30100_REG_FIFO_DATA_ENTRY_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 					    (u8 *) &data->buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	return (ret == MAX30100_REG_FIFO_DATA_ENTRY_LEN) ? 0 : ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static irqreturn_t max30100_interrupt_handler(int irq, void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	struct iio_dev *indio_dev = private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	struct max30100_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	int ret, cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	while (cnt || (cnt = max30100_fifo_count(data)) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		ret = max30100_read_measurement(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		iio_push_to_buffers(data->indio_dev, data->buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		cnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int max30100_get_current_idx(unsigned int val, int *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	/* LED turned off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (val == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		*reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	for (idx = 0; idx < ARRAY_SIZE(max30100_led_current_mapping); idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		if (max30100_led_current_mapping[idx] == val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			*reg = idx + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int max30100_led_init(struct max30100_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	struct device *dev = &data->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	unsigned int val[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	int reg, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	ret = device_property_read_u32_array(dev, "maxim,led-current-microamp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 					(unsigned int *) &val, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		/* Default to 24 mA RED LED, 50 mA IR LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		reg = (MAX30100_REG_LED_CONFIG_24MA <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			MAX30100_REG_LED_CONFIG_RED_LED_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			MAX30100_REG_LED_CONFIG_50MA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		dev_warn(dev, "no led-current-microamp set");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		return regmap_write(data->regmap, MAX30100_REG_LED_CONFIG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	/* RED LED current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	ret = max30100_get_current_idx(val[0], &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		dev_err(dev, "invalid RED current setting %d", val[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	ret = regmap_update_bits(data->regmap, MAX30100_REG_LED_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		MAX30100_REG_LED_CONFIG_LED_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		MAX30100_REG_LED_CONFIG_RED_LED_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		reg << MAX30100_REG_LED_CONFIG_RED_LED_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	/* IR LED current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	ret = max30100_get_current_idx(val[1], &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		dev_err(dev, "invalid IR current setting %d", val[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	return regmap_update_bits(data->regmap, MAX30100_REG_LED_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		MAX30100_REG_LED_CONFIG_LED_MASK, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int max30100_chip_init(struct max30100_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	/* setup LED current settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	ret = max30100_led_init(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	/* enable hi-res SPO2 readings at 100Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	ret = regmap_write(data->regmap, MAX30100_REG_SPO2_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 				 MAX30100_REG_SPO2_CONFIG_HI_RES_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 				 MAX30100_REG_SPO2_CONFIG_100HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	/* enable SPO2 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	ret = regmap_update_bits(data->regmap, MAX30100_REG_MODE_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 				 MAX30100_REG_MODE_CONFIG_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 				 MAX30100_REG_MODE_CONFIG_MODE_HR_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 				 MAX30100_REG_MODE_CONFIG_MODE_SPO2_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	/* enable FIFO interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	return regmap_update_bits(data->regmap, MAX30100_REG_INT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 				 MAX30100_REG_INT_ENABLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 				 MAX30100_REG_INT_ENABLE_FIFO_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 				 << MAX30100_REG_INT_ENABLE_MASK_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static int max30100_read_temp(struct max30100_data *data, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	ret = regmap_read(data->regmap, MAX30100_REG_TEMP_INTEGER, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	*val = reg << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	ret = regmap_read(data->regmap, MAX30100_REG_TEMP_FRACTION, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	*val |= reg & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	*val = sign_extend32(*val, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int max30100_get_temp(struct max30100_data *data, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	/* start acquisition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	ret = regmap_update_bits(data->regmap, MAX30100_REG_MODE_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 				 MAX30100_REG_MODE_CONFIG_TEMP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 				 MAX30100_REG_MODE_CONFIG_TEMP_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	msleep(35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	return max30100_read_temp(data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static int max30100_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 			     struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 			     int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	struct max30100_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		 * Temperature reading can only be acquired while engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		 * is running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		mutex_lock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		if (!iio_buffer_enabled(indio_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 			ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 			ret = max30100_get_temp(data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 			if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 				ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		mutex_unlock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		*val = 1;  /* 0.0625 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		*val2 = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		ret = IIO_VAL_FRACTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static const struct iio_info max30100_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	.read_raw = max30100_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static int max30100_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 			  const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	struct max30100_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	struct iio_buffer *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	buffer = devm_iio_kfifo_allocate(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	if (!buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	iio_device_attach_buffer(indio_dev, buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	indio_dev->name = MAX30100_DRV_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	indio_dev->channels = max30100_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	indio_dev->info = &max30100_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	indio_dev->num_channels = ARRAY_SIZE(max30100_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	indio_dev->available_scan_masks = max30100_scan_masks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	indio_dev->modes = (INDIO_BUFFER_SOFTWARE | INDIO_DIRECT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	indio_dev->setup_ops = &max30100_buffer_setup_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	data->indio_dev = indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	mutex_init(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	data->regmap = devm_regmap_init_i2c(client, &max30100_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	if (IS_ERR(data->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 		dev_err(&client->dev, "regmap initialization failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 		return PTR_ERR(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	max30100_set_powermode(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	ret = max30100_chip_init(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	if (client->irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		dev_err(&client->dev, "no valid irq defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	ret = devm_request_threaded_irq(&client->dev, client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 					NULL, max30100_interrupt_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 					IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 					"max30100_irq", indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 		dev_err(&client->dev, "request irq (%d) failed\n", client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	return iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static int max30100_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	struct iio_dev *indio_dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	struct max30100_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	max30100_set_powermode(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static const struct i2c_device_id max30100_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	{ "max30100", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) MODULE_DEVICE_TABLE(i2c, max30100_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static const struct of_device_id max30100_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	{ .compatible = "maxim,max30100" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) MODULE_DEVICE_TABLE(of, max30100_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static struct i2c_driver max30100_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 		.name	= MAX30100_DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 		.of_match_table	= max30100_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	.probe		= max30100_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	.remove		= max30100_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	.id_table	= max30100_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) module_i2c_driver(max30100_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) MODULE_AUTHOR("Matt Ranostay <matt.ranostay@konsulko.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) MODULE_DESCRIPTION("MAX30100 heart rate and pulse oximeter sensor");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) MODULE_LICENSE("GPL");