^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AFE440X Heart Rate Monitors and Low-Cost Pulse Oximeters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Andrew F. Davis <afd@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _AFE440X_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _AFE440X_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* AFE440X registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define AFE440X_CONTROL0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define AFE440X_LED2STC 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define AFE440X_LED2ENDC 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AFE440X_LED1LEDSTC 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AFE440X_LED1LEDENDC 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AFE440X_ALED2STC 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AFE440X_ALED2ENDC 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AFE440X_LED1STC 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AFE440X_LED1ENDC 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AFE440X_LED2LEDSTC 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AFE440X_LED2LEDENDC 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AFE440X_ALED1STC 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AFE440X_ALED1ENDC 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AFE440X_LED2CONVST 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AFE440X_LED2CONVEND 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AFE440X_ALED2CONVST 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AFE440X_ALED2CONVEND 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AFE440X_LED1CONVST 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AFE440X_LED1CONVEND 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AFE440X_ALED1CONVST 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AFE440X_ALED1CONVEND 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AFE440X_ADCRSTSTCT0 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AFE440X_ADCRSTENDCT0 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AFE440X_ADCRSTSTCT1 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AFE440X_ADCRSTENDCT1 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AFE440X_ADCRSTSTCT2 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AFE440X_ADCRSTENDCT2 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AFE440X_ADCRSTSTCT3 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AFE440X_ADCRSTENDCT3 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AFE440X_PRPCOUNT 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AFE440X_CONTROL1 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AFE440X_LEDCNTRL 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AFE440X_CONTROL2 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AFE440X_ALARM 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AFE440X_LED2VAL 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AFE440X_ALED2VAL 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AFE440X_LED1VAL 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AFE440X_ALED1VAL 0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AFE440X_LED2_ALED2VAL 0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AFE440X_LED1_ALED1VAL 0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AFE440X_CONTROL3 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AFE440X_PDNCYCLESTC 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AFE440X_PDNCYCLEENDC 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* CONTROL0 register fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AFE440X_CONTROL0_REG_READ BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AFE440X_CONTROL0_TM_COUNT_RST BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AFE440X_CONTROL0_SW_RESET BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* CONTROL1 register fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AFE440X_CONTROL1_TIMEREN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* TIAGAIN register fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AFE440X_TIAGAIN_ENSEPGAIN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* CONTROL2 register fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AFE440X_CONTROL2_PDN_AFE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AFE440X_CONTROL2_PDN_RX BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AFE440X_CONTROL2_DYNAMIC4 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AFE440X_CONTROL2_DYNAMIC3 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AFE440X_CONTROL2_DYNAMIC2 BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AFE440X_CONTROL2_DYNAMIC1 BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* CONTROL3 register fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AFE440X_CONTROL3_CLKDIV GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* CONTROL0 values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AFE440X_CONTROL0_WRITE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define AFE440X_CONTROL0_READ 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define AFE440X_INTENSITY_CHAN(_index, _mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .type = IIO_INTENSITY, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .channel = _index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .address = _index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .scan_index = _index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .sign = 's', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .realbits = 24, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .storagebits = 32, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .endianness = IIO_CPU, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) _mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .indexed = true, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AFE440X_CURRENT_CHAN(_index) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .type = IIO_CURRENT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .channel = _index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .address = _index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .scan_index = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .indexed = true, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .output = true, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct afe440x_val_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int integer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int fract;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define AFE440X_TABLE_ATTR(_name, _table) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static ssize_t _name ## _show(struct device *dev, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct device_attribute *attr, char *buf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ssize_t len = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) for (i = 0; i < ARRAY_SIZE(_table); i++) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06u ", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) _table[i].integer, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) _table[i].fract); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) buf[len - 1] = '\n'; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return len; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static DEVICE_ATTR_RO(_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct afe440x_attr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct device_attribute dev_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned int field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) const struct afe440x_val_table *val_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned int table_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define to_afe440x_attr(_dev_attr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) container_of(_dev_attr, struct afe440x_attr, dev_attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define AFE440X_ATTR(_name, _field, _table) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct afe440x_attr afe440x_attr_##_name = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .dev_attr = __ATTR(_name, (S_IRUGO | S_IWUSR), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) afe440x_show_register, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) afe440x_store_register), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .field = _field, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .val_table = _table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .table_size = ARRAY_SIZE(_table), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #endif /* _AFE440X_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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