Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * AFE4403 Heart Rate Monitors and Low-Cost Pulse Oximeters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *	Andrew F. Davis <afd@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/iio/trigger.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include "afe440x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define AFE4403_DRIVER_NAME		"afe4403"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /* AFE4403 Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define AFE4403_TIAGAIN			0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define AFE4403_TIA_AMB_GAIN		0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) enum afe4403_fields {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	/* Gains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	F_RF_LED1, F_CF_LED1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	F_RF_LED, F_CF_LED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	/* LED Current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	F_ILED1, F_ILED2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	/* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	F_MAX_FIELDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static const struct reg_field afe4403_reg_fields[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	/* Gains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	[F_RF_LED1]	= REG_FIELD(AFE4403_TIAGAIN, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	[F_CF_LED1]	= REG_FIELD(AFE4403_TIAGAIN, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	[F_RF_LED]	= REG_FIELD(AFE4403_TIA_AMB_GAIN, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	[F_CF_LED]	= REG_FIELD(AFE4403_TIA_AMB_GAIN, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	/* LED Current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	[F_ILED1]	= REG_FIELD(AFE440X_LEDCNTRL, 0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	[F_ILED2]	= REG_FIELD(AFE440X_LEDCNTRL, 8, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * struct afe4403_data - AFE4403 device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * @dev: Device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * @spi: SPI device handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * @regmap: Register map of the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  * @fields: Register fields of the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * @regulator: Pointer to the regulator for the IC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  * @trig: IIO trigger for this device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  * @irq: ADC_RDY line interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  * @buffer: Used to construct data layout to push into IIO buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) struct afe4403_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct regmap_field *fields[F_MAX_FIELDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	struct regulator *regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	struct iio_trigger *trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	/* Ensure suitable alignment for timestamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	s32 buffer[8] __aligned(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) enum afe4403_chan_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	LED2 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	ALED2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	LED1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	ALED1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	LED2_ALED2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	LED1_ALED1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static const unsigned int afe4403_channel_values[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	[LED2] = AFE440X_LED2VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	[ALED2] = AFE440X_ALED2VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	[LED1] = AFE440X_LED1VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	[ALED1] = AFE440X_ALED1VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	[LED2_ALED2] = AFE440X_LED2_ALED2VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	[LED1_ALED1] = AFE440X_LED1_ALED1VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const unsigned int afe4403_channel_leds[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	[LED2] = F_ILED2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	[LED1] = F_ILED1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const struct iio_chan_spec afe4403_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	/* ADC values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	AFE440X_INTENSITY_CHAN(LED2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	AFE440X_INTENSITY_CHAN(ALED2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	AFE440X_INTENSITY_CHAN(LED1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	AFE440X_INTENSITY_CHAN(ALED1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	AFE440X_INTENSITY_CHAN(LED2_ALED2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	AFE440X_INTENSITY_CHAN(LED1_ALED1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	/* LED current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	AFE440X_CURRENT_CHAN(LED2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	AFE440X_CURRENT_CHAN(LED1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const struct afe440x_val_table afe4403_res_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	{ 500000 }, { 250000 }, { 100000 }, { 50000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	{ 25000 }, { 10000 }, { 1000000 }, { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) AFE440X_TABLE_ATTR(in_intensity_resistance_available, afe4403_res_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const struct afe440x_val_table afe4403_cap_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	{ 0, 5000 }, { 0, 10000 }, { 0, 20000 }, { 0, 25000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	{ 0, 30000 }, { 0, 35000 }, { 0, 45000 }, { 0, 50000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	{ 0, 55000 }, { 0, 60000 }, { 0, 70000 }, { 0, 75000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	{ 0, 80000 }, { 0, 85000 }, { 0, 95000 }, { 0, 100000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	{ 0, 155000 }, { 0, 160000 }, { 0, 170000 }, { 0, 175000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	{ 0, 180000 }, { 0, 185000 }, { 0, 195000 }, { 0, 200000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	{ 0, 205000 }, { 0, 210000 }, { 0, 220000 }, { 0, 225000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	{ 0, 230000 }, { 0, 235000 }, { 0, 245000 }, { 0, 250000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) AFE440X_TABLE_ATTR(in_intensity_capacitance_available, afe4403_cap_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static ssize_t afe440x_show_register(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 				     struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 				     char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	struct afe4403_data *afe = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	struct afe440x_attr *afe440x_attr = to_afe440x_attr(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	unsigned int reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	int vals[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	ret = regmap_field_read(afe->fields[afe440x_attr->field], &reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (reg_val >= afe440x_attr->table_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	vals[0] = afe440x_attr->val_table[reg_val].integer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	vals[1] = afe440x_attr->val_table[reg_val].fract;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, 2, vals);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static ssize_t afe440x_store_register(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 				      struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 				      const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	struct afe4403_data *afe = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	struct afe440x_attr *afe440x_attr = to_afe440x_attr(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	int val, integer, fract, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	ret = iio_str_to_fixpoint(buf, 100000, &integer, &fract);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	for (val = 0; val < afe440x_attr->table_size; val++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		if (afe440x_attr->val_table[val].integer == integer &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		    afe440x_attr->val_table[val].fract == fract)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (val == afe440x_attr->table_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	ret = regmap_field_write(afe->fields[afe440x_attr->field], val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static AFE440X_ATTR(in_intensity1_resistance, F_RF_LED, afe4403_res_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static AFE440X_ATTR(in_intensity1_capacitance, F_CF_LED, afe4403_cap_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static AFE440X_ATTR(in_intensity2_resistance, F_RF_LED, afe4403_res_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static AFE440X_ATTR(in_intensity2_capacitance, F_CF_LED, afe4403_cap_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static AFE440X_ATTR(in_intensity3_resistance, F_RF_LED1, afe4403_res_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static AFE440X_ATTR(in_intensity3_capacitance, F_CF_LED1, afe4403_cap_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static AFE440X_ATTR(in_intensity4_resistance, F_RF_LED1, afe4403_res_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static AFE440X_ATTR(in_intensity4_capacitance, F_CF_LED1, afe4403_cap_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static struct attribute *afe440x_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	&dev_attr_in_intensity_resistance_available.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	&dev_attr_in_intensity_capacitance_available.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	&afe440x_attr_in_intensity1_resistance.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	&afe440x_attr_in_intensity1_capacitance.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	&afe440x_attr_in_intensity2_resistance.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	&afe440x_attr_in_intensity2_capacitance.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	&afe440x_attr_in_intensity3_resistance.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	&afe440x_attr_in_intensity3_capacitance.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	&afe440x_attr_in_intensity4_resistance.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	&afe440x_attr_in_intensity4_capacitance.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static const struct attribute_group afe440x_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.attrs = afe440x_attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int afe4403_read(struct afe4403_data *afe, unsigned int reg, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	u8 tx[4] = {AFE440X_CONTROL0, 0x0, 0x0, AFE440X_CONTROL0_READ};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	u8 rx[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	/* Enable reading from the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	ret = spi_write_then_read(afe->spi, &reg, 1, rx, sizeof(rx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	*val = get_unaligned_be24(&rx[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	/* Disable reading from the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	tx[3] = AFE440X_CONTROL0_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int afe4403_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			    struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			    int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	struct afe4403_data *afe = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	unsigned int reg = afe4403_channel_values[chan->address];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	unsigned int field = afe4403_channel_leds[chan->address];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	case IIO_INTENSITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			ret = afe4403_read(afe, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	case IIO_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			ret = regmap_field_read(afe->fields[field], val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			*val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			*val2 = 800000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int afe4403_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 			     struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 			     int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	struct afe4403_data *afe = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	unsigned int field = afe4403_channel_leds[chan->address];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	case IIO_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 			return regmap_field_write(afe->fields[field], val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static const struct iio_info afe4403_iio_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	.attrs = &afe440x_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	.read_raw = afe4403_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	.write_raw = afe4403_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static irqreturn_t afe4403_trigger_handler(int irq, void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	struct iio_poll_func *pf = private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	struct afe4403_data *afe = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	int ret, bit, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	u8 tx[4] = {AFE440X_CONTROL0, 0x0, 0x0, AFE440X_CONTROL0_READ};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	u8 rx[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	/* Enable reading from the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	for_each_set_bit(bit, indio_dev->active_scan_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 			 indio_dev->masklength) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		ret = spi_write_then_read(afe->spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 					  &afe4403_channel_values[bit], 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 					  rx, sizeof(rx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		afe->buffer[i++] = get_unaligned_be24(&rx[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	/* Disable reading from the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	tx[3] = AFE440X_CONTROL0_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	iio_push_to_buffers_with_timestamp(indio_dev, afe->buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 					   pf->timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const struct iio_trigger_ops afe4403_trigger_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define AFE4403_TIMING_PAIRS			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	{ AFE440X_LED2STC,	0x000050 },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	{ AFE440X_LED2ENDC,	0x0003e7 },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	{ AFE440X_LED1LEDSTC,	0x0007d0 },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	{ AFE440X_LED1LEDENDC,	0x000bb7 },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	{ AFE440X_ALED2STC,	0x000438 },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	{ AFE440X_ALED2ENDC,	0x0007cf },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	{ AFE440X_LED1STC,	0x000820 },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	{ AFE440X_LED1ENDC,	0x000bb7 },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	{ AFE440X_LED2LEDSTC,	0x000000 },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	{ AFE440X_LED2LEDENDC,	0x0003e7 },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	{ AFE440X_ALED1STC,	0x000c08 },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	{ AFE440X_ALED1ENDC,	0x000f9f },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	{ AFE440X_LED2CONVST,	0x0003ef },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	{ AFE440X_LED2CONVEND,	0x0007cf },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	{ AFE440X_ALED2CONVST,	0x0007d7 },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	{ AFE440X_ALED2CONVEND,	0x000bb7 },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	{ AFE440X_LED1CONVST,	0x000bbf },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	{ AFE440X_LED1CONVEND,	0x009c3f },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	{ AFE440X_ALED1CONVST,	0x000fa7 },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	{ AFE440X_ALED1CONVEND,	0x001387 },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	{ AFE440X_ADCRSTSTCT0,	0x0003e8 },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	{ AFE440X_ADCRSTENDCT0,	0x0003eb },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	{ AFE440X_ADCRSTSTCT1,	0x0007d0 },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	{ AFE440X_ADCRSTENDCT1,	0x0007d3 },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	{ AFE440X_ADCRSTSTCT2,	0x000bb8 },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	{ AFE440X_ADCRSTENDCT2,	0x000bbb },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	{ AFE440X_ADCRSTSTCT3,	0x000fa0 },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	{ AFE440X_ADCRSTENDCT3,	0x000fa3 },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	{ AFE440X_PRPCOUNT,	0x009c3f },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	{ AFE440X_PDNCYCLESTC,	0x001518 },	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	{ AFE440X_PDNCYCLEENDC,	0x00991f }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static const struct reg_sequence afe4403_reg_sequences[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	AFE4403_TIMING_PAIRS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	{ AFE440X_CONTROL1, AFE440X_CONTROL1_TIMEREN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	{ AFE4403_TIAGAIN, AFE440X_TIAGAIN_ENSEPGAIN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static const struct regmap_range afe4403_yes_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	regmap_reg_range(AFE440X_LED2VAL, AFE440X_LED1_ALED1VAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static const struct regmap_access_table afe4403_volatile_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	.yes_ranges = afe4403_yes_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	.n_yes_ranges = ARRAY_SIZE(afe4403_yes_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static const struct regmap_config afe4403_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	.val_bits = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	.max_register = AFE440X_PDNCYCLEENDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	.cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	.volatile_table = &afe4403_volatile_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const struct of_device_id afe4403_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	{ .compatible = "ti,afe4403", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) MODULE_DEVICE_TABLE(of, afe4403_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int __maybe_unused afe4403_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	struct iio_dev *indio_dev = spi_get_drvdata(to_spi_device(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	struct afe4403_data *afe = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	ret = regmap_update_bits(afe->regmap, AFE440X_CONTROL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 				 AFE440X_CONTROL2_PDN_AFE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 				 AFE440X_CONTROL2_PDN_AFE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	ret = regulator_disable(afe->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		dev_err(dev, "Unable to disable regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int __maybe_unused afe4403_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	struct iio_dev *indio_dev = spi_get_drvdata(to_spi_device(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	struct afe4403_data *afe = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	ret = regulator_enable(afe->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		dev_err(dev, "Unable to enable regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	ret = regmap_update_bits(afe->regmap, AFE440X_CONTROL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 				 AFE440X_CONTROL2_PDN_AFE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static SIMPLE_DEV_PM_OPS(afe4403_pm_ops, afe4403_suspend, afe4403_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static int afe4403_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	struct afe4403_data *afe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*afe));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	afe = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	afe->dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	afe->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	afe->irq = spi->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	afe->regmap = devm_regmap_init_spi(spi, &afe4403_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	if (IS_ERR(afe->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 		dev_err(afe->dev, "Unable to allocate register map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 		return PTR_ERR(afe->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	for (i = 0; i < F_MAX_FIELDS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 		afe->fields[i] = devm_regmap_field_alloc(afe->dev, afe->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 							 afe4403_reg_fields[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 		if (IS_ERR(afe->fields[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 			dev_err(afe->dev, "Unable to allocate regmap fields\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 			return PTR_ERR(afe->fields[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	afe->regulator = devm_regulator_get(afe->dev, "tx_sup");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	if (IS_ERR(afe->regulator)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 		dev_err(afe->dev, "Unable to get regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 		return PTR_ERR(afe->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	ret = regulator_enable(afe->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 		dev_err(afe->dev, "Unable to enable regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	ret = regmap_write(afe->regmap, AFE440X_CONTROL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 			   AFE440X_CONTROL0_SW_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 		dev_err(afe->dev, "Unable to reset device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 		goto err_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	ret = regmap_multi_reg_write(afe->regmap, afe4403_reg_sequences,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 				     ARRAY_SIZE(afe4403_reg_sequences));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 		dev_err(afe->dev, "Unable to set register defaults\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 		goto err_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	indio_dev->channels = afe4403_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	indio_dev->num_channels = ARRAY_SIZE(afe4403_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	indio_dev->name = AFE4403_DRIVER_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	indio_dev->info = &afe4403_iio_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	if (afe->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 		afe->trig = devm_iio_trigger_alloc(afe->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 						   "%s-dev%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 						   indio_dev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 						   indio_dev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 		if (!afe->trig) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 			dev_err(afe->dev, "Unable to allocate IIO trigger\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 			ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 			goto err_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 		iio_trigger_set_drvdata(afe->trig, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 		afe->trig->ops = &afe4403_trigger_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 		afe->trig->dev.parent = afe->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 		ret = iio_trigger_register(afe->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 			dev_err(afe->dev, "Unable to register IIO trigger\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 			goto err_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 		ret = devm_request_threaded_irq(afe->dev, afe->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 						iio_trigger_generic_data_rdy_poll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 						NULL, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 						AFE4403_DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 						afe->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 			dev_err(afe->dev, "Unable to request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 			goto err_trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 					 afe4403_trigger_handler, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 		dev_err(afe->dev, "Unable to setup buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 		goto err_trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 	ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 		dev_err(afe->dev, "Unable to register IIO device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 		goto err_buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) err_buff:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 	iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) err_trig:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 	if (afe->irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 		iio_trigger_unregister(afe->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) err_disable_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 	regulator_disable(afe->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static int afe4403_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 	struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 	struct afe4403_data *afe = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 	iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 	if (afe->irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 		iio_trigger_unregister(afe->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 	ret = regulator_disable(afe->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 		dev_err(afe->dev, "Unable to disable regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static const struct spi_device_id afe4403_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 	{ "afe4403", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) MODULE_DEVICE_TABLE(spi, afe4403_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static struct spi_driver afe4403_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 		.name = AFE4403_DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 		.of_match_table = afe4403_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 		.pm = &afe4403_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 	.probe = afe4403_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 	.remove = afe4403_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 	.id_table = afe4403_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) module_spi_driver(afe4403_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) MODULE_DESCRIPTION("TI AFE4403 Heart Rate Monitor and Pulse Oximeter AFE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) MODULE_LICENSE("GPL v2");