^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ADXRS450/ADXRS453 Digital Output Gyroscope Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2011 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ADXRS450_STARTUP_DELAY 50 /* ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* The MSB for the spi commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ADXRS450_SENSOR_DATA (0x20 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ADXRS450_WRITE_DATA (0x40 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ADXRS450_READ_DATA (0x80 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ADXRS450_RATE1 0x00 /* Rate Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ADXRS450_TEMP1 0x02 /* Temperature Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ADXRS450_LOCST1 0x04 /* Low CST Memory Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ADXRS450_HICST1 0x06 /* High CST Memory Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ADXRS450_QUAD1 0x08 /* Quad Memory Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ADXRS450_FAULT1 0x0A /* Fault Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ADXRS450_PID1 0x0C /* Part ID Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ADXRS450_SNH 0x0E /* Serial Number Registers, 4 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ADXRS450_SNL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ADXRS450_DNC1 0x12 /* Dynamic Null Correction Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Check bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ADXRS450_P 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ADXRS450_CHK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ADXRS450_CST 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ADXRS450_PWR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ADXRS450_POR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ADXRS450_NVM 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ADXRS450_Q 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ADXRS450_PLL 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ADXRS450_UV 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ADXRS450_OV 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ADXRS450_AMP 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ADXRS450_FAIL 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ADXRS450_WRERR_MASK (0x7 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ADXRS450_MAX_RX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ADXRS450_MAX_TX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ADXRS450_GET_ST(a) ((a >> 26) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ID_ADXRS450,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ID_ADXRS453,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * struct adxrs450_state - device instance specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @us: actual spi_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @buf_lock: mutex to protect tx and rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @tx: transmit buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @rx: receive buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct adxrs450_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct spi_device *us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct mutex buf_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) __be32 tx ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) __be32 rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * adxrs450_spi_read_reg_16() - read 2 bytes from a register pair
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @indio_dev: device associated with child of actual iio_dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @reg_address: the address of the lower of the two registers, which should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * an even address, the second register's address is reg_address + 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @val: somewhere to pass back the value read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int adxrs450_spi_read_reg_16(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 reg_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u16 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct adxrs450_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct spi_transfer xfers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .tx_buf = &st->tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .bits_per_word = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .len = sizeof(st->tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .cs_change = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .rx_buf = &st->rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .bits_per_word = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .len = sizeof(st->rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) mutex_lock(&st->buf_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) tx = ADXRS450_READ_DATA | (reg_address << 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (!(hweight32(tx) & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) tx |= ADXRS450_P;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) st->tx = cpu_to_be32(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) dev_err(&st->us->dev, "problem while reading 16 bit register 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) reg_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) *val = (be32_to_cpu(st->rx) >> 5) & 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) error_ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) mutex_unlock(&st->buf_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * adxrs450_spi_write_reg_16() - write 2 bytes data to a register pair
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @indio_dev: device associated with child of actual actual iio_dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @reg_address: the address of the lower of the two registers,which should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * an even address, the second register's address is reg_address + 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @val: value to be written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int adxrs450_spi_write_reg_16(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u8 reg_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct adxrs450_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) mutex_lock(&st->buf_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) tx = ADXRS450_WRITE_DATA | (reg_address << 17) | (val << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (!(hweight32(tx) & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) tx |= ADXRS450_P;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) st->tx = cpu_to_be32(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ret = spi_write(st->us, &st->tx, sizeof(st->tx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dev_err(&st->us->dev, "problem while writing 16 bit register 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) reg_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) usleep_range(100, 1000); /* enforce sequential transfer delay 0.1ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) mutex_unlock(&st->buf_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * adxrs450_spi_sensor_data() - read 2 bytes sensor data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @indio_dev: device associated with child of actual iio_dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * @val: somewhere to pass back the value read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int adxrs450_spi_sensor_data(struct iio_dev *indio_dev, s16 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct adxrs450_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct spi_transfer xfers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .tx_buf = &st->tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .bits_per_word = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .len = sizeof(st->tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .cs_change = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .rx_buf = &st->rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .bits_per_word = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .len = sizeof(st->rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) mutex_lock(&st->buf_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) st->tx = cpu_to_be32(ADXRS450_SENSOR_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dev_err(&st->us->dev, "Problem while reading sensor data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) *val = (be32_to_cpu(st->rx) >> 10) & 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) error_ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) mutex_unlock(&st->buf_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * adxrs450_spi_initial() - use for initializing procedure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * @st: device instance specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * @val: somewhere to pass back the value read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * @chk: Whether to perform fault check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int adxrs450_spi_initial(struct adxrs450_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 *val, char chk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct spi_transfer xfers = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .tx_buf = &st->tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .rx_buf = &st->rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .bits_per_word = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .len = sizeof(st->tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) mutex_lock(&st->buf_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) tx = ADXRS450_SENSOR_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (chk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) tx |= (ADXRS450_CHK | ADXRS450_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) st->tx = cpu_to_be32(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = spi_sync_transfer(st->us, &xfers, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dev_err(&st->us->dev, "Problem while reading initializing data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) *val = be32_to_cpu(st->rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) error_ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) mutex_unlock(&st->buf_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Recommended Startup Sequence by spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int adxrs450_initial_setup(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct adxrs450_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) msleep(ADXRS450_STARTUP_DELAY*2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = adxrs450_spi_initial(st, &t, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (t != 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dev_warn(&st->us->dev, "The initial power on response is not correct! Restart without reset?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) msleep(ADXRS450_STARTUP_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ret = adxrs450_spi_initial(st, &t, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) msleep(ADXRS450_STARTUP_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ret = adxrs450_spi_initial(st, &t, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (((t & 0xff) | 0x01) != 0xff || ADXRS450_GET_ST(t) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dev_err(&st->us->dev, "The second response is not correct!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ret = adxrs450_spi_initial(st, &t, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (((t & 0xff) | 0x01) != 0xff || ADXRS450_GET_ST(t) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev_err(&st->us->dev, "The third response is not correct!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ret = adxrs450_spi_read_reg_16(indio_dev, ADXRS450_FAULT1, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (data & 0x0fff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dev_err(&st->us->dev, "The device is not in normal status!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int adxrs450_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) case IIO_CHAN_INFO_CALIBBIAS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (val < -0x400 || val >= 0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ret = adxrs450_spi_write_reg_16(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ADXRS450_DNC1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int adxrs450_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) s16 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) case IIO_ANGL_VEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ret = adxrs450_spi_sensor_data(indio_dev, &t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) *val = t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ret = adxrs450_spi_read_reg_16(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ADXRS450_TEMP1, &t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) *val = (t >> 6) + 225;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) case IIO_ANGL_VEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) *val2 = 218166;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return IIO_VAL_INT_PLUS_NANO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) *val = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) *val2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) case IIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ret = adxrs450_spi_read_reg_16(indio_dev, ADXRS450_QUAD1, &t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) *val = t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) case IIO_CHAN_INFO_CALIBBIAS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ret = adxrs450_spi_read_reg_16(indio_dev, ADXRS450_DNC1, &t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) *val = sign_extend32(t, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static const struct iio_chan_spec adxrs450_channels[2][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) [ID_ADXRS450] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .type = IIO_ANGL_VEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .modified = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .channel2 = IIO_MOD_Z,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) BIT(IIO_CHAN_INFO_CALIBBIAS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) BIT(IIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .type = IIO_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) [ID_ADXRS453] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .type = IIO_ANGL_VEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .modified = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .channel2 = IIO_MOD_Z,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) BIT(IIO_CHAN_INFO_SCALE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) BIT(IIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .type = IIO_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static const struct iio_info adxrs450_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .read_raw = &adxrs450_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .write_raw = &adxrs450_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int adxrs450_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct adxrs450_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* setup the industrialio driver allocated elements */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) st->us = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) mutex_init(&st->buf_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* This is only used for removal purposes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) indio_dev->info = &adxrs450_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) indio_dev->channels =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) adxrs450_channels[spi_get_device_id(spi)->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) indio_dev->num_channels = ARRAY_SIZE(adxrs450_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) indio_dev->name = spi->dev.driver->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ret = devm_iio_device_register(&spi->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* Get the device into a sane initial state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ret = adxrs450_initial_setup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static const struct spi_device_id adxrs450_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {"adxrs450", ID_ADXRS450},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {"adxrs453", ID_ADXRS453},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) MODULE_DEVICE_TABLE(spi, adxrs450_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static struct spi_driver adxrs450_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .name = "adxrs450",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .probe = adxrs450_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .id_table = adxrs450_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) module_spi_driver(adxrs450_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) MODULE_AUTHOR("Cliff Cai <cliff.cai@xxxxxxxxxx>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) MODULE_DESCRIPTION("Analog Devices ADXRS450/ADXRS453 Gyroscope SPI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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