^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ADXRS290 SPI Gyroscope Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Nishant Malpani <nish.malpani25@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2020 Analog Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/iio/trigger.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ADXRS290_ADI_ID 0xAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ADXRS290_MEMS_ID 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ADXRS290_DEV_ID 0x92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ADXRS290_REG_ADI_ID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ADXRS290_REG_MEMS_ID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ADXRS290_REG_DEV_ID 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ADXRS290_REG_REV_ID 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ADXRS290_REG_SN0 0x04 /* Serial Number Registers, 4 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ADXRS290_REG_DATAX0 0x08 /* Roll Rate o/p Data Regs, 2 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ADXRS290_REG_DATAY0 0x0A /* Pitch Rate o/p Data Regs, 2 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ADXRS290_REG_TEMP0 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ADXRS290_REG_POWER_CTL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ADXRS290_REG_FILTER 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ADXRS290_REG_DATA_RDY 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ADXRS290_READ BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ADXRS290_TSM BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ADXRS290_MEASUREMENT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ADXRS290_DATA_RDY_OUT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ADXRS290_SYNC_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ADXRS290_SYNC(x) FIELD_PREP(ADXRS290_SYNC_MASK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ADXRS290_LPF_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ADXRS290_LPF(x) FIELD_PREP(ADXRS290_LPF_MASK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ADXRS290_HPF_MASK GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ADXRS290_HPF(x) FIELD_PREP(ADXRS290_HPF_MASK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ADXRS290_READ_REG(reg) (ADXRS290_READ | (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ADXRS290_MAX_TRANSITION_TIME_MS 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) enum adxrs290_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ADXRS290_MODE_STANDBY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ADXRS290_MODE_MEASUREMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) enum adxrs290_scan_index {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ADXRS290_IDX_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ADXRS290_IDX_Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ADXRS290_IDX_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ADXRS290_IDX_TS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct adxrs290_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Serialize reads and their subsequent processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) enum adxrs290_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int lpf_3db_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned int hpf_3db_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct iio_trigger *dready_trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Ensure correct alignment of timestamp when present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) s16 channels[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) s64 ts __aligned(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) } buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * Available cut-off frequencies of the low pass filter in Hz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * The integer part and fractional part are represented separately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const int adxrs290_lpf_3db_freq_hz_table[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) [0] = {480, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) [1] = {320, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) [2] = {160, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) [3] = {80, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) [4] = {56, 600000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) [5] = {40, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) [6] = {28, 300000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) [7] = {20, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * Available cut-off frequencies of the high pass filter in Hz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * The integer part and fractional part are represented separately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const int adxrs290_hpf_3db_freq_hz_table[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) [0] = {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) [1] = {0, 11000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) [2] = {0, 22000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) [3] = {0, 44000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) [4] = {0, 87000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [5] = {0, 175000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) [6] = {0, 350000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) [7] = {0, 700000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) [8] = {1, 400000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) [9] = {2, 800000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) [10] = {11, 300000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int adxrs290_get_rate_data(struct iio_dev *indio_dev, const u8 cmd, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct adxrs290_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) temp = spi_w8r16(st->spi, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (temp < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ret = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) *val = sign_extend32(temp, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) err_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int adxrs290_get_temp_data(struct iio_dev *indio_dev, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) const u8 cmd = ADXRS290_READ_REG(ADXRS290_REG_TEMP0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct adxrs290_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) temp = spi_w8r16(st->spi, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (temp < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ret = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* extract lower 12 bits temperature reading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) *val = sign_extend32(temp, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) err_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int adxrs290_get_3db_freq(struct iio_dev *indio_dev, u8 *val, u8 *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) const u8 cmd = ADXRS290_READ_REG(ADXRS290_REG_FILTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct adxrs290_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) short temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) temp = spi_w8r8(st->spi, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (temp < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ret = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) *val = FIELD_GET(ADXRS290_LPF_MASK, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) *val2 = FIELD_GET(ADXRS290_HPF_MASK, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) err_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int adxrs290_spi_write_reg(struct spi_device *spi, const u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) const u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) buf[0] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return spi_write_then_read(spi, buf, ARRAY_SIZE(buf), NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int adxrs290_find_match(const int (*freq_tbl)[2], const int n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) const int val, const int val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) for (i = 0; i < n; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (freq_tbl[i][0] == val && freq_tbl[i][1] == val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int adxrs290_set_filter_freq(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) const unsigned int lpf_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) const unsigned int hpf_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct adxrs290_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) val = ADXRS290_HPF(hpf_idx) | ADXRS290_LPF(lpf_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return adxrs290_spi_write_reg(st->spi, ADXRS290_REG_FILTER, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int adxrs290_set_mode(struct iio_dev *indio_dev, enum adxrs290_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct adxrs290_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int val, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (st->mode == mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ret = spi_w8r8(st->spi, ADXRS290_READ_REG(ADXRS290_REG_POWER_CTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) val = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) case ADXRS290_MODE_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) val &= ~ADXRS290_MEASUREMENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) case ADXRS290_MODE_MEASUREMENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) val |= ADXRS290_MEASUREMENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = adxrs290_spi_write_reg(st->spi, ADXRS290_REG_POWER_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dev_err(&st->spi->dev, "unable to set mode: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* update cached mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) st->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static void adxrs290_chip_off_action(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct iio_dev *indio_dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) adxrs290_set_mode(indio_dev, ADXRS290_MODE_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static int adxrs290_initial_setup(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct adxrs290_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct spi_device *spi = st->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ret = adxrs290_spi_write_reg(spi, ADXRS290_REG_POWER_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ADXRS290_MEASUREMENT | ADXRS290_TSM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) st->mode = ADXRS290_MODE_MEASUREMENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return devm_add_action_or_reset(&spi->dev, adxrs290_chip_off_action,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int adxrs290_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct adxrs290_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) unsigned int t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ret = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) case IIO_ANGL_VEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ret = adxrs290_get_rate_data(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ADXRS290_READ_REG(chan->address),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ret = adxrs290_get_temp_data(indio_dev, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) case IIO_ANGL_VEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* 1 LSB = 0.005 degrees/sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) *val2 = 87266;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return IIO_VAL_INT_PLUS_NANO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* 1 LSB = 0.1 degrees Celsius */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) *val = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) case IIO_ANGL_VEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) t = st->lpf_3db_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) *val = adxrs290_lpf_3db_freq_hz_table[t][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) *val2 = adxrs290_lpf_3db_freq_hz_table[t][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) case IIO_ANGL_VEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) t = st->hpf_3db_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) *val = adxrs290_hpf_3db_freq_hz_table[t][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) *val2 = adxrs290_hpf_3db_freq_hz_table[t][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int adxrs290_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct adxrs290_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int ret, lpf_idx, hpf_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) lpf_idx = adxrs290_find_match(adxrs290_lpf_3db_freq_hz_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ARRAY_SIZE(adxrs290_lpf_3db_freq_hz_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (lpf_idx < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* caching the updated state of the low-pass filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) st->lpf_3db_freq_idx = lpf_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* retrieving the current state of the high-pass filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) hpf_idx = st->hpf_3db_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ret = adxrs290_set_filter_freq(indio_dev, lpf_idx, hpf_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) hpf_idx = adxrs290_find_match(adxrs290_hpf_3db_freq_hz_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ARRAY_SIZE(adxrs290_hpf_3db_freq_hz_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (hpf_idx < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* caching the updated state of the high-pass filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) st->hpf_3db_freq_idx = hpf_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* retrieving the current state of the low-pass filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) lpf_idx = st->lpf_3db_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ret = adxrs290_set_filter_freq(indio_dev, lpf_idx, hpf_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static int adxrs290_read_avail(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) const int **vals, int *type, int *length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) *vals = (const int *)adxrs290_lpf_3db_freq_hz_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) *type = IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* Values are stored in a 2D matrix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) *length = ARRAY_SIZE(adxrs290_lpf_3db_freq_hz_table) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return IIO_AVAIL_LIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) *vals = (const int *)adxrs290_hpf_3db_freq_hz_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) *type = IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* Values are stored in a 2D matrix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) *length = ARRAY_SIZE(adxrs290_hpf_3db_freq_hz_table) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return IIO_AVAIL_LIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int adxrs290_reg_access_rw(struct spi_device *spi, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) unsigned int *readval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ret = spi_w8r8(spi, ADXRS290_READ_REG(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) *readval = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static int adxrs290_reg_access(struct iio_dev *indio_dev, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) unsigned int writeval, unsigned int *readval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct adxrs290_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (readval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return adxrs290_reg_access_rw(st->spi, reg, readval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return adxrs290_spi_write_reg(st->spi, reg, writeval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static int adxrs290_data_rdy_trigger_set_state(struct iio_trigger *trig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) bool state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct adxrs290_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) val = state ? ADXRS290_SYNC(ADXRS290_DATA_RDY_OUT) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ret = adxrs290_spi_write_reg(st->spi, ADXRS290_REG_DATA_RDY, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_err(&st->spi->dev, "failed to start data rdy interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static int adxrs290_reset_trig(struct iio_trigger *trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * Data ready interrupt is reset after a read of the data registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * Here, we only read the 16b DATAY registers as that marks the end of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * a read of the data registers and initiates a reset for the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) adxrs290_get_rate_data(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ADXRS290_READ_REG(ADXRS290_REG_DATAY0), &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static const struct iio_trigger_ops adxrs290_trigger_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .set_trigger_state = &adxrs290_data_rdy_trigger_set_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .validate_device = &iio_trigger_validate_own_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .try_reenable = &adxrs290_reset_trig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static irqreturn_t adxrs290_trigger_handler(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct adxrs290_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u8 tx = ADXRS290_READ_REG(ADXRS290_REG_DATAX0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* exercise a bulk data capture starting from reg DATAX0... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ret = spi_write_then_read(st->spi, &tx, sizeof(tx), st->buffer.channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) sizeof(st->buffer.channels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) goto out_unlock_notify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) iio_push_to_buffers_with_timestamp(indio_dev, &st->buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) pf->timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) out_unlock_notify:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define ADXRS290_ANGL_VEL_CHANNEL(reg, axis) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .type = IIO_ANGL_VEL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .address = reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .modified = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .channel2 = IIO_MOD_##axis, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .info_mask_shared_by_type_available = \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .scan_index = ADXRS290_IDX_##axis, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .sign = 's', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .realbits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .endianness = IIO_LE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static const struct iio_chan_spec adxrs290_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ADXRS290_ANGL_VEL_CHANNEL(ADXRS290_REG_DATAX0, X),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ADXRS290_ANGL_VEL_CHANNEL(ADXRS290_REG_DATAY0, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .type = IIO_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .address = ADXRS290_REG_TEMP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .scan_index = ADXRS290_IDX_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .scan_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .sign = 's',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .realbits = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .storagebits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .endianness = IIO_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) IIO_CHAN_SOFT_TIMESTAMP(ADXRS290_IDX_TS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static const unsigned long adxrs290_avail_scan_masks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) BIT(ADXRS290_IDX_X) | BIT(ADXRS290_IDX_Y) | BIT(ADXRS290_IDX_TEMP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static const struct iio_info adxrs290_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .read_raw = &adxrs290_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .write_raw = &adxrs290_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .read_avail = &adxrs290_read_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .debugfs_reg_access = &adxrs290_reg_access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static int adxrs290_probe_trigger(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct adxrs290_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (!st->spi->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dev_info(&st->spi->dev, "no irq, using polling\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) st->dready_trig = devm_iio_trigger_alloc(&st->spi->dev, "%s-dev%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) indio_dev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) indio_dev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (!st->dready_trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) st->dready_trig->dev.parent = &st->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) st->dready_trig->ops = &adxrs290_trigger_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) iio_trigger_set_drvdata(st->dready_trig, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ret = devm_request_irq(&st->spi->dev, st->spi->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) &iio_trigger_generic_data_rdy_poll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) IRQF_ONESHOT, "adxrs290_irq", st->dready_trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return dev_err_probe(&st->spi->dev, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) "request irq %d failed\n", st->spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) ret = devm_iio_trigger_register(&st->spi->dev, st->dready_trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) dev_err(&st->spi->dev, "iio trigger register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) indio_dev->trig = iio_trigger_get(st->dready_trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static int adxrs290_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct adxrs290_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) u8 val, val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) st->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) indio_dev->name = "adxrs290";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) indio_dev->channels = adxrs290_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) indio_dev->num_channels = ARRAY_SIZE(adxrs290_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) indio_dev->info = &adxrs290_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) indio_dev->available_scan_masks = adxrs290_avail_scan_masks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) mutex_init(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) val = spi_w8r8(spi, ADXRS290_READ_REG(ADXRS290_REG_ADI_ID));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (val != ADXRS290_ADI_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dev_err(&spi->dev, "Wrong ADI ID 0x%02x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) val = spi_w8r8(spi, ADXRS290_READ_REG(ADXRS290_REG_MEMS_ID));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (val != ADXRS290_MEMS_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) dev_err(&spi->dev, "Wrong MEMS ID 0x%02x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) val = spi_w8r8(spi, ADXRS290_READ_REG(ADXRS290_REG_DEV_ID));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (val != ADXRS290_DEV_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) dev_err(&spi->dev, "Wrong DEV ID 0x%02x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* default mode the gyroscope starts in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) st->mode = ADXRS290_MODE_STANDBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* switch to measurement mode and switch on the temperature sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ret = adxrs290_initial_setup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* max transition time to measurement mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) msleep(ADXRS290_MAX_TRANSITION_TIME_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) ret = adxrs290_get_3db_freq(indio_dev, &val, &val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) st->lpf_3db_freq_idx = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) st->hpf_3db_freq_idx = val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) &iio_pollfunc_store_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) &adxrs290_trigger_handler, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return dev_err_probe(&spi->dev, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) "iio triggered buffer setup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ret = adxrs290_probe_trigger(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return devm_iio_device_register(&spi->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static const struct of_device_id adxrs290_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) { .compatible = "adi,adxrs290" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) MODULE_DEVICE_TABLE(of, adxrs290_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static struct spi_driver adxrs290_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .name = "adxrs290",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .of_match_table = adxrs290_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .probe = adxrs290_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) module_spi_driver(adxrs290_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) MODULE_AUTHOR("Nishant Malpani <nish.malpani25@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) MODULE_DESCRIPTION("Analog Devices ADXRS290 Gyroscope SPI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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