^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Analog Devices ADF4371 SPI Wideband Synthesizer driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2019 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Registers address macro */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ADF4371_REG(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* ADF4371_REG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ADF4371_ADDR_ASC_MSK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ADF4371_ADDR_ASC(x) FIELD_PREP(ADF4371_ADDR_ASC_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ADF4371_ADDR_ASC_R_MSK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ADF4371_ADDR_ASC_R(x) FIELD_PREP(ADF4371_ADDR_ASC_R_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ADF4371_RESET_CMD 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* ADF4371_REG17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ADF4371_FRAC2WORD_L_MSK GENMASK(7, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ADF4371_FRAC2WORD_L(x) FIELD_PREP(ADF4371_FRAC2WORD_L_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ADF4371_FRAC1WORD_MSK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ADF4371_FRAC1WORD(x) FIELD_PREP(ADF4371_FRAC1WORD_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* ADF4371_REG18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ADF4371_FRAC2WORD_H_MSK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ADF4371_FRAC2WORD_H(x) FIELD_PREP(ADF4371_FRAC2WORD_H_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* ADF4371_REG1A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ADF4371_MOD2WORD_MSK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ADF4371_MOD2WORD(x) FIELD_PREP(ADF4371_MOD2WORD_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* ADF4371_REG24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ADF4371_RF_DIV_SEL_MSK GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ADF4371_RF_DIV_SEL(x) FIELD_PREP(ADF4371_RF_DIV_SEL_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* ADF4371_REG25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ADF4371_MUTE_LD_MSK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ADF4371_MUTE_LD(x) FIELD_PREP(ADF4371_MUTE_LD_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* ADF4371_REG32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ADF4371_TIMEOUT_MSK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ADF4371_TIMEOUT(x) FIELD_PREP(ADF4371_TIMEOUT_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* ADF4371_REG34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ADF4371_VCO_ALC_TOUT_MSK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ADF4371_VCO_ALC_TOUT(x) FIELD_PREP(ADF4371_VCO_ALC_TOUT_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Specifications */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ADF4371_MIN_VCO_FREQ 4000000000ULL /* 4000 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ADF4371_MAX_VCO_FREQ 8000000000ULL /* 8000 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ADF4371_MAX_OUT_RF8_FREQ ADF4371_MAX_VCO_FREQ /* Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ADF4371_MIN_OUT_RF8_FREQ (ADF4371_MIN_VCO_FREQ / 64) /* Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ADF4371_MAX_OUT_RF16_FREQ (ADF4371_MAX_VCO_FREQ * 2) /* Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ADF4371_MIN_OUT_RF16_FREQ (ADF4371_MIN_VCO_FREQ * 2) /* Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ADF4371_MAX_OUT_RF32_FREQ (ADF4371_MAX_VCO_FREQ * 4) /* Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ADF4371_MIN_OUT_RF32_FREQ (ADF4371_MIN_VCO_FREQ * 4) /* Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ADF4371_MAX_FREQ_PFD 250000000UL /* Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ADF4371_MAX_FREQ_REFIN 600000000UL /* Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* MOD1 is a 24-bit primary modulus with fixed value of 2^25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ADF4371_MODULUS1 33554432ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* MOD2 is the programmable, 14-bit auxiliary fractional modulus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ADF4371_MAX_MODULUS2 BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ADF4371_CHECK_RANGE(freq, range) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ((freq > ADF4371_MAX_ ## range) || (freq < ADF4371_MIN_ ## range))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ADF4371_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ADF4371_POWER_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ADF4371_CHANNEL_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ADF4371_CH_RF8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ADF4371_CH_RFAUX8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ADF4371_CH_RF16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ADF4371_CH_RF32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) enum adf4371_variant {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ADF4371,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ADF4372
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct adf4371_pwrdown {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const char * const adf4371_ch_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "RF8x", "RFAUX8x", "RF16x", "RF32x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static const struct adf4371_pwrdown adf4371_pwrdown_ch[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) [ADF4371_CH_RF8] = { ADF4371_REG(0x25), 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) [ADF4371_CH_RFAUX8] = { ADF4371_REG(0x72), 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) [ADF4371_CH_RF16] = { ADF4371_REG(0x25), 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) [ADF4371_CH_RF32] = { ADF4371_REG(0x25), 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const struct reg_sequence adf4371_reg_defaults[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { ADF4371_REG(0x0), 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { ADF4371_REG(0x12), 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { ADF4371_REG(0x1E), 0x48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { ADF4371_REG(0x20), 0x14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { ADF4371_REG(0x22), 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { ADF4371_REG(0x23), 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { ADF4371_REG(0x24), 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { ADF4371_REG(0x25), 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { ADF4371_REG(0x27), 0xC5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { ADF4371_REG(0x28), 0x83 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { ADF4371_REG(0x2C), 0x44 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { ADF4371_REG(0x2D), 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { ADF4371_REG(0x2E), 0x12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { ADF4371_REG(0x2F), 0x94 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { ADF4371_REG(0x32), 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { ADF4371_REG(0x35), 0xFA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { ADF4371_REG(0x36), 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { ADF4371_REG(0x39), 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { ADF4371_REG(0x3A), 0x55 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { ADF4371_REG(0x3E), 0x0C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { ADF4371_REG(0x3F), 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { ADF4371_REG(0x40), 0x50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { ADF4371_REG(0x41), 0x28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { ADF4371_REG(0x47), 0xC0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { ADF4371_REG(0x52), 0xF4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { ADF4371_REG(0x70), 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { ADF4371_REG(0x71), 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { ADF4371_REG(0x72), 0x32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const struct regmap_config adf4371_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .reg_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .read_flag_mask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct adf4371_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) const struct iio_chan_spec *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct adf4371_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct clk *clkin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * Lock for accessing device registers. Some operations require
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * multiple consecutive R/W operations, during which the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * shouldn't be interrupted. The buffers are also shared across
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * all operations so need to be protected on stand alone reads and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * writes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) const struct adf4371_chip_info *chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned long clkin_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned long fpfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned int integer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned int fract1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned int fract2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned int mod2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned int rf_div_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned int ref_div_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u8 buf[10] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static unsigned long long adf4371_pll_fract_n_get_rate(struct adf4371_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned long long val, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned int ref_div_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) val = (((u64)st->integer * ADF4371_MODULUS1) + st->fract1) * st->fpfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) tmp = (u64)st->fract2 * st->fpfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) do_div(tmp, st->mod2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) val += tmp + ADF4371_MODULUS1 / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (channel == ADF4371_CH_RF8 || channel == ADF4371_CH_RFAUX8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ref_div_sel = st->rf_div_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ref_div_sel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) do_div(val, ADF4371_MODULUS1 * (1 << ref_div_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (channel == ADF4371_CH_RF16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) val <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) else if (channel == ADF4371_CH_RF32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) val <<= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static void adf4371_pll_fract_n_compute(unsigned long long vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned long long pfd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned int *integer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned int *fract1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned int *fract2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned int *mod2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned long long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 gcd_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) tmp = do_div(vco, pfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) tmp = tmp * ADF4371_MODULUS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) *fract2 = do_div(tmp, pfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) *integer = vco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) *fract1 = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) *mod2 = pfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) while (*mod2 > ADF4371_MAX_MODULUS2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) *mod2 >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) *fract2 >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) gcd_div = gcd(*fract2, *mod2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) *mod2 /= gcd_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) *fract2 /= gcd_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int adf4371_set_freq(struct adf4371_state *st, unsigned long long freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u32 cp_bleed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u8 int_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) switch (channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) case ADF4371_CH_RF8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case ADF4371_CH_RFAUX8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (ADF4371_CHECK_RANGE(freq, OUT_RF8_FREQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) st->rf_div_sel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) while (freq < ADF4371_MIN_VCO_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) freq <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) st->rf_div_sel++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) case ADF4371_CH_RF16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* ADF4371 RF16 8000...16000 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (ADF4371_CHECK_RANGE(freq, OUT_RF16_FREQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) freq >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case ADF4371_CH_RF32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* ADF4371 RF32 16000...32000 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (ADF4371_CHECK_RANGE(freq, OUT_RF32_FREQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) freq >>= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) adf4371_pll_fract_n_compute(freq, st->fpfd, &st->integer, &st->fract1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) &st->fract2, &st->mod2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) st->buf[0] = st->integer >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) st->buf[1] = 0x40; /* REG12 default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) st->buf[2] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) st->buf[3] = st->fract1 & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) st->buf[4] = st->fract1 >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) st->buf[5] = st->fract1 >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) st->buf[6] = ADF4371_FRAC2WORD_L(st->fract2 & 0x7F) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ADF4371_FRAC1WORD(st->fract1 >> 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) st->buf[7] = ADF4371_FRAC2WORD_H(st->fract2 >> 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) st->buf[8] = st->mod2 & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) st->buf[9] = ADF4371_MOD2WORD(st->mod2 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ret = regmap_bulk_write(st->regmap, ADF4371_REG(0x11), st->buf, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * The R counter allows the input reference frequency to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * divided down to produce the reference clock to the PFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ret = regmap_write(st->regmap, ADF4371_REG(0x1F), st->ref_div_factor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ret = regmap_update_bits(st->regmap, ADF4371_REG(0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ADF4371_RF_DIV_SEL_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ADF4371_RF_DIV_SEL(st->rf_div_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) cp_bleed = DIV_ROUND_UP(400 * 1750, st->integer * 375);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) cp_bleed = clamp(cp_bleed, 1U, 255U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret = regmap_write(st->regmap, ADF4371_REG(0x26), cp_bleed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * Set to 1 when in INT mode (when FRAC1 = FRAC2 = 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * and set to 0 when in FRAC mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (st->fract1 == 0 && st->fract2 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int_mode = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ret = regmap_write(st->regmap, ADF4371_REG(0x2B), int_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return regmap_write(st->regmap, ADF4371_REG(0x10), st->integer & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static ssize_t adf4371_read(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) uintptr_t private,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct adf4371_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned long long val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned int readval, reg, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) switch ((u32)private) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case ADF4371_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) val = adf4371_pll_fract_n_get_rate(st, chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ret = regmap_read(st->regmap, ADF4371_REG(0x7C), &readval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (readval == 0x00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dev_dbg(&st->spi->dev, "PLL un-locked\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) case ADF4371_POWER_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) reg = adf4371_pwrdown_ch[chan->channel].reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) bit = adf4371_pwrdown_ch[chan->channel].bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ret = regmap_read(st->regmap, reg, &readval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) val = !(readval & BIT(bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) case ADF4371_CHANNEL_NAME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return sprintf(buf, "%s\n", adf4371_ch_names[chan->channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return ret < 0 ? ret : sprintf(buf, "%llu\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static ssize_t adf4371_write(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) uintptr_t private,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) const char *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct adf4371_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) unsigned long long freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) bool power_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) unsigned int bit, readval, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) switch ((u32)private) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) case ADF4371_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ret = kstrtoull(buf, 10, &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ret = adf4371_set_freq(st, freq, chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) case ADF4371_POWER_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ret = kstrtobool(buf, &power_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) reg = adf4371_pwrdown_ch[chan->channel].reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) bit = adf4371_pwrdown_ch[chan->channel].bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret = regmap_read(st->regmap, reg, &readval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) readval &= ~BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) readval |= (!power_down << bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ret = regmap_write(st->regmap, reg, readval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return ret ? ret : len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define _ADF4371_EXT_INFO(_name, _ident) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .read = adf4371_read, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .write = adf4371_write, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .private = _ident, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .shared = IIO_SEPARATE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static const struct iio_chan_spec_ext_info adf4371_ext_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * Ideally we use IIO_CHAN_INFO_FREQUENCY, but there are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * values > 2^32 in order to support the entire frequency range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * in Hz. Using scale is a bit ugly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) _ADF4371_EXT_INFO("frequency", ADF4371_FREQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) _ADF4371_EXT_INFO("powerdown", ADF4371_POWER_DOWN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) _ADF4371_EXT_INFO("name", ADF4371_CHANNEL_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define ADF4371_CHANNEL(index) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .type = IIO_ALTVOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .output = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .channel = index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .ext_info = adf4371_ext_info, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static const struct iio_chan_spec adf4371_chan[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ADF4371_CHANNEL(ADF4371_CH_RF8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ADF4371_CHANNEL(ADF4371_CH_RFAUX8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ADF4371_CHANNEL(ADF4371_CH_RF16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ADF4371_CHANNEL(ADF4371_CH_RF32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static const struct adf4371_chip_info adf4371_chip_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) [ADF4371] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .channels = adf4371_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) [ADF4372] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .channels = adf4371_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .num_channels = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static int adf4371_reg_access(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) unsigned int writeval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) unsigned int *readval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct adf4371_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (readval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return regmap_read(st->regmap, reg, readval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return regmap_write(st->regmap, reg, writeval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static const struct iio_info adf4371_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .debugfs_reg_access = &adf4371_reg_access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int adf4371_setup(struct adf4371_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) unsigned int synth_timeout = 2, timeout = 1, vco_alc_timeout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) unsigned int vco_band_div, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* Perform a software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ret = regmap_write(st->regmap, ADF4371_REG(0x0), ADF4371_RESET_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ret = regmap_multi_reg_write(st->regmap, adf4371_reg_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ARRAY_SIZE(adf4371_reg_defaults));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* Mute to Lock Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (device_property_read_bool(&st->spi->dev, "adi,mute-till-lock-en")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ret = regmap_update_bits(st->regmap, ADF4371_REG(0x25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ADF4371_MUTE_LD_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ADF4371_MUTE_LD(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* Set address in ascending order, so the bulk_write() will work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ret = regmap_update_bits(st->regmap, ADF4371_REG(0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ADF4371_ADDR_ASC_MSK | ADF4371_ADDR_ASC_R_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ADF4371_ADDR_ASC(1) | ADF4371_ADDR_ASC_R(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * Calculate and maximize PFD frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * fPFD = REFIN × ((1 + D)/(R × (1 + T)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * Where D is the REFIN doubler bit, T is the reference divide by 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * R is the reference division factor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * TODO: it is assumed D and T equal 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) st->ref_div_factor++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) st->fpfd = st->clkin_freq / st->ref_div_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) } while (st->fpfd > ADF4371_MAX_FREQ_PFD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* Calculate Timeouts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) vco_band_div = DIV_ROUND_UP(st->fpfd, 2400000U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) tmp = DIV_ROUND_CLOSEST(st->fpfd, 1000000U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) timeout++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (timeout > 1023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) timeout = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) synth_timeout++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) } while (synth_timeout * 1024 + timeout <= 20 * tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) vco_alc_timeout++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) } while (vco_alc_timeout * 1024 - timeout <= 50 * tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) st->buf[0] = vco_band_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) st->buf[1] = timeout & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) st->buf[2] = ADF4371_TIMEOUT(timeout >> 8) | 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) st->buf[3] = synth_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) st->buf[4] = ADF4371_VCO_ALC_TOUT(vco_alc_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return regmap_bulk_write(st->regmap, ADF4371_REG(0x30), st->buf, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static void adf4371_clk_disable(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct adf4371_state *st = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) clk_disable_unprepare(st->clkin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static int adf4371_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) const struct spi_device_id *id = spi_get_device_id(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct adf4371_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) regmap = devm_regmap_init_spi(spi, &adf4371_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) dev_err(&spi->dev, "Error initializing spi regmap: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) PTR_ERR(regmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) st->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) st->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) mutex_init(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) st->chip_info = &adf4371_chip_info[id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) indio_dev->name = id->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) indio_dev->info = &adf4371_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) indio_dev->channels = st->chip_info->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) indio_dev->num_channels = st->chip_info->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) st->clkin = devm_clk_get(&spi->dev, "clkin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (IS_ERR(st->clkin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return PTR_ERR(st->clkin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ret = clk_prepare_enable(st->clkin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ret = devm_add_action_or_reset(&spi->dev, adf4371_clk_disable, st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) st->clkin_freq = clk_get_rate(st->clkin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) ret = adf4371_setup(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) dev_err(&spi->dev, "ADF4371 setup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return devm_iio_device_register(&spi->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static const struct spi_device_id adf4371_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) { "adf4371", ADF4371 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) { "adf4372", ADF4372 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) MODULE_DEVICE_TABLE(spi, adf4371_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static const struct of_device_id adf4371_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) { .compatible = "adi,adf4371" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) { .compatible = "adi,adf4372" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) MODULE_DEVICE_TABLE(of, adf4371_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static struct spi_driver adf4371_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .name = "adf4371",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .of_match_table = adf4371_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .probe = adf4371_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .id_table = adf4371_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) module_spi_driver(adf4371_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) MODULE_DESCRIPTION("Analog Devices ADF4371 SPI PLL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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